This is information on a product in full production.
December 2014 DocID15028 Rev 6 1/31
VIPER28
Peak power high-voltage converter - VIPer Plus
Datasheet
-
production data
Figure 1. Typical application
Features
800 V avalanche-rugged power MOSFET
allowing achieving ultra wide-range input V
ac
Embedded HV startup and sense FET
PWM current-mod e control le r
OCP with selectable threshold (I
Dlim
) and 2
nd
OCP with higher value (I
DMAX
) to protect the IC
from transformer saturation or short-circuit of
the secondary diode
30 mW no-load consumption at 230 V
ac
Two operating frequencies:
60 kHz (L type) or 115 kHz (H type)
Jittered frequency reduces the EMI
Extra power timer (EPT) blanks the overload
current for few seconds
Output overvoltage protection with tight
tolerance and digital noise filter
Soft-start reduces the stress during startup and
increases IC lifetime
Automatic restart after a fault condition
Thermal shutdown increases system reliability
and IC lifetime
Applications
Auxiliary power supply for consumer and home
equipment
Power supply for energy meters and data
concentrators
AC-DC adapters
Description
The device is a high-voltage converter that
smartly integrates an 800 V rugged power
MOSFET with PWM current-mode control.This IC
is capable of meeting more stringent energy-
saving standards as it has very low consumption
and operates in burst mode under light load. The
device features an adjustable extra power timer
(EPT) that enables the IC to sustain overload
conditions for a few seconds. The integrated HV
startup, sense FET and oscillator with jitter allow
the advantage of using minimal components in
the application. The device features high-level
protections like dual-level OCP, output
overvoltage, short-circuit, and thermal shutdown
with hysteresis. After the removal of a fault
condition, the IC is automatically restarted.
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Table 1. Device summary
Order codes Package Packaging
VIPER28LN /
VIPER28HN DIP-7 Tube
VIPER28HD /
VIPER28LD SO16 narrow
VIPER28HDTR /
VIPER28LDTR Tape and reel
www.st.com
Contents VIPER28
2/31 DocID15028 Rev 6
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Elect rical char acteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2 High-voltage start up ge nerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3 Power-up and soft startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5 Auto- restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7 Current mode conversion with adj ustable current limit set point . . . . . . . . 18
7.8 Overvol tage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.10 Feedback and overload protecti on (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20
7.11 Burst-mode operation at no load or very l ight load . . . . . . . . . . . . . . . . . . 23
7.12 Extra power timer (EPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 25
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1 DIP-7 package informati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2 SO16 Narrow package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID15028 Rev 6 3/31
VIPER28 List of tables
31
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Avalanche ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 9. Controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. CONT pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. DIP-7 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. SO16 Narrow mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
List of figures VIPER28
4/31 DocID15028 Rev 6
List of figures
Figure 1. Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Connection diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Minimum turn-on time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. OVP threshold test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. I
Dlim
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. F
OSC
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. V
DRAIN_START
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. I
DD0
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. I
DD1
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Main FET R
DSON
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12. Main FET V
BVDSS
vs. T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. I
Dlim
vs. R
LIM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. Basic flyback application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. Full-featured flyback application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. IDD current during startup and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Soft-start: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20. Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. OVP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. CONT pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. FB pin configuration (option 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. FB pin configuration (option 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Burst mode timing diagram, light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. EPT timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. DIP-7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 28. SO16 narrow package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DocID15028 Rev 6 5/31
VIPER28 Block diagram
31
1 Block diagram
Figure 2. Block diagram
2 Typical power
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Table 2. Typical power
Nominal power 230 V
AC
85-265 V
AC
Adapter
(1)
Open frame
(2)
Adapter
(1)
Open frame
(2)
VIPER28xD/xN 13 W 16 W 10 W 12 W
22 W (peak)
(3)
26 W (peak)
(3)
17 W (peak)
(3)
20 W (peak)
(3)
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.
3. Maximum practical peak power at 50 °C ambient, with adequate heat sinking for 2 sec (max).
Pin settings VIPER28
6/31 DocID15028 Rev 6
3 Pin settings
Figure 3. Connection diagram (top view)
Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
Table 3. Pin description
SO16N Name Function
1, 2 GND This pin represents the device ground and the source of the power section.
3 N.C. Not connected.
4N.A.
Not available for user. This pin is mechanically connected to the
controller die pad of the frame. In order to improve the noise immunity,
is highly recommended connect it to GND (pin 1-2).
5VDD
Supply voltage of the control section. This pin also provides the charging
current of the external capacitor during startup.
6CONT
Control pin. The following functions can be selected:
1. current limit setpoint adjustment. The default value (set internally) of the cycle-
by-cycl e curren t limit can be re duced by co nnecti ng a n exter nal res istor to ground.
2. output voltage monitoring. A voltage exceeding the V
OVP
threshold (see
Table 9: Controller section on page 9) shuts the IC down, reducing device
consump tio n. Thi s fu nc tion is s trobed and di gitally fi ltered for hig h noi se imm un ity.
7FB
Control input for duty cycle control. The internal current generator provides bias
current for loop regulation. A voltage below the threshold V
FBbm
activates burst-
mode operation. A level close to the threshold V
FBlin
means that we are
approachi ng the cy cl e-by -c yc le ove r cu rren t setpo in t.
8EPT
This pin allows the connection of an external capacitor for extra power
management. If the function is not used, the pin has to be connected to GND.
9...12 N.C. Not connected.
13...16 DRAIN High-voltage drain pin. The built-in high-voltage switched startup bias current is
drawn from this pin too. These pins are connected to the metal frame to facilitate
heat dissipation.
DocID15028 Rev 6 7/31
VIPER28 Electrical ratings
31
4 Electrical ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
Min Max
V
DRAIN
Drain-to-source (ground) voltage 800 V
I
DRAIN
Pulse drain current (limited by T
J
= 150 °C) 3 A
V
CONT
Control input pin voltage -0.3 6 V
V
FB
Feedbac k voltag e -0.3 5.5 V
V
EPT
EPT input pin voltage -0.3 5 V
V
DD
Supply voltage (I
DD
= 25 mA) -0.3 Self limited V
I
DD
Input current 25 mA
P
TOT
Power dissipation at T
A
< 40 °C (DIP-7) 1 W
Power dissipation at T
A
< 60 °C (SO16N) 1.5
T
J
Operati ng jun cti on tem perature range -40 150 °C
T
STG
Storage tempera ture -55 150 °C
HBM
(ESD)
Human body model 2 kV
ESD
(CDM)
Charge device mode 1.5
Table 5. Thermal ratings
Symbol Parameter Max value Unit
SO16N DIP7
R
thJP
Thermal resistance junction pin
(dissipated power = 1 W) 35 35 °C/W
R
thJA
Thermal resistance junction ambient
(dissipated power = 1 W) 105 110 °C/W
R
thJA
Thermal resistance junction ambient
(1)
(dissipated power = 1 W)
1. When mounted on a standard single side FR4 board with 100 mm
2
(0.155 sq inch) of Cu (35 µm thick)
80 90 °C/W
Table 6. Avalanche ratings
Symbol Parameter Test condition Value Unit
I
AS
Av ala nc he cu rrent Repetitive or non repetitive
(pulse width limited by T
Jmax
)1A
E
AS
Single pulse avalanche
energy
(1)
1. This parameter is derived from characterization data.
I
D
= I
AS
, V
DS
=100 V
starting T
J
= 25°C 3mJ
Electrical ratings VIPER28
8/31 DocID15028 Rev 6
4.1 Electrical characteristics
T
J
= -25 to 125 °C, V
DD
= 14 V; unless otherwise specified (adjust V
DD
above V
DDon
startup
threshold before setting to 14 V).
Table 7. Power section
Symbol Parameter Test condition Min Typ Max Unit
V
BVDSS
Breakdown voltage I
DRAIN
= 1 mA, V
FB
= GND, T
J
= 25 °C 800 V
I
OFF
OFF-state drain current
V
DRAIN
= max rating,V
FB
= GND, T
J
= 25°C 60 µA
R
DS(on)
Drain-source on-state
resistance I
DRAIN
= 0.4 A, V
FB
= 3 V, V
EPT
= GND, T
J
= 25 °C 7
I
DRAIN
= 0.4 A, V
FB
= 3 V, V
EPT
= GND, T
J
= 125 °C 14
C
OSS
Effective (energy related)
output capacit a nc e
V
DRAIN
= 0 to 640 V, T
J
= 25°C 40 pF
Table 8. Supply section
Symbol Parameter Test condition Min Typ Max Unit
Voltage
V
DRAIN_START Drain-source start voltage 60 80 100 V
IDDch1 Start up cha r gi ng current
V
DRAIN
= 120 V, V
EPT
= GND,
V
FB
= GND, V
DD
= 4 V -2 -3 -4 mA
I
DDch2
Restar t charging cur rent
(after faul t)
V
DRAIN
= 120 V, V
EPT
= GND,
V
FB
= GND, V
DD
= 5 V -0.4 -0.6 -0.8 mA
V
DD
Operating voltage range After turn-on 8.5 23.5 V
V
DDclamp
V
DD
clamp voltage I
DD
= 20 mA 23.5 V
V
DDon
V
DD
startup threshold
V
DRAIN
= 120 V, V
EPT
= GND,
V
FB
= GND
13 14 15 V
V
DDoff
V
DD
undervoltage shutdown
threshold 7.588.5V
V
DD(RESTART)
V
DD
restart voltage threshold
V
DRAIN
= 120 V, V
EPT
= GND,
V
FB
= GND 44.55 V
Current
I
DD0
Operating supply current, not
switching V
FB
= GND, F
OSC
= 0 kHz
V
EPT
= GND, V
DD
= 10 V 0.9 mA
I
DD1
Operating supply current,
switching
V
DRAIN
= 120 V, F
OSC
= 60 kHz 2.5 mA
V
DRAIN
= 120 V,F
OSC
= 115 kHz 3.5 mA
I
DD_FAULT
Operating supply current, with
protection tripping V
DD
= 10 V 400 uA
I
DD_OFF
Operating supply current with
V
DD
< V
DD_OFF
V
DD
= 7 V 270 uA
DocID15028 Rev 6 9/31
VIPER28 Electrical ratings
31
Table 9. Controller section
Symbol Parameter Test condition Min Typ Max Unit
Feed-back pin
V
FBolp
Overload shutdown threshold 4.5 4.8 5.2 V
V
FBlin
Overload detection threshold 3.2 3.5 3.7 V
V
FBbm
Burst mode threshold Voltage falling 0.54 0.6 0.66 V
V
FBbmhys
Burst mode hysteresis Voltage rising 100 mV
I
FB1
Feedback sourced current V
FB
= 0.3 V -150 -200 -280 uA
I
FB2
Feedback current-OLP
delay V
FBlin
< V
FB
< V
FBolp
-3 uA
R
FB(DYN)
Dynamic resistance V
FB
< 3.3 V 14 20 k
H
FB
V
FB
/ I
D
(1)
T
J
= 25 °C 2 6 V/A
CONT pin
V
CONT_l
Low-level clamp voltage I
CONT
= -100 µA 0.4 0 .5 0.6 V
V
CONT_h
High-level clamp voltage I
CONT
= 1 mA 5 5.5 6 V
Current limitation
I
Dlim
Max drain current limitation V
FB
= 4 V, I
CONT
= -10 µA
T
J
= 25 °C 0.75 0.80 0.85 A
t
SS
Soft-start time 7.6 8 .5 9.4 ms
T
ON_MIN
Minimum turn-on time 220 370 480 ns
td Propagation dela y 100 ns
t
LEB
Leading edge blankin g
(1)
300 ns
I
D_BM
Peak dra in current during burst
mode V
FB
= 0.6 V 160 mA
Oscillator section
F
OSC
V
FB
= 1 V VIPER28L 54 60 66 kHz
VIPER28H 103 115 127 kHz
FD Modulati on depth VIPER28L ±4 kHz
VIPER28H ±8 kHz
FM Mo dul ati on freq uen cy 200 250 300 Hz
D
MAX
Maximum duty cycle 70 80 %
Overcurrent protection (2
nd
OCP)
I
DMAX
Second overcurrent threshold
(1)
1.2 A
Overvoltage protection
V
OVP
Overvoltage protection threshold 2.7 3 3.3 V
Electrical ratings VIPER28
10/31 DocID15028 Rev 6
Figure 4. Minimum turn-on time test circuit
Figure 5. OVP threshold te st circuit
Note: Adjust V
DD
above V
DDon
startup threshold before setting to 14 V.
t
STROBE
Overvoltage protection strobe
time 2.2 µs
Extra power management
I
DLIM_EPT
Drain current limit with EPT
function
(1)
85%
I
Dlim
A
V
EPT(STOP)
EPT shutdown threshold
I
CONT
< -10 µA
3.6 4 4.4 V
V
EPT(RESTART)
EPT restart threshold 0.4 0.6 0.8 V
I
EPT
Sink/source current 4 5 6 µA
Thermal shutdown
T
SD
Thermal shutdown temperature
(1)
150 160 °C
T
HYST
Thermal shutdown hysteresis
(1)
30 °C
1. S pecification guaranteed by characterization.
Table 9. Controller section (continued)
Symbol Parameter Test condition Min Typ Max Unit
14 V
3.5 V
50 Ω
30 V
GND
CONT
FB
VDD
DRAIN
EPT
DRAIN
VDRAIN
IDRAIN
IDLIM
Time
Time
TONmin
90 %
10 %
GND
CONT
FB
VDD
DRAIN
EPT
DRAIN
VOVP
VCONT
VDRAIN
14 V
2 V
10 kW
30 V
Time
Time
DocID15028 Rev 6 11/31
VIPER28 Typical electrical characteristics
31
5 Typical electrical characteristics
Figure 6. I
Dlim
vs. T
J
Figure 7. F
OSC
vs. T
J
AM13881V1
IDLIM/(IDLIM@25°C)
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vs. T
J
Figure 9. I
DD0
vs. T
J
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Figure 11. Main FET R
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12/31 DocID15028 Rev 6
Figure 14. Thermal shutdown
Figure 12. Main FET V
BVDSS
vs. T
J
Figure 13. I
Dlim
vs. R
LIM
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VIPER28 Typi cal circ u it
31
6 Typical circuit
Figure 15. Basic flyback application
Figure 16. Full-featured flyback application
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Operation VIPER28
14/31 DocID15028 Rev 6
7 Operation
The device
is a high-performance low-voltage PWM controller chip with an 800 V, avalanche
rugged power section.
The controller includes the oscillator with jitter, startup circuit with soft-start, PWM logic,
current limiting circuit with adjustable setpoint, second overcurrent circuit, burst mode
management, Extra Power Timer circuit, UVLO circuit, auto-restart circuit and thermal
protection circuit.
The current limit setpoint is set by the CONT pin. Burst mode operation guarantees high
performance in standby mode and contributes to meeting energy-saving standards.
All the fault protections are built in auto-restart mode with very low repetition rate to prevent
the IC from overheating.
7.1 Power section and gate driver
The power section is implemented with an avalanche-rugged N-channel MOSFET, which
guarantees safe operation within the specified energy rating as well as high dv/dt capability.
The power section has a B
VDSS
of 800 V min. and a maximum R
DS(on)
of 7 at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common-mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power section cannot be turned on
accidentally.
7.2 High-voltage startup generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than the V
DRAIN_START
threshold, 80 V DC typically.
When the HV current generator is ON, the I
DDch1
current (3 mA typical value) is delivered to
the capacitor on the V
DD
pin. During auto-restart mode after a fault event, the current is
reduced to I
DDch2
(0.6 mA, typ) in order to have a slow duty cycle during the restart phase.
7.3 Power-up and soft startup
When the input voltage rises to the device start threshold, V
DRAIN_START
, the VDD voltage
begins to grow due to the I
DDch1
current (see Table 8: Supply section) coming from the
internal high-voltage startup circuit. If the VDD voltage reaches the V
DDon
threshold, the
power MOSFET starts switching and the HV current generator is turned OFF.
The IC is powered by the energy stored in the capacitor on the VDD pin, C
VDD
, until the self-
supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
The C
VDD
capacitor must be correctly sized to avoid fast discharge and keep the required
voltage higher than the V
DDoff
threshold. In fact, an insufficient capacitance value could
terminate the switching operation before the controller receives any energy from the
auxiliary winding.
DocID15028 Rev 6 15/31
VIPER28 Operation
31
The following formula can be used for the C
VDD
capacitor calculation:
Equation 1
The parameter t
SSaux
is the time needed for the steady state of the auxiliary voltage. This
time represents an estimate of the users application according to the output stage
configurations (transformer, output capacitances, etc.).
During the converter startup time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of the startup converter or after a fault.
Figure 17. I
DD
current during startup and burst mode
C
VDD
I
DDch1
t
SSaux
×
V
DDon
V
DDoff
-----------------------------------------=
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16/31 DocID15028 Rev 6
Figure 18. Timing diagram: normal power-up and power-down sequences
Figure 19. Soft-start: timing diagram
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VIPER28 Operation
31
7.4 Power-down
At converter power-down, the system loses its ability to regulate as soon as the decreasing
input voltage is low enough for the peak current limitation to be reached. The VDD voltage
drops and when it falls below the V
DDoff
threshold (see Table 8: Supply section) the power
MOSFET is switched OFF, the energy transfers to the IC is interrupted and, consequently,
the VDD voltage decreases (Table 19: Soft-start: timing diagram), the startup sequence is
inhibited and the power-down is completed. This feature is useful as it prevents the
converter from attempting a restart and ensures monotonic output voltage decay during
system power-down.
7.5 Auto-restart
Every time a protection is tripped, the IC is automatically restarted after a duration that
depends on the discharge and recharge of the C
VDD
cap a ci to r. As s how n in Figure 20, after
a fault the IC is stopped and, consequently, the V
DD
voltage decreases because of the IC's
consumption. As soon as the V
DD
voltage falls below the threshold V
DD(RESTART)
and if the
DC input voltage is higher than V
DRAIN_START
threshold, the internal HV current source is
turned ON and it starts to charge the C
VDD
capacitor with the current I
DDch2
(0.6 mA, typ).
As soon as the V
DD
voltage rea ches the thr es hol d V
DD(ON)
, the IC restarts.
Figure 20. Timing diagram: behavior after short-circuit
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18/31 DocID15028 Rev 6
7.6 Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both cases the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz
version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the
energy of each harmonic of the switching frequency over a number of side-band harmonics
having the same energy on the whole, but smaller amplitudes.
7.7 Current mode conversion with adjustable current limit
setpoint
The device is a current mode converter. The drain current is sensed and converted to
voltage that is applied to the non-inverting pin of the PWM comparator. This voltage is
compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle
basis.
The device has a default current limit value, I
Dlim
, that can be adjusted according to the
electrical specification, by the R
LIM
resistor connected to the CONT pin.
The CONT pin has a minimum current sunk needed to activate the I
Dlim
adjustment. Without
R
LIM
or with high R
LIM
(i.e. 100 k) the current limit is set to the default value (see I
Dlim
,
Table 9: Controller section).
7.8 Overvoltage protection (OVP)
The device has integrated logic for the monitoring of the output voltage using as an input
signal the voltage V
CONT
during the OFF time of the power MOSFET. This is the time when
the voltage from the auxiliary winding tracks the output voltage, through the turn ratio.
The CONT pin has to be connected to the auxiliary winding through the diode D
OVP
and the
resistors R
OVP
and R
LIM
as shown in Figure 22: CONT pin configuration. When, during the
OFF time, the vo ltage V
CONT
exceeds four co nse cu tiv e tim es the re ferenc e vol tage V
OVP
(see Table 9: Controller section), the overvoltage protection will stop the power MOSFET
and the converter enters auto-restart mode.
In order to bypass the noise immediately after the turn-off of the power MOSFET, the
voltage V
CONT
is sampled inside a short window after the time T
STROBE
, see Table 9:
Controller section and the Figure 21: OVP timing diagram. The sampled signal, if higher
than V
OVP
, triggers the internal OVP digital signal and increments the internal counter. The
same counter is reset every time the signal OVP is not triggered in one oscillator cycle.
Referring to Figure 22: CONT pin configuration, the resistor divider ratio k
OVP
will be given
by:
Equation 2
k
OVP
V
OVP
N
AUX
N
SEC
-------------- V
OUTOVP
V
DSEC
+()V
DAUX
---------------------------------------------------------------------------------------------------=
DocID15028 Rev 6 19/31
VIPER28 Operation
31
Equation 3
Where:
V
OVP
is the OVP threshold (see Table 9: Controller section)
V
OUT OVP
is the converter output voltage value to activate the OVP set by the designer
N
AUX
is the number of the auxiliary winding turns
N
SEC
is the number of the secondary winding turns
V
DSEC
is the secondary diode forward voltage
V
DAUX
is the auxiliar y diode forward voltage
R
OVP
together with R
LIM
constitute the output voltage divider
Then, fixing R
LIM
according to the desired I
Dlim
, the R
OVP
can be calculated by:
Equation 4
The resistor values will be such that the current sourced and sunk by the CONT pin are
within the rated capability of the internal clamp.
Figure 21. OVP timing diagram
k
OVP
R
LIM
R
LIM
R
OVP
+
----------------------------------=
R
OVP
R
LIM
1k
OVP
k
OVP
-----------------------×=
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Operation VIPER28
20/31 DocID15028 Rev 6
7.9 About CONT pin
Referring to Figure 22, the CONT pin is used to configure the:
1. reduction of the OCP setpoint (I
Dlim
)
2. output overv ol tage protecti on (OV P)
Table 10 lists the external components needed to activate one or more of the CONT pin
functions.
Figure 22. CONT pin configuration
7.10 Feedback and overload protection (OLP)
The device is a current-mode converter. The feedback pin controls PWM operation as well
as b urst mo de a nd ac ti vat es th e ov er loa d pr ote ctio n. Figure 23: FB pin configuration (option
1) and Figure 24: F B pin conf ig urati on (o ption 2) show the internal current-mode structure.
With the feedback pin voltage between
V
FBbm
and
V
FBlin
, (see Table 9: Co ntr oller sec tio n)
the drain current is sensed and converted to voltage that is applied to the non-inverting pin
of the PWM comparator.
This voltage is compared to the voltage on the feedback pin through a voltage divider on a
cycle-by-cycle basis. When these two voltages are equal, the PWM logic orders the switch-
off of the power MOSFET. The drain current is always limited to the value of I
Dlim
.
Table 10. CONT pin configurations
Function / component R
LIM
R
OVP
D
AUX
I
Dlim
reduction See Figure 13 No No
OVP 80 kSee Equation 4 Yes
I
Dlim
reduction and OVP
(1)
1. Select R
LIM
then R
OVP.
See Figure 13 See Equation 4 Yes
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DocID15028 Rev 6 21/31
VIPER28 Operation
31
When the feedback pin voltage reaches the threshold V
FBlin
, an internal cu rren t generator
starts to charge the feedback capacitor (C
FB
) and when the feedback voltage reaches the
V
FBolp
threshold, the converter is turned off and the automatic restart is activated.
During startup, when the output voltage is still low, if the feedback network is not properly
dimensioned, the feedback voltage could rise up to the overload threshold (V
FBolp)
generating the switching off of the IC itself. Taking into account that the feedback network
also fixes the loop stability, two options can be considered for this network.
The time from the overload detection (V
FB
= V
FBlin
) to the device shutdown (V
FB
= V
FBolp
)
must be set by C
FB
(or C
FB1
) using the formula:
Equation 5
In the option 1 shown in Figure 23: FB pin configuration (option 1), the capacitor C
FB
has a
dual function: guaranteeing the loop compensation and fixing the overload delay time as
calculated in Equation 5.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output
voltage is in steady state. The output transient time depends on the value of the output
capacitor and on the load.
When the value of the C
FB
capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
shown in Figure 24: FB pin configuration (option 2).
Using this alternative compensation network, two poles (f
PFB
, f
PFB1
) and one zero (f
ZFB
) ar e
introduced by the capacitors C
FB
and C
FB1
and the resistor R
FB1
.
The cap acit or C
FB
introduces a pole (f
PFB
) at higher frequency than f
ZB
and f
PFB1
. This pole
is usually used to compensate the high-frequency zero due to the ESR (equivalent series
resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency are:
Equation 6
Equation 7
The R
FB(DYN)
is the dynamic resistance seen by the FB pin.
T
OLP delay
C
FB
V
FBolp
V
FBlin
I
FB2
----------------------------------------×=
f
ZFB
1
2πC
FB1
R
FB1
⋅⋅
-----------------------------------------------=
f
PFB
R
FB DYN()
R
FB1
+
2πC
FB
R
FB DYN()
R
FB1
()⋅⋅
-------------------------------------------------------------------------------=
()
)DYN(FB1FB1FB
1PFB
RRC2 1
f+π
=
Operation VIPER28
22/31 DocID15028 Rev 6
The C
FB1
capacitor fixes the OLP delay and usually C
FB1
results in a much higher value
than C
FB
. Equation 5 can be still used to calculate the OLP delay, but C
FB1
has to be
considered instead of C
FB
. Using the compensation network shown in option 2, in all cases
the loop stability can be set as well as a sufficient OLP delay.
Figure 23. FB pin configuration (option 1)
Figure 24. FB pin configuration (option 2)
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VIPER28 Operation
31
7.11 Burst-mode operation at no load or very light load
When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If
it falls below the burst mode threshold, V
FBbm
, the power MOSFET is no longer allowed to
be switched on. After the MOSFET stops, the feedback pin voltage increases and when it
excee ds th e leve l , V
FBbm
+ V
FBbmhys
, the power MOSFET starts switching again. The burst
mode thresholds are provided in Table 9: Controller section and Figure 25: Burst mode
timing dia gr am, light loa d shows this behavior. The system alternates between a period of
time where the power MOSFET is switching to a period of time where the power MOSFET is
not switching. This mode of operation is the burst mode. The advantage of burst mode
operation is an average switching frequency much lower than the normal operation
frequency, up to several hundred hertz, minimizing all frequency-related losses. In order to
prevent audible noise, during burst mode the drain current peak is clamped to the level,
I
D_BM
, given in Table 9: Controller section.
Figure 25. Burst mode timing diagram, light load
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24/31 DocID15028 Rev 6
7.12 Extra power timer (EPT)
The extra power timer feature allows the setting of a blanking time inside which an overload
current can be admitted.
The timer is set through a capacitor (C
EPT
) connected to the EPT pin. Its duration is in the
range of a few seconds and is limited by thermal constraints.
The extra power timer (EPT) is started as soon as the drain current reaches the threshold
I
DLIM_EPT
(typ. 85% of I
Dlim
) and its duration is defined by the time needed to charge the
cap acitor C
EPT
up to the value V
EPT(STOP)
(4V, typ). The charging current is I
EPT
(5 uA, typ).
If the EPT starts, the IC sustains the overload and continues to operate normally if the drain
current falls below the threshold I
DLIM_EPT
(85% of I
Dlim
) before the EPT voltage reaches the
value V
EPT(STOP)
. The capacitor C
EPT
is discharged through the current I
EPT
(5 uA, typ) and
the next EPT is inhibited until the EPT voltage is higher than V
EPT(RESTART)
(0.6 V, typ).
If the EPT starts and the EPT voltage reaches the value V
EPT(STOP)
, the IC stops and it is
automatically restarted. The C
VDD
capacitor is then discharged down to the value
V
DD(RESTART)
(4.5 V, typ) and is recharged, through the HV current source, up to the value
V
DDon
(14 V, typ). Also in this case the capacitor C
EPT
is discharged through the I
EPT
current. See Figure 26 and Table 8: Supply section.
The EPT pin has to be connected to GND if the function is not used.
Figure 26. EPT timing diagram
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DocID15028 Rev 6 25/31
VIPER28 Operation
31
7.13 2
nd
level overcurrent protection and hiccup mode
The device is protected against short-circuit of the secondary rectifier, short-circuit on the
secondary winding or a hard-saturation of the flyback transformer. This type of anomalous
condition is invoked when the drain current exceeds the threshold I
DMAX
, see Table 9:
Controller section.
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal is tripped. If, in the subsequent switching
cycles, the signal is not tripped, a temporary disturbance is assumed and the protection
logic will be reset in its idle state; otherwise if the I
DMAX
threshold is exceeded for two
consecutive switching cycles, a real malfunction is assumed and the power MOSFET is
turned OF F.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding, hence the voltage on the C
VDD
capacitor
decays until the V
DD
undervoltage threshold (V
DDoff
), which clears the latch.
The startup HV current generator is still off, until the V
DD
voltage falls below its restart
voltage, V
DD(RESTART)
. After this condition the C
VDD
capacitor is charged again by the
I
DDch2
current, and the converter switching restarts if V
DDon
occurs. If the fault condition is
not removed, the device enters auto-restart mode. This behavior results in a low-frequency
intermittent operation (hiccup-mode operation), with very low stress on the power circuit.
Package mechanical data VIPER28
26/31 DocID15028 Rev 6
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
8.1 DIP-7 package information
Figure 27. DIP-7 package outline
DocID15028 Rev 6 27/31
VIPER28 Package mechanical data
31
Table 11. DIP-7 mechanical data
Dim. mm
Typ Min Max
A 5,33
A1 0,38
A2 3,30 2,92 4,95
b 0,46 0,36 0,56
b2 1,52 1,14 1,78
c 0,25 0,20 0,36
D 9,27 9,02 10,16
E 7,87 7,62 8,26
E1 6,35 6,10 7,11
e 2,54
eA 7,62
eB 10,92
L 3,30 2,92 3,81
M
(6)(8)
2,508
N 0,50 0,40 0,60
N1 0,60
O
(7)(8)
0,548
Package mechanical data VIPER28
28/31 DocID15028 Rev 6
8.2 SO16 narrow package information
Figure 28. SO16 narrow package outline
DocID15028 Rev 6 29/31
VIPER28 Package mechanical data
31
Table 12. SO16 narrow mechanical data
Dim. mm
Min. Typ. Max.
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.8 6 6.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
Revision history VIPER28
30/31 DocID15028 Rev 6
9 Revision history
Table 13. Document revision history
Date Revision Changes
30-Sep-2008 1In iti al rele as e
22-Jan-2009 2 Updated Figure 3 on page 4
21-Oct-2009 3 Added SO16N and SDIP10 packages
31-Aug-2010 4 Updated Figure 3, Figure 4, Figure 5 on pag e 10 and Table 3
on page 6
08-Jan-2013 5
Minor text changes to improve readability in Chapter 7.3,
Chapter 7.4, Chapter 7.5, Chapter 7.7, Chapter 7.8,
Chapter 7.9, Chapter 7.10, Chapter 7.11, Chapter 7.13, in
Ta bl e 8 on page 8, Table 9 on pag e 9 and in Figure 21 on
page 19
16-Dec-2014 6 Updated titl e in cover page.
Removed SDIP10 package.
Content reworked to improve readability.
DocID15028 Rev 6 31/31
VIPER28
31
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