FM25V02AG - CYPRESS SEMICONDUCTOR

Radar Receive Path AFE:

4-Channel LNA and PGA

Data Sheet

ADA8282

Rev. 0 Document Feedback

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FEATURES

4 channels of low noise amplifiers (LNAs) followed by

programmable gain amplifiers (PGAs)

Minimum −3 dB bandwidth of 5 MHz

Typical –3 dB bandwidth of 42.3 MHz

Typical slew rate of 28 V/µs

Differential input and output

Gain of 18 dB to 36 dB in 6 dB steps

Selectable low noise and low power modes

Input referred noise of 4.5 nV/√Hz at 18.3 mW per channel

Input referred noise of 3.8 nV/√Hz at 26.5 mW per channel

Input referred noise of 3.6 nV/√Hz at 34.8 mW per channel

Input referred noise of 3.4 nV/√Hz at 54.8 mW per channel

Channel to channel gain matching of ±0.25 dB

Absolute gain error of ±0.5 dB

SPI programmable

Power-down mode (SPI selectable)

3.1 V p-p differential output swing when using a 3.3 V supply

32-lead, 5 mm × 5 mm LFCSP package

Specified from −40°C to +125°C

Qualified for automotive applications

APPLICATIONS

Automotive radar

Adaptive cruise control

Collision avoidance

Blind spot detection

Self parking

Electronic bumpers

FUNCTIONAL BLOCK DIAGRAM

+OUTA

–OUTA

+INA

–INA LNA PGA

3nV√Hz

+24dB –6dB T O +12dB

+OUTB

–OUTB

+INB

–INB LNA PGA

3nV√Hz

+24dB –6dB T O +12dB

+OUTC

–OUTC

+INC

–INC LNA PGA

3nV√Hz

+24dB –6dB T O +12dB

+OUTD

–OUTD

+IND

–IND LNA PGA

3nV√Hz

+24dB –6dB T O +12dB

ADA8282

POWER

MODE

SPI

GAIN

SELECT

VIO AVDD RESETSCLK SDI SDOCS

13132-001

Figure 1.

GENERAL DESCRIPTION

The ADA8282 is designed for applications that require low cost,

low power, compact size, and flexibility. The ADA8282 has four

parallel channels, each including an LNA and a PGA. The LNA

and PGA combine to form a signal chain that features a gain range

of 18 dB to 36 dB in 6 dB increments with a guaranteed

minimum bandwidth of 5 MHz.

Using the highest power settings, the combined input referred

voltage noise of the combined LNA and PGA channel is

3.4 nV/√Hz at maximum gain.

The ADA8282 can be configured in four power modes that

trade off power and noise performance to optimize the overall

performance according to the end application.

Fabricated in an advanced complementary metal-oxide

semiconductor (CMOS) process, the ADA8282 is available in a

5 mm × 5 mm, RoHS-compliant, 32-lead LFCSP. It is specified

over the automotive temperature range of −40°C to +125°C.

ADA8282* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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EVALUATION KITS

•ADA8282 Evaluation Board

DOCUMENTATION

Data Sheet

•ADA8282: Radar Receive Path AFE: 4-Channel LNA and

PGA Data Sheet

User Guides

•UG-846: Evaluating the ADA8282 Radar Receive Path AFE

TOOLS AND SIMULATIONS

•ADA8282 SPICE Macro-Model

DESIGN RESOURCES

•ADA8282 Material Declaration

•PCN-PDN Information

•Quality And Reliability

•Symbols and Footprints

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ADA8282 Data Sheet

Rev. 0 | Page 2 of 21

TABLE OF CONTENTS

Features........................................................................................... 1

Applications ................................................................................... 1

Functional Block Diagram ............................................................ 1

General Description ...................................................................... 1

Revision History ............................................................................ 2

Specifications ................................................................................. 3

Digital Specifications ................................................................. 4

Absolute Maximum Ratings ......................................................... 5

Thermal Resistance ................................................................... 5

ESD Ca ution............................................................................... 5

Pin Configuration and Function Descriptions............................ 6

Typical Performance Characteristics............................................ 7

Theory of Operation.................................................................... 11

Radar Receive Path AFE.......................................................... 11

Default SPI Settings ................................................................. 11

Input Impedance...................................................................... 11

Power Modes............................................................................ 11

Programmable Gain Range ..................................................... 12

Output Swing Variation with Gain......................................... 12

Offset Voltage Adjustments .................................................... 12

Single-Ended or Differential Input......................................... 12

Short-Circuit Currents ............................................................ 12

SPI Interface ............................................................................. 12

Channel to Channel Phase Matching..................................... 13

Applications ................................................................................. 14

Increased Gain Using Two ADA8282 Devices in Series ....... 14

Multiplexing Inputs Using Multiple ADA8282 Devices ....... 15

Basic Connections for a Typical Application......................... 16

Register Map ................................................................................ 17

Register Summary ................................................................... 17

Register Details ........................................................................ 17

Outline Dimensions .................................................................... 21

Ordering Guide............................................................................ 21

Automotive Products............................................................... 21

REVISION HISTORY

7/15—Revision 0: Initial Version

Data Sheet ADA8282

Rev. 0 | Page 3 of 21

SPECIFICATIONS

AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = −40°C to +125°C, PGA_BIAS_SEL = b’10,

LNA_BIAS_SEL= b’10, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

ANALOG CHANNEL CHARACTERISTICS

Gain 18/24/30/36 dB

Gain Range 18 dB

Gain Error ±0.5 dB

−3 dB Bandwidth VOUT = 100 mV p-p, gain = 36 dB

PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 5 20.5 MHz

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 5 34.2 MHz

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 5 42.3 MHz

PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 5 52.3 MHz

Channel to Channel Gain Matching Frequencies up to 5 MHz 0.1 ±0.25 dB

Channel to Channel Phase Matching1 Frequencies up to 5 MHz 0.1 ±1 Degrees

Slew Rate 28 V/μs

Input Referred Noise Gain = 36 dB at 2 MHz

PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 4.5 nV/√Hz

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 3.8 nV/√Hz

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 3.6 nV/√Hz

PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 3.4 nV/√Hz

50 Ω impedance used for voltage to power

conversion

−156 dBm/Hz

Output Referred Noise Gain = 18 dB 36 nV/√Hz

Gain = 24 dB 61 nV/√Hz

Gain = 30 dB 115 nV/√Hz

Gain = 36 dB 218 nV/√Hz

Offset Voltage

Referred to Input Gain = 36 dB ±0.8 ±3 mV

Referred to Output Gain = 36 dB ±50 ±200 mV

SPI Offset Adjustment Resolution

(Relative to Input)

LNA_BIAS_SEL = b’00 113 μV

LNA_BIAS_SEL = b’01 186 μV

LNA_BIAS_SEL = b’10 250 μV

LNA_BIAS_SEL = b’11 440 μV

SPI Offset Adjustment Range (Relative

to Input)

LNA_BIAS_SEL = b’00 ±4 mV

LNA_BIAS_SEL = b’01 ±6 mV

LNA_BIAS_SEL = b’10 ±8 mV

LNA_BIAS_SEL = b’11 ±14 mV

Harmonic Distortion

Second Harmonic (HD2) VOUT = 2 V p-p, fIN = 100 kHz −70 dBc

V

OUT = 100 mV p-p, fIN = 2 MHz −85 dBc

Third Harmonic (HD3) VOUT = 2 V p-p, fIN = 100 kHz −85 dBc

V

OUT = 100 mV p-p, fIN = 2 MHz −95 dBc

Intermodulation Distortion VOUT = 2 V p-p, fIN1 = 100 kHz, fIN2 = 150 kHz −72 dBc

V

OUT = 100 mV p-p, fIN1 = 2 MHz, fIN2 = 2.1 MHz −83 dBc

Common-Mode Rejection Ratio (CMRR) −80 dB

Crosstalk −105 dBc

ADA8282 Data Sheet

Rev. 0 | Page 4 of 21

Parameter Test Conditions/Comments Min Typ Max Unit

POWER SUPPLY

Total Power Dissipation

PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 73 mW

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 106 mW

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 139 mW

PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 219 mW

Power Dissipation per Channel 31 mW

AVDD 3.0 3.6 V

VIO 1.8 3.6 V

IAVDD Four channels active

PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 19.6 22 mA

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 29 32 mA

PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 37.7 42 mA

PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 60 66.3 mA

One channel active 9.8 11 mA

IVIO 10 12 µA

Power-Down Current IAVDD and IVIO 20 100 µA

Power-Down Dissipation 0.07 0.33 mW

Power-Up Time Time to operational after chip is enabled 5 µs

Power Supply Rejection Ratio (PSRR) At dc −80 dB

At 1 MHz −80 dB

INPUT

Input Resistance

Differential Input Resistance 1.45 1.57 1.7 kΩ

Common-Mode Input Resistance 0.37 0.39 0.42 kΩ

Differential Input Capacitance 10.8 12 13.2 pF

OUTPUT

Output Voltage Swing +OUTx (−OUTx), gain = 18 dB 3.1 V p-p

+OUTx (−OUTx), gain = 24 dB, 30 dB, or 36 dB 6.3 V p-p

Output Balance fIN = 100 kHz −70 dB

Short-Circuit Current Per output at 25°C 205 mA

Capacitive Load 20% overshoot 30 pF

1 Normalized to 0° phase matching at 25°C; see the Theory of Operation section for details.

DIGITAL SPECIFICATIONS

AVDD = 3.3 V, TA = −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter Temperature Min Typ Max Unit

LOGIC INPUT (CS)

Logic 1 Voltage Full 1.2 VIO + 0.3 V

Logic 0 Voltage Full 0.3 V

Input Resistance 25°C 15 kΩ

Input Capacitance 25°C 0.5 pF

LOGIC INPUTS (SDI, SCLK, RESET)

Logic 1 Voltage Full 1.2 VIO + 0.3 V

Logic 0 Voltage Full 0 0.3 V

Input Resistance 25°C 2.5 kΩ

Input Capacitance 25°C 2 pF

Maximum SCLK Frequency 10 MHz

LOGIC OUTPUT (SDO)

Logic 1 Voltage (IOH = 800 A) Full VIO − 0.3 V

Logic 0 Voltage (IOL = 50 A) Full 0.3 V

Data Sheet ADA8282

Rev. 0 | Page 5 of 21

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Electrical

AVDD to EPAD −0.3 V to +3.9 V

+INx, −INx, SCLK, SDI, SDO, CS, VIO, RESET,

−OUTx, +OUTx to EPAD

−0.3V to AVDD +

0.3 V

ESD Ratings

Human Body Model (HBM) ±4000 V

Charged Device Model (CDM) ±2000 V

Environmental

Operating Temperature Range (Ambient) −40°C to +125°C

Storage Temperature Range (Ambient) −65°C to +150°C

Maximum Junction Temperature 150°C

Lead Temperature (Soldering, 10 sec) 300°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

θJA is specified for the worst case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA θ

JC Unit

32-Lead, 5 mm × 5 mm LFCSP 33.51 4.1 °C/W

ESD CAUTION

ADA8282 Data Sheet

Rev. 0 | Page 6 of 21

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24 +OUTA

23 –OUTA

22 +OUTB

21 –OUTB

20 +OUTC

19 –OUTC

18 +OUTD

17 –OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

ADA8282

TOP VIEW

(Not to Scale)

NOTES

1. NIC = NO INTERNAL CONNECTION.

2. TIE THE EXPOSED PAD ON THE BOTTOM SIDE OF THE

PACKAGE TO THE ANALOG/DIGITAL GROUND PLANE.

13132-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

0 EPAD Exposed Pad. Tie the exposed pad on the bottom side of the package to the analog/digital ground plane.

1 +INA Positive LNA Analog Input for Channel A.

2 −INA Negative LNA Analog Input for Channel A.

3 +INB Positive LNA Analog Input for Channel B.

4 −INB Negative LNA Analog Input for Channel B.

5 +INC Positive LNA Analog Input for Channel C.

6 −INC Negative LNA Analog Input for Channel C.

7 +IND Positive LNA Analog Input for Channel D.

8 −IND Negative LNA Analog Input for Channel D.

9 AVDD 3.3 V Analog Supply.

10 NIC No Internal Connection. Leave this pin floating.

11 NIC No Internal Connection. Leave this pin floating.

12 NIC No Internal Connection. Leave this pin floating.

13 NIC No Internal Connection. Leave this pin floating.

14 NIC No Internal Connection. Leave this pin floating.

15 NIC No Internal Connection. Leave this pin floating.

16 AVDD 3.3 V Analog Supply.

17 −OUTD Negative Analog Output for Channel D.

18 +OUTD Positive Analog Output for Channel D.

19 −OUTC Negative Analog Output for Channel C.

20 +OUTC Positive Analog Output for Channel C.

21 −OUTB Negative Analog Output for Channel B.

22 +OUTB Positive Analog Output for Channel B.

23 −OUTA Negative Analog Output for Channel A.

24 +OUTA Positive Analog Output for Channel A.

25 AVDD 3.3 V Analog Supply.

26 VIO Digital Level Select for SPI and RESET. This pin can accept 1.8 V to 3.3 V.

27 RESET Reset Input. RESET overrides the SPI and powers down the device and returns all settings back to default. RESET is

pulled to ground by default. A logic high triggers the reset.

28 SCLK Serial Clock.

29 CS Chip Select Bar.

30 SDI Serial Data Input.

31 SDO Serial Data Output.

32 AVDD 3.3 V Analog Supply.

Data Sheet ADA8282

Rev. 0 | Page 7 of 21

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.3 V, LNA + PGA gain = 36 dB (LNA gain = 24 dB, PGA gain = 12 dB), TA = 25°C, PGA_BIAS_SEL = b’10, LNA_BIAS_SEL=

b’10, unless otherwise noted.

25000

0

5000

10000

15000

20000

NUMBER O F HI TS

GAI N E RROR (dB)

T

A

= –40° C

T

A

= +25°C

T

A

= +125°C

13132-103

–0.20

–0.19

–0.18

–0.17

–0.16

–0.15

–0.14

–0.13

–0.12

–0.11

–0.10

–0.09

–0.08

–0.07

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

Figure 3. Gain Accuracy Distribution

3000

2500

2000

1500

1000

0

500

–150 –100 –50 050 100 150

NUMBER O F HI TS

V

OS

(mV)

T

A

= –40° C

T

A

= +25°C

T

A

= +125°C N: 12199

M: –13.1269

SD: 19. 535

N: 12353

M: –7.49789

SD: 20. 0841

N: 11292

M: 0.0246995

SD: 21. 4755

13132-110

Figure 4. Output Offset Voltage Distribution

3000

2500

2000

1500

1000

0

500

0.050

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0

NUMBER O F HI TS

DC GAI N M ISM ATCH ( dB)

TA = –40° C

TA = +25°C

TA = +125°C

13132-106

Figure 5. Distribution of Channel to Channel Gain Matching

350

300

250

200

150

100

50

0

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

NUMBER O F HI TS

PHASE M ISM ATCH ( Degrees)

T

A

= –40° C

T

A

= +125°C

13132-107

Figure 6. Distribution of Channel to Channel Phase Matching

0

–20

–40

–60

–80

–120

–100

0 54321

THD ( dB)

FREQUENCY (MHz)

24dB

30dB

36dB

18dB

13132-108

Figure 7. Total Harmonic Distortion (THD) vs. Frequency for Various

Gains, VOUT = −10 dBm

1800

1600

1400

1200

1000

800

600

400

200

01k 1G10M 100M1M100k10k

INPUT IMPEDANCE (Ω)

FRE Q UE NCY ( Hz )

13132-109

Figure 8. Input Impedance vs. Frequency

ADA8282 Data Sheet

Rev. 0 | Page 8 of 21

TIME (80ns/DIV)

ANALOG OUTPUT (1V/DIV)

2V

250mV

ANALOG OUT P UT

SDI

b'00 b'11

13132-105

Figure 9. Gain Step Transient Response

30

25

20

15

10

5

01k 10k 100k 1M 10M 100M

NOISE (nV/√Hz)

FREQUENCY ( Hz )

GAI N = 18dB

GAI N = 24dB

GAI N = 30dB

GAI N = 36dB

13132-111

Figure 10. Input Referred Noise vs. Frequency

40

35

30

25

20

15

10

5

01k 10k 100k 1M 10M 100M

NOISE FIGURE (dB)

FREQUENCY ( Hz )

UNTERMINATED

50Ω

13132-112

Figure 11. Noise Figure vs. Frequency

42

–24

–18

–12

–6

0

6

12

18

24

30

36

100k 1M 10M 100M

GAI N ( dB)

FREQUENCY ( Hz )

GAI N = 36dB

GAI N = 30dB

GAI N = 24dB

GAI N = 18dB

13132-113

Figure 12. Frequency Response at All Gains (Bias Mode 0)

42

–24

–18

–12

–6

0

6

12

18

24

30

36

100k 1M 10M 100M

GAI N ( dB)

FREQUENCY ( Hz )

GAI N = 36dB

GAI N = 30dB

GAI N = 24dB

GAI N = 18dB

13132-114

Figure 13. Frequency Response at All Gains (Bias Mode 2)

4

–4

–3

–2

–1

0

1

2

3

0800700

600500400300200100

AMPLITUDE (V)

TIME (ns)

V

IN

× GAIN

V

OUT

13132-115

Figure 14. Overdrive Recovery

Data Sheet ADA8282

Rev. 0 | Page 9 of 21

200

–50

0

50

100

150

01000800600400200

V

OUT

(mV)

TIME (ns)

NO LOAD

5pF

33pF

66pF

100pF

13132-116

Figure 15. Pulse Response at Various Output Capacitive Loads

0100 200 300 400 500 600 700 800 900 1000

VOUT (V)

TIME (ns)

–1.5

–1.0

–0.5

0

0.5

1.0

1.5 MODE 0

MODE 1

MODE 2

MODE 3

13132-121

Figure 16. Larg e Signal

Pulse Response for Various LNA and PGA Bias Modes

500

300

320

340

360

380

400

420

440

460

480

–40 –25 10 520 35 50 65 80 95 110 125

SHORT- CI RCUIT CURRE NT ( mA)

TEMPERATURE (°C)

13132-118

Figure 17. Short-Circuit Current vs. Temperature Per Channel

30

20

21

22

23

24

25

26

27

28

29

–40 –25 10 520 35 50 65 80 95 110 125

SLEW RATE (V/µs)

TEMPERATURE (°C)

GAI N = 18dB

GAI N = 24dB

GAI N = 30dB

GAI N = 36dB

13132-119

Figure 18. Output Slew Rate vs. Temperature

18 24 30 36

V

OUT

(V)

GAI N ( dB)

–3.4

–3.0

–2.6

–2.2

–1.8

–1.4

–1.0

–0.6

–0.2

0.2

0.6

1.0

1.4

1.8

2.2

2.6

3.0

3.4

13132-125

Figure 19. Maximum and Minimum Differential VOUT vs. Gain

4

–4

–3

–2

–1

0

1

2

3

10 100 1k 10k 100k

OUTPUT VOLTAGE SWING (V)

OUTPUT LOAD RESISTANCE (Ω)

T

A

= –40° C

T

A

= +25°C

T

A

= +85°C

13132-117

Figure 20. Differential Output Voltage Swing vs. Output Load Resistance

ADA8282 Data Sheet

Rev. 0 | Page 10 of 21

120

0

20

40

60

80

100

10k 100k 1M 10M 100M

PSRR ( dB)

FREQUENCY ( Hz )

GAI N = 18dB

GAI N = 24dB

GAI N = 30dB

GAI N = 36dB

13132-122

Figure 21. PSRR vs. Frequency at Various Gains

100

0

20

40

60

80

10

30

50

70

90

100k 1M 10M 100M

CMRR (dB)

FRE Q UE NCY ( Hz )

GAI N = 18dB

GAI N = 24dB

GAI N = 30dB

GAI N = 36dB

13132-123

Figure 22. CMRR vs. Frequency at Various Gains

0

–140

–120

–100

–80

–60

–40

–20

10k 100k 1M 10M 100M

CROSS TAL K ( dB)

FREQUENCY ( Hz )

13132-124

Figure 23. Crosstalk vs. Frequency

–40 –25 10 520 35 50 65 80 95 110 125

SUPPLY CURRE NT (mA)

TEMPERATURE (°C)

37.55

37.60

37.65

37.70

37.75

37.80

37.85

13132-120

Figure 24. Quiescent Supply Current vs. Temperature

Data Sheet ADA8282

Rev. 0 | Page 11 of 21

THEORY OF OPERATION

RADAR RECEIVE PATH AFE

The primary application for the ADA8282 is a high speed ramp,

frequency modulated, continuous wave radar (HSR-FMCW radar).

Figure 25 shows a simplified block diagram of an HSR-FMCW

radar system. The signal chain requires multiple channels, each

including an LNA and a PGA. The ADA8282 provides these key

components in a single 5 mm × 5 mm LFCSP.

The performance of each component is designed to meet the

demands of an HSR-FMCW radar system. Some examples of

these performance metrics are the LNA noise, PGA gain range,

and signal chain bandwidth and power. The ADA8282 also has

adjustable power modes to adjust the power and performance

level to accommodate a wide variety of applications.

The ADA8282 is programmable via the SPI. Channel gain,

power mode, and offset voltage can be adjusted using the SPI port.

DEFAULT SPI SETTINGS

When initially powered, the ADA8282 defaults to a setting of

0x00 in Register 0x17, which disables all channels. The device is

enabled by writing 0x0F to Register 0x17.

INPUT IMPEDANCE

The input impedance to the ADA8282 is set by an internal 785 Ω

resistance at each input, biased to midsupply by an internal voltage

buffer. Both the positive and negative inputs are biased with the

same network, creating a differential input impedance of 1.57 kΩ.

The input to the ADA8282 is typically ac-coupled. The ac

coupling capacitors operate with the input impedance of the

ADA8282 to create a high-pass filter with a pole at 1/(2π2RC),

where R = 785 Ω with a typical tolerance of ±15%.

POWER MODES

The ADA8282 has four power modes that can be controlled

through Register 0x14 (BIAS_SEL). The power modes allow a

user to adjust the power and performance tradeoffs to suit the end

application. Use the low power mode when power savings are in

demand, and use the high power mode in applications that

require increased bandwidth and low noise.

Table 6 shows the power performance trade-offs of the various

SPI settings.

Table 6. Power Mode Trade-Offs

Mode

Setting

Power per

Channel

(mW)

Input Referred

Noise at 2 MHz

(nV/√Hz)

Typical Bandwidth

(MHz), Gain = 36 dB

b’00 18.3 4.5 20.5

b’01 26.5 3.8 34.2

b’10 34.8 3.6 42.3

b’11 54.8 3.4 52.3

PA

DSP

ANTENNA

VCO

12-BIT

ADC

12-BIT

ADC

12-BIT

ADC

PGALNA

ADA8282

REF.

OSCILLATOR CHIRP RAMP

GENERATOR

TRANSMIT SIGNAL GENERATION

13132-021

Figure 25. Typical Signal Chain Overview

ADA8282 Data Sheet

Rev. 0 | Page 12 of 21

PROGRAMMABLE GAIN RANGE

The ADA8282 has a programmable gain to allow adjusting of

the output amplitudes of signals to accommodate a variety of

applications. The gain of the ADA8282 is programmable in 6 dB

increments from 18 dB to 36 dB. The gain is controlled using

Register 0x15. The same register controls all four channels, but

each channel can be independently controlled by utilizing the

appropriate bits in the register. Channel A is controlled with the

two LSBs of Register 0x15 (Bits[1:0]), Channel B uses Bits[3:2],

Channel C uses Bits[5:4], and Channel D uses the two MSBs,

Bits[7:6].

The gain setting and gains are listed in Table 7.

Table 7. Gain Settings

Register 0x15 Setting Gain (dB) Gain (V/V)

b’00 18 7.9

b’01 24 15.9

b’10 30 31.6

b’11 36 63.1

OUTPUT SWING VARIATION WITH GAIN

The ADA8282 gain is implemented using two internal gain stages.

The first stage is an LNA with a gain of 24 dB, and the second

stage is a PGA with a gain that varies from −6 dB to +12 dB. The

output of the LNA has a fixed output swing range, and is the

limiting factor when the channel gain is 18 dB. Because of the

limitations of the LNA swing range, the ADA8282 has an output

swing that is dependent on gain, as shown in Table 8.

Table 8. Output Swing at Various Gains

Gain (dB) Output Swing (V p-p)

18 3.1

24 6.3

30 6.3

36 6.3

OFFSET VOLTAGE ADJUSTMENTS

Register 0x10 through Register 0x13 adjust the dc offset voltage

of each channel. The default value of 0x20 is intended to be the

setting for the offset closest to 0 V, but adjustments can be made

as required by the application.

The default setting (0x20) applies a zero offset, 0x00 applies the

maximum negative offset, and 0x3F applies the maximum

positive offset.

The range and resolution of the LNA_OFFSETx adjustments

are dependent on the LNA bias mode as described in Table 9.

Table 9. Offset Voltage Adjustments

LNA_BIAS_SEL

Setting

Referred to Input (RTI)

Offset Resolution (μV)

RTI Offset

Range (mV)

b’00 113 ±4

b’01 186 ±6

b’10 250 ±8

b’11 440 ±14

VIO Pin

The VIO pin sets the voltage levels used by the SPI interface. If

the VIO pin is tied to the 3.3 V supply, the SPI port functions

on 3.3 V logic.

SINGLE-ENDED OR DIFFERENTIAL INPUT

The ADA8282 operates with either a differential or single-ended

signal source. The maximum input voltage swing is the same in

either configuration. When using a single-ended signal source,

connect the unused input to ground with a capacitor. Matching

the ac coupling capacitor to the ac grounding capacitor

optimizes CMRR performance.

SHORT-CIRCUIT CURRENTS

The ADA8282 typically has a 205 mA short-circuit current per

output pin. The thermal implications of this current during

unintended shorting of these outputs must be taken into account

when designing boards with this device.

SPI INTERFACE

The ADA8282 SPI interface uses a 4-wire interface to deliver a

16-bit instruction header, followed by 8 bits of data. The first bit

is a read/write bit. W1 and W0 determine how many bytes are

transferred, and must both be zeros for the ADA8282 to write to a

single register. Then, a 13-bit address and an 8-bit data byte follow.

The SPI port operates at SCLK frequencies of up to 10 MHz.

For additional SPI timing information, see the AN-877

Application Note.

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0A12W0W1R/W

CS

SCLK

SDI

DON’T CARE

16-BIT INSTRUCTION HEADER

MSB-FIRST 16-BIT INSTRUCTION

REGISTER (N) DATA

13132-022

Figure 26. Serial Instruction Details

Data Sheet ADA8282

Rev. 0 | Page 13 of 21

CHANNEL TO CHANNEL PHASE MATCHING

In a multichannel radar application, matching the ac performance

between channels improves the distance and angle resolution of

a detected object, particularly the phase matching in the band of

interest for the application. The ADA8282 layout and design are

optimized to increase phase matching. The ADA8282 also has

sufficient bandwidth to minimize any channel to channel phase

variation for up to 5 MHz input signals.

The phase mismatch between channels can be calibrated at a

single temperature. However, any variation in phase matching

over temperature can still degrade system performance. The

ADA8282 is characterized to capture the maximum channel to

channel phase mismatch as the temperature varies from a

calibration temperature of 25°C.

Figure 27 shows a distribution of channel to channel phase

mismatch for signal frequencies up to 5 MHz. When the initial

phase mismatch between channels is normalized to 0° at +25°C,

the 6σ mismatch is 0.43° at −40°C and 0.6° at +125°C.

350

300

250

200

150

100

50

0

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

NUMBER OF HITS

PHASE MISMATCH (Degrees)

T

A

= –40°C

T

A

= +125°C

13132-126

Figure 27. Channel to Channel Phase Mismatch, Normalized to 0° at 25°C,

LNA_BIAS_SEL = PGA_BIAS_SEL = b’00, PGA_GAIN = b’11

The amount of channel to channel phase mismatch varies with

the power mode. Table 10 shows the 6σ phase mismatch up to

5 MHz over the full temperature range for all gain settings in

different power modes, when normalized to 0° at 25°C in each

power mode.

Table 10. Maximum Channel to Channel Phase Mismatch over Temperature After 25°C Calibration

PGA_BIAS_SEL LNA_BIAS_SEL

6σ Channel to Channel Phase Mismatch

over Temperature (Degrees)

Maximum Channel to Channel Phase

Mismatch (Degrees)

b’00 b’00 0.60 ±1

b’01 b’01 0.41 ±1

b’10 b’10 0.33 ±1

b’11 b’11 0.60 ±1

ADA8282 Data Sheet

Rev. 0 | Page 14 of 21

APPLICATIONS INFORMATION

INCREASED GAIN USING TWO ADA8282 DEVICES

IN SERIES

For applications that require gains greater than 36 dB, two

ADA8282 devices can be used in series with each other. To

optimize the signal swing for the path, increment the gains

according to Table 11.

Table 11. Gain Settings for Two Devices in Series

Total Gain (dB)

A1 (Input Side

ADA8282) Gain (dB)

A2 (Output Side

ADA8282) Gain (dB)

36 18 18

42 18 24

48 24 24

54 30 24

60 30 30

66 36 30

72 36 36

24

+OUTA

23

–OUTA

22

+OUTB

21

–OUTB

20

+OUTC

19

–OUTC

18

+OUTD

17

–OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

ADA8282

EPAD TIED

TO GROUND

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

0.1µF

0.1µF 0.1µF

+3.3V+3.3V

+3.3V

GPIO: +3.3V/0V

+3.3V

10kΩ

SPI BUS

24

+OUTA

23

–OUTA

22

+OUTB

21

–OUTB

20

+OUTC

19

–OUTC

18

+OUTD

17

–OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

ADA8282

EPAD TIED

TO GROUND

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

0.1µF

INPUT A

SOURCE

INPUT B

SOURCE

INPUT C

SOURCE

INPUT D

SOURCE

0.1µF 0.1µF

+3.3V+3.3V

+3.3V

GPIO: +3.3V/0V

+3.3V

10kΩ

SPI BUS

TO ADC

13132-023

Figure 28. Using Two ADA8282 Devices in Series to Increase Gain

Data Sheet ADA8282

Rev. 0 | Page 15 of 21

MULTIPLEXING INPUTS USING MULTIPLE

ADA8282 DEVICES

It is possible to multiplex eight differential inputs down to four

differential outputs by using two ADA8282 devices. The devices

can be connected such that the outputs are connected (see

Figure 29) as long as only one device is enabled at a time. When

an ADA8282 is disabled, the outputs present a 6 kΩ load on the

output bus.

24

+OUTA

23

–OUTA

22

+OUTB

21

–OUTB

20

+OUTC

19

–OUTC

18

+OUTD

17

–OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

ADA8282

EPAD TIED

TO GROUND

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

0.1µF

INPUT A

SOURCE

INPUT B

SOURCE

INPUT C

SOURCE

INPUT D

SOURCE

0.1µF 0.1µF

+3.3V+3.3V

+3.3V

GPIO: +3.3V/0V

+3.3V

10kΩ

SPI BUS

24

+OUTA

23

–OUTA

22

+OUTB

21

–OUTB

20

+OUTC

19

–OUTC

18

+OUTD

17

–OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

ADA8282

EPAD TIED

TO GROUND

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

0.1µF

INPUT E

SOURCE

INPUT F

SOURCE

INPUT G

SOURCE

INPUT H

SOURCE

0.1µF 0.1µF

+3.3V+3.3V

+3.3V

GPIO: +3.3V/0V

+3.3V

10kΩ

SPI BUS

TO ADC

13132-024

Figure 29. Multiplexing by Connecting Two ADA8282 Outputs to One Output Bus

ADA8282 Data Sheet

Rev. 0 | Page 16 of 21

BASIC CONNECTIONS FOR A TYPICAL

APPLICATION

The ADA8282 is typically configured to operate with a nominal

3.3 V power supply, using the EPAD as the analog ground

connection. Place the bypass capacitors as close as possible to

the power supply pins to minimize the length of metal traces in

series with the bypassing paths. AC couple the inputs and

outputs for each channel as shown in Figure 30. Pull the RESET pin

low with a 10 kΩ resistor and drive it with 3.3 V GPIO logic.

The SPI pins can be directly connected to the SPI bus.

24

+OUTA

23

–OUTA

22

+OUTB

21

–OUTB

20

+OUTC

19

–OUTC

18

+OUTD

17

–OUTD

1

2

3

4

5

6

7

8

+INA

–INA

+INB

–INB

+INC

–INC

+IND

–IND

9

10

11

12

13

14

15

16

AVDD

NIC

AVDD

32

31

30

29

28

27

26

25

ADA8282

EPAD TIED

TO GROUND

AVDD

SDO

SDI

CS

SCLK

RESET

VIO

AVDD

0.1µF

INPUT A

SOURCE

INPUT B

SOURCE

INPUT C

SOURCE

INPUT D

SOURCE

0.1µF 0.1µF

+3.3V+3.3V

+3.3V

GPIO: +3.3V/0V

+3.3V

10kΩ

SPI BUS

TO ADC

13132-025

Figure 30. Typical Component Connections

Data Sheet ADA8282

Rev. 0 | Page 17 of 21

REGISTER MAP

REGISTER SUMMARY

Table 12. Register Summary

Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW

0x00 INTF_CONFA [7:0] INTF_CONFA2 LSBFIRST1 INTF_CONFA1 LSBFIRST0 INTF_CONFA0 0x00 RW

0x01 SOFT_RESET [7:0] Unused SOFT_RESET 0x00 R

0x04 CHIP_ID1 [7:0] CHIP_IDLOW 0x82 R

0x05 CHIP_ID2 [7:0] CHIP_IDHI 0x82 R

0x06 Revision [7:0] Revision 0x00 R

0x10 LNA_OFFSET0 [7:0] Unused LNA_OFFSET0 0x20 RW

0x11 LNA_OFFSET1 [7:0] Unused LNA_OFFSET1 0x20 RW

0x12 LNA_OFFSET2 [7:0] Unused LNA_OFFSET2 0x20 RW

0x13 LNA_OFFSET3 [7:0] Unused LNA_OFFSET3 0x20 RW

0x14 BIAS_SEL [7:0] Unused PGA_BIAS_SEL LNA_BIAS_SEL 0x0A RW

0x15 PGA_GAIN [7:0] PGA_GAIN3 PGA_GAIN2 PGA_GAIN1 PGA_GAIN0 0x00 RW

0x17 EN_CHAN [7:0] Unused EN_

CHANNEL3

EN_

CHANNEL2

EN_

CHANNEL1

EN_

CHANNEL0

0x00 RW

0x18 EN_BIAS_GEN [7:0] Unused EN_BIAS_GEN 0x00 RW

0x1D SPAREWR0 [7:0] Unused GPIO_WRITE GPIO_WR_

MODE

0x00 RW

0x1E SPARERD0 [7:0] Unused GPIO_READ 0x00 R

REGISTER DETAILS

Register 0x00: Interface Configuration Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTF_CONFA2 LSBFIRST1 INTF_CONFA1 LSBFIRST0 INTF_CONFA0

The INTF_CONFA configuration register is symmetric, as it is the first register written and sets the data direction (LSB first or MSB first).

Table 13. INTF_CONFA Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[7:0] INTF_CONFA2 INTF_CONFA2 must remain b’00. 0x00 RW

5 LSBFIRST1 LSBFIRST1 must be set to b’1 for LSB first operation and to b’0 for MSB first operation. 0x00 RW

[4:3] INTF_CONFA1 INTF_CONFA1 must remain b’00. 0x00 RW

2 LSBFIRST0 LSBFIRST0 must be set to b’1 for LSB first operation and to b’0 for MSB first operation. 0x00 RW

[1:0] INTF_CONFA0 INTF_CONFA0 must remain b’00. 0x00 RW

Register 0x01: Soft Reset Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused SOFT_RESET

Table 14. SOFT_RESET Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

0 SOFT_RESET The SOFT_RESET bit resets all registers to their default values when SOFT_RESET is set to b’1. 0x00 RW

Register 0x04: Chip ID Low Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CHIP_IDLOW

Table 15. CHIP_IDLOW Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[7:0] CHIP_IDLOW The CHIP_ID1 and CHIP_ID2 registers identify the ADA8282. 0x82 R

ADA8282 Data Sheet

Rev. 0 | Page 18 of 21

Register 0x05: Chip ID High Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CHIP_IDHI

Table 16. CHIP_IDHI Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[7:0] CHIP_IDHI The CHIP_ID1 and CHIP_ID2 registers identify the ADA8282. 0x82 R

Register 0x06: Revision Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Revision

Table 17. Revision Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[7:0] Revision The revision register identifies the silicon revision of the current die. 0x00 R

Register 0x10: LNA Offset 0 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused LNA_OFFSET0

Table 18. LNA_OFFSET0 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[5:0] LNA_OFFSET0

LNA_OFFSET0 controls the offset of Channel A. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20 RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x11: LNA Offset 1 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused LNA_OFFSET1

Table 19. LNA_OFFSET1 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[5:0] LNA_OFFSET1

LNA_OFFSET0 controls the offset of Channel B. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20 RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x12: LNA Offset 2 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused LNA_OFFSET2

Data Sheet ADA8282

Rev. 0 | Page 19 of 21

Table 20. LNA_OFFSET2 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[5:0] LNA_OFFSET2

LNA_OFFSET0 controls the offset of Channel C. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20 RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x13: LNA Offset 3 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused LNA_OFFSET3

Table 21. LNA_OFFSET3 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[5:0] LNA_OFFSET3

LNA_OFFSET0 controls the offset of Channel D. The default setting (0x20) applies the minimum

offset, 0x00 applies the maximum negative offset, and 0x3F applies the maximum positive offset.

0x20 RW

The resolution of the offset varies with the LNA bias mode as follows:

LNA Bias Mode 0: 113 μV RTI offset resolution, ±4 mV range.

LNA Bias Mode 1: 186 μV RTI offset resolution, ±6 mV range.

LNA Bias Mode 2: 250 μV RTI offset resolution, ±8 mV range.

LNA Bias Mode 3: 440 μV RTI offset resolution, ±14 mV range.

Register 0x14: PGA Bias Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused PGA_BIAS_SEL LNA_BIAS_SEL

The PGA bias select register allows the user to trade off power and performance (for example, bandwidth and noise).

Table 22. BIAS_SEL Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[3:2] PGA_BIAS_SEL Set PGA_BIAS_SEL to b’00 for the minimum PGA bias and to b’11 for the maximum PGA bias. 0x00 RW

[1:0] LNA_BIAS_SEL Set LNA_BIAS_SEL to b’00 for the minimum LNA bias and to b’11 for the maximum LNA bias. 0x00 RW

Register 0x15: PGA Gain Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PGA_GAIN3 PGA_GAIN2 PGA_GAIN1 PGA_GAIN0

The PGA gain register allows independent gain settings for each channel.

Table 23. PGA_GAIN Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

[7:6] PGA_GAIN3 Set PGA_GAIN3 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel D

0x00 RW

[5:4] PGA_GAIN2 Set PGA_GAIN2 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel C

0x00 RW

[3:2] PGA_GAIN1 Set PGA_GAIN1 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel B

0x00 RW

[1:0] PGA_GAIN0 Set PGA_GAIN0 to b’00 for 18 dB gain, to b’01 for 24 dB gain, to b’10 for 30 dB gain, and to

b’11 for 36 dB gain for Channel A

0x00 RW

ADA8282 Data Sheet

Rev. 0 | Page 20 of 21

Register 0x17: Enable Channel Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused EN_CHANNEL3 EN_CHANNEL2 EN_CHANNEL1 EN_CHANNEL0

The enable channel register allows individual channels to be enabled or disabled. The default mode for the channel is disabled. Write 0x0F

to the EN_CHAN register to enable all channels.

When a channel is disabled but the bias generator is still enabled, the channel’s current consumption is <100 μA. When a channel is

disabled, its output pins are high-Z. The enable channel register resets at AVDD power-on to 0x00 to avoid inrush current for fast supply

ramps.

Table 24. EN_CHAN Register Bit Descriptions

Bits Bit Name Description Reset Access

3 EN_CHANNEL3 Set to b’1 to enable Channel D, and set to b’0 to disable Channel D 0x00 RW

2 EN_CHANNEL2 Set to b’1 to enable Channel C, and set to b’0 to disable Channel C 0x00 RW

1 EN_CHANNEL1 Set to b’1 to enable Channel B, and set to b’0 to disable Channel B 0x00 RW

0 EN_CHANNEL0 Set to b’1 to enable Channel A, and set to b’0 to disable Channel A 0x00 RW

Register 0x18: Enable Bias Generator Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused EN_BIAS_GEN

When any channel is enabled, the bias generator is automatically enabled. The EN_BIAS_GEN register controls whether the bias

generator stays active, even when all channels are disabled. Leaving the bias generator active decreases the enable time of the device.

Table 25. EN_BIAS_GEN Register Bit Descriptions

Bits Bit Name Description Reset Access

0 EN_BIAS_GEN Setting EN_BIAS_GEN to 1 keeps the bias generator active, providing a faster enable time (~2 μs). 0x00 RW

Register 0x1D: GPIO Write Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused GPIO_WRITE GPIO_WR_MODE

The GPIO_WR_MODE bit reconfigures the SDO pin to a general-purpose input/output (GPIO) port that can be written by the

GPIO_WRITE register or read by the GPIO_READ register.

Table 26. SPAREWR0 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

1 GPIO_WRITE Data bit is put onto the SDO pin when GPIO write mode is active. 0x00 RW

0 GPIO_WR_MODE Write b’1 to this register to activate GPIO write mode. 0x00 RW

Register 0x1E: GPIO Read Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Unused GPIO_READ

Table 27. SPARERD0 Configuration Register Bit Descriptions

Bits Bit Name Description Reset Access

0 GPIO_READ This register reflects the logic level placed on SDO when a b’0 is written to GPIO_WR_MODE. 0x00 R

Data Sheet ADA8282

Rev. 0 | Page 21 of 21

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

1

0.50

BSC

3.50 REF

BOTTOM VIEWTOP VIEW

PIN 1

INDICATOR

32

916

17

24

25

8

EXPOSED

PAD

PIN 1

INDICATOR

3.65

3.50 SQ

3.45

S

EATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.18

5.10

5.00 SQ

4.90

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.50

0.40

0.30

0.25 MIN

04-02-2012-A

Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-11)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option

ADA8282WBCPZ-R7 −40°C to +125°C 32-Lead LFCSP_WQ, 7” Tape and Reel CP-32-11

ADA8282WBCPZ −40°C to +125°C 32-Lead LFCSP_WQ CP-32-11

ADA8282CP-EBZ Evaluation Board

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADA8282W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

registered trademarks are the property of their respective owners.

D13132-0-7/15(0)