STM32F105xx STM32F107xx Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces Features FBGA Core: ARM 32-bit CortexTM-M3 CPU - 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access - Single-cycle multiplication and hardware division Memories - 64 to 256 Kbytes of Flash memory - 64 Kbytes of general-purpose SRAM Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 3-to-25 MHz crystal oscillator - Internal 8 MHz factory-trimmed RC - Internal 40 kHz RC with calibration - 32 kHz oscillator for RTC with calibration Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers 2 x 12-bit, 1 s A/D converters (16 channels) - Conversion range: 0 to 3.6 V - Sample and hold capability - Temperature sensor - up to 2 MSPS in interleaved mode 2 x 12-bit D/A converters DMA: 12-channel DMA controller - Supported peripherals: timers, ADCs, DAC, I2Ss, SPIs, I2Cs and USARTs Debug mode - Serial wire debug (SWD) & JTAG interfaces - Cortex-M3 Embedded Trace MacrocellTM Up to 80 fast I/O ports - 51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant CRC calculation unit, 96-bit unique ID August 2011 LQFP100 14 x 14 mm LQFP64 10 x 10 mm LFBGA100 10 x 10 mm Up to 10 timers with pinout remap capability - Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - 1 x 16-bit motor control PWM timer with dead-time generation and emergency stop - 2 x watchdog timers (Independent and Window) - SysTick timer: a 24-bit downcounter - 2 x 16-bit basic timers to drive the DAC Up to 14 communication interfaces with pinout remap capability - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 3 SPIs (18 Mbit/s), 2 with a multiplexed I2S interface that offers audio class accuracy via advanced PLL schemes - 2 x CAN interfaces (2.0B Active) with 512 bytes of dedicated SRAM - USB 2.0 full-speed device/host/OTG controller with on-chip PHY that supports HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM - 10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages Table 1. Device summary Reference Part number STM32F105xx STM32F105R8, STM32F105V8 STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC STM32F107xx STM32F107RB, STM32F107VB STM32F107RC, STM32F107VC Doc ID 15274 Rev 6 1/103 www.st.com 1 Contents STM32F105xx, STM32F107xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2/103 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 ARM(R) CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . . 13 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs) 18 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 19 2.3.21 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 20 2.3.23 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.25 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.26 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.27 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.3.29 Contents Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 36 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.8 PLL, PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54 5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Doc ID 15274 Rev 6 3/103 Contents 6 7 STM32F105xx, STM32F107xx Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 87 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A.1 USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 A.2 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.3 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A.4 USB OTG FS interface + Ethernet/I2S interface solutions . . . . . . . . . . . . 96 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4/103 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Doc ID 15274 Rev 6 5/103 List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/103 STM32F105xx, STM32F107xx USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Dynamic characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 LQPF100 - 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 84 LQFP64 - 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 85 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Applicative current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view. . . . . . . . 23 STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 24 STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 70 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 77 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 77 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 83 LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 LQFP64 - 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Doc ID 15274 Rev 6 7/103 List of figures Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. 8/103 STM32F105xx, STM32F107xx Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 USB OTG FS + I2S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 1 Introduction Introduction This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family. The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F105xx and STM32F107xx connectivity line family incorporates the highperformance ARM(R) CortexTM-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 256 Kbytes and SRAM 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx only. The STM32F105xx and STM32F107xx connectivity line family operates in the -40 to +105 C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F105xx and STM32F107xx connectivity line family offers devices in three different package types: from 64 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F105xx and STM32F107xx connectivity line microcontroller family suitable for a wide range of applications such as motor drives and application control, medical and handheld equipment, industrial applications, PLCs, inverters, printers, and scanners, alarm systems, video intercom, HVAC and home audio equipment. Doc ID 15274 Rev 6 9/104 Description 2.1 STM32F105xx, STM32F107xx Device overview Figure 1 shows the general block diagram of the device family. Table 2. STM32F105xx and STM32F107xx features and peripheral counts Peripherals(1) Flash memory in Kbytes STM32F105Rx 64 128 STM32F107Rx 256 128 256 SRAM in Kbytes 64 128 256 STM32F107Vx 128 256 64 Package LQFP 100 LQFP64 Ethernet Timers STM32F105Vx No Yes General-purpose 4 Advanced-control 1 Basic 2 SPI(I2S)(2) 2C I Communication USART interfaces USB OTG FS No Yes 3(2) 3(2) 3(2) 2 1 2 1 5 Yes 2 51 80 12-bit ADC Number of channels 2 16 12-bit DAC Number of channels 2 2 CPU frequency 72 MHz Operating voltage Operating temperatures LQFP100 3(2) CAN GPIOs LQFP100, BGA100 2.0 to 3.6 V Ambient temperatures: -40 to +85 C /-40 to +105 C Junction temperature: -40 to + 125 C 1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I2S audio mode. 10/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.2 Description Full compatibility throughout the family The STM32F105xx and STM32F107xx constitute the connectivity line family whose members are fully pin-to-pin, software and feature compatible. The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) and high-density (STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle. Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family(1) STM32 Low-density device STM32F103xx devices Medium-density STM32F103xx devices High-density STM32F103xx devices STM32F105xx STM32F107xx Flash size (KB) 16 32 32 64 128 256 384 512 64 128 256 128 256 RAM size (KB) 6 10 10 20 20 48 64 64 64 64 64 64 64 144 pins 100 pins 2 x USARTs 64 pins 2 x 16-bit timers 1 x SPI, 1 x I2C, USB, CAN, 1 x PWM timer 2 x ADCs 48 pins 5 x USARTs, 5 x USARTs 4 x 16-bit timers, 4 x 16-bit timers, 2 x basic timers, 3 x USARTs 2 x basic timers, 3 x SPIs, 3 x SPIs, 2 2 x USARTs 3 x 16-bit 2 x I Ss, 2 x I2Cs, USB, 2 x I2Ss, timers 2 x 16-bit CAN, 2 x PWM timers 2 x I2Cs, 2 x SPIs, timers 3 x ADCs, 2 x DACs, 2 USB OTG FS, 2 x I Cs, USB, 1 x SDIO, FSMC (1001 x SPI, 2 x CANs, CAN, (2) 1 x I2C, and 144-pin packages ) 1 x PWM timer, USB, CAN, 1 x PWM timer 2 x ADCs, 2 x ADCs 1 x PWM 2 x DACs timer 2 x ADCs 5 x USARTs, 4 x 16-bit timers, 2 x basic timers, 3 x SPIs, 2 x I2S, 1 x I2C, USB OTG FS, 2 x CANs, 1 x PWM timer, 2 x ADCs, 2 x DACs, Ethernet 36 pins 1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by the application. 2. Ports F and G are not available in devices delivered in 100-pin packages. Doc ID 15274 Rev 6 11/104 Description STM32F105xx, STM32F107xx 2.3 Overview Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram TPIU SW/JTAG ETM Trace/Trig Ibus Cortex-M3 CPU GP DMA1 Ethernet MAC 10/100 DMA Ethernet NRST VDDA VSSA @VDD XTAL osc 3-25 MHz OSC_IN OSC_OUT C_O IWDG PCLK1 PCLK2 HCLK FCLK PLL3 Standby interface @V VBAT =1.8 V to 3.6 V BAT AHB XTAL 32kHz Bac kup register RTC AWU OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT Backup interface AHB to APB2 AHB to APB1 PD[15:0] GPIO port D PE[15:0] GPIO port E APB2 : F max = 72 MHz GPIO port C APB1 : Fmax = 36 MHz EXT.IT WKUP PC[15:0] TIM1 SPI1 WWDG USART1 TIM2 4 Channels , ETR as AF TIM3 4 Channels , ETR as AF TIM4 4 Channels , ETR as AF TIM5 4 Channel s, ETR as A F RX,TX, CTS, RTS, CK as AF USART2 USART3 UART4 UART5 RX,TX, CTS, RTS, CK as AF RX,TX as AF RX,TX as AF SPI2 2x(8x16b it) / I2S2(1) MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF SPI3 2x(8x16b it) / I2S3 MOSI/SD, MISO, MCK, SCK/CK, NSS/WS as AF I2C1 SCL,SDA, SMBA as AF I2C2 SCL,SDA,SMBA as AF bx CAN1 CAN1_TX as AF CAN1_RX as AF SRAM 512B Temp sensor VREF- VREF+ POR / PDR USB OTG FS GPIO P port B 16 ADC12_INs common to ADC1 & ADC2 Supply supervision Int @VDDA DPRAM 2 KB DPRAM 2 KB PB[ 15:0] RX,TX, CTS, RTS, CK as AF POR Reset PLL2 Reset & clock control VSS PVD PLL3 GP DMA2 GPIO P port A MOSI,MISO, SCK,NSS as AF RC HS PLL PA[ 15:0] 4 Channels 4 compl. Channels BKIN, ETR input as AF @VDDA 7 channels SRAM 1.25 KB 80 AF 64 bit RC LS 5 channels VDD = 2 to 3.6 V @VDD Bus Matri x NVIC SOF VBUS ID DM DP Flash 256 KB SRAM 64 KB System MII_TXD[3:0]/RMII_TXD[1:0] MII_TX_CLK/RMII_TX_CLK MII_TX_EN/RMII_TX_EN MII_RXD[3:0]/RMII_RXD[1:0] MII_RX_ER/RMII_RX_ER MII_RX_CLK/RMII_REF_CLK MII_RX_DV/RMII_CRS_DV MII_CRS MII_COL/RMII_COL MDC MDIO PPS_OUT Voltage reg. 3.3 V to 1.8 V Dbus Fmax : 72 MHz Power VDD18 Interface as AF NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as A F Flashl obl TRACECLK TRACED[0:3] bx CAN2 12bi t ADC1 IF 12bit ADC2 IF CAN2_TX a s AF CAN2_RX as AF TIM6 IF 12bit DAC1 IF DAC_OUT1 as AF TIM7 12bit DAC 2 DAC_OUT2 as AF @VDDA @VDDA ai15411 1. TA = -40 C to +85 C (suffix 6, see Table 62) or -40 C to +105 C (suffix 7, see Table 62), junction temperature up to 105 C or 125 C, respectively. 2. AF = alternate function on I/O port pin. 12/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.3.1 Description ARM(R) CortexTM-M3 core with embedded Flash and SRAM The ARM CortexTM-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 64 to 256 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. Doc ID 15274 Rev 6 13/104 Description 2.3.6 STM32F105xx, STM32F107xx External interrupt/event controller (EXTI) The external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. Refer to Figure 55: USB OTG FS + Ethernet solution on page 96. The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy error. Refer to Figure 56: USB OTG FS + I2S (Audio) solution on page 96. To configure the PLLs, please refer to Table 63 on page 97, which provides PLL configurations according to the application type. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options: Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode (DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions. The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For full details about the boot loader, please refer to AN2606. 14/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.3.9 2.3.10 Description Power supply schemes VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. 2.3.12 Low-power modes The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB OTG FS wakeup. Doc ID 15274 Rev 6 15/104 Description STM32F105xx, STM32F107xx Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.13 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced control timers TIMx, DAC, I2S and ADC. In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for more information). 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. For more information, please refer to AN2604: "STM32F101xx and STM32F103xx RTC calibration", available from www.st.com. 16/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.3.15 Description Timers and watchdogs The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIMx (TIM2, TIM3, TIM4, TIM5) 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Advanced-control timer (TIM1) The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Doc ID 15274 Rev 6 17/104 Description STM32F105xx, STM32F107xx Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.16 A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F105xx and STM32F107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. 18/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Description USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.18 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC/SDHC(a) modes. All SPIs can be served by the DMA controller. 2.3.19 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 96 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see Section 2.3.7: Clocks and startup). Please refer to the "Audio frequency precision" tables provided in the "Serial peripheral interface (SPI)" section of the STM32F10xxx reference manual. 2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral not available on STM32F105xx devices. The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz (RMII) output from the STM32F107xx. The STM32F107xx includes the following features: Supports 10 and 100 Mbit/s rates Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F105xx/STM32F107xx reference manual for details) Tagged MAC frame support (VLAN support) Half-duplex (CSMA/CD) and full-duplex operation MAC control sublayer (control frames) support a. SDHC = Secure digital high capacity. Doc ID 15274 Rev 6 19/104 Description 2.3.21 STM32F105xx, STM32F107xx 32-bit CRC generation and removal Several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with the timestamp comparator connected to the TIM2 trigger input Triggers interrupt when system time becomes greater than target time Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral. 2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS) The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG fullspeed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: 2.3.23 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral) 4 bidirectional endpoints HNP/SNP/IP inside (no need for any external resistor) for OTG/Host modes, a power switch is needed in case bus-powered devices are connected the SOF output can be used to synchronize the external audio DAC clock in isochronous mode in accordance with the USB 2.0 Specification, the supported transfer speeds are: - in Host mode: full speed and low speed - in Device mode: full speed GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 20/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 2.3.24 Description Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations. 2.3.25 ADCs (analog-to-digital converters) Two 12-bit analog-to-digital converters are embedded into STM32F105xx and STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.26 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: two DAC converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channel independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Doc ID 15274 Rev 6 21/104 Description STM32F105xx, STM32F107xx Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.27 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.28 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.29 Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 22/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Pinouts and pin description 3 Pinouts and pin description Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view 1 A 2 PC14PC13OSC32_IN TAMPER-RTC 3 4 5 6 7 8 9 10 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12 C OSC_IN VSS_5 PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11 D OSC_OUT VDD_5 PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10 E NRST PC2 PE6 VSS_4 VSS_3 VSS_2 VSS_1 PD1 PC9 PC7 F PC0 PC1 PC3 VDD_4 VDD_3 VDD_2 VDD_1 NC PC8 PC6 G VSSA PA0-WKUP PA4 PC4 PB2 PE10 PE14 PB15 PD11 PD15 H VREF- PA1 PA5 PC5 PE7 PE11 PE15 PB14 PD10 PD14 J VREF+ PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13 K VDDA PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12 AI16001c Doc ID 15274 Rev 6 23/104 Pinouts and pin description STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3. STM32F105xx, STM32F107xx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 ai14391 24/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 Figure 4. Pinouts and pin description ai14392 Doc ID 15274 Rev 6 25/104 Pinouts and pin description Pin definitions LQFP64 LQFP100 Pin name Type(1) I / O Level(2) Alternate functions(4) BGA100 Table 5. STM32F105xx, STM32F107xx Main function(3) (after reset) A3 - 1 PE2 I/O FT PE2 TRACECK B3 - 2 PE3 I/O FT PE3 TRACED0 C3 - 3 PE4 I/O FT PE4 TRACED1 D3 - 4 PE5 I/O FT PE5 TRACED2 E3 - 5 PE6 I/O FT PE6 TRACED3 B2 1 6 VBAT S A2 2 7 A1 3 8 B1 4 9 C2 - 10 VSS_5 S VSS_5 D2 - 11 VDD_5 S VDD_5 C1 5 12 OSC_IN I OSC_IN D1 6 13 OSC_OUT O OSC_OUT E1 7 14 NRST I/O NRST F1 8 15 PC0 I/O PC0 ADC12_IN10 F2 9 16 PC1 I/O PC1 ADC12_IN11/ ETH_MII_MDC/ ETH_RMII_MDC E2 10 17 PC2 I/O PC2 ADC12_IN12/ ETH_MII_TXD2 F3 11 18 PC3 I/O PC3 ADC12_IN13/ ETH_MII_TX_CLK G1 12 19 VSSA S VSSA H1 - 20 VREF- S VREF- J1 - 21 VREF+ S VREF+ K1 13 22 VDDA S VDDA Pins G2 14 23 H2 15 24 26/104 PC13-TAMPERI/O RTC(5) Default VBAT PC13(6) TAMPER-RTC I/O PC14(6) OSC32_IN PC15I/O OSC32_OUT(5) PC15(6) OSC32_OUT PC14OSC32_IN(5) PA0-WKUP PA1 I/O I/O PA0 WKUP/USART2_CTS(7) ADC12_IN0/TIM2_CH1_ETR TIM5_CH1/ ETH_MII_CRS_WKUP PA1 USART2_RTS(7)/ ADC12_IN1/ TIM5_CH2 /TIM2_CH2(7)/ ETH_MII_RX_CLK/ ETH_RMII_REF_CLK Doc ID 15274 Rev 6 Remap STM32F105xx, STM32F107xx Pin definitions (continued) J2 16 25 Pin name PA2 Type(1) LQFP100 LQFP64 BGA100 Pins I / O Level(2) Table 5. Pinouts and pin description I/O Alternate functions(4) Main function(3) (after reset) Default PA2 USART2_TX(7)/ TIM5_CH3/ADC12_IN2/ TIM2_CH3 (7)/ ETH_MII_MDIO/ ETH_RMII_MDIO USART2_RX(7)/ TIM5_CH4/ADC12_IN3 / TIM2_CH4(7)/ ETH_MII_COL Remap K2 17 26 PA3 I/O PA3 E4 18 27 VSS_4 S VSS_4 F4 19 28 VDD_4 S VDD_4 G3 20 29 PA4 I/O PA4 SPI1_NSS(7)/DAC_OUT1 / USART2_CK(7) / ADC12_IN4 H3 21 30 PA5 I/O PA5 SPI1_SCK(7) / DAC_OUT2 / ADC12_IN5 J3 PA6 I/O PA6 SPI1_MISO(7)/ADC12_IN6 / TIM3_CH1(7) TIM1_BKIN TIM1_CH1N 22 31 SPI3_NSS/I2S3_WS K3 23 32 PA7 I/O PA7 SPI1_MOSI(7)/ADC12_IN7 / TIM3_CH2(7)/ ETH_MII_RX_DV(8)/ ETH_RMII_CRS_DV G4 24 33 PC4 I/O PC4 ADC12_IN14/ ETH_MII_RXD0(8)/ ETH_RMII_RXD0 H4 25 34 PC5 I/O PC5 ADC12_IN15/ ETH_MII_RXD1(8)/ ETH_RMII_RXD1 J4 26 35 PB0 I/O PB0 ADC12_IN8/TIM3_CH3/ ETH_MII_RXD2(8) TIM1_CH2N K4 27 36 PB1 I/O PB1 ADC12_IN9/TIM3_CH4(7)/ ETH_MII_RXD3(8) TIM1_CH3N G5 28 37 PB2 I/O FT PB2/BOOT1 H5 - 38 PE7 I/O FT PE7 TIM1_ETR J5 - 39 PE8 I/O FT PE8 TIM1_CH1N K5 - 40 PE9 I/O FT PE9 TIM1_CH1 - - - VSS_7 S - - - VDD_7 S G6 - 41 PE10 I/O FT PE10 TIM1_CH2N H6 - 42 PE11 I/O FT PE11 TIM1_CH2 J6 - 43 PE12 I/O FT PE12 TIM1_CH3N Doc ID 15274 Rev 6 27/104 Pinouts and pin description Pin definitions (continued) Alternate functions(4) LQFP64 LQFP100 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 5. STM32F105xx, STM32F107xx K6 - 44 PE13 I/O FT PE13 TIM1_CH3 G7 - 45 PE14 I/O FT PE14 TIM1_CH4 H7 - 46 PE15 I/O FT PE15 TIM1_BKIN 29 47 PB10 I/O FT PB10 I2C2_SCL(8)/USART3_TX(7)/ ETH_MII_RX_ER TIM2_CH3 K7 30 48 PB11 I/O FT PB11 I2C2_SDA(8)/USART3_RX(7)/ ETH_MII_TX_EN/ ETH_RMII_TX_EN TIM2_CH4 E7 31 49 VSS_1 S VSS_1 F7 32 50 VDD_1 S VDD_1 J7 K8 33 51 Pin name PB12 I/O FT Default PB12 SPI2_NSS(8)/I2S2_WS(8)/ I2C2_SMBA(8) / USART3_CK(7)/ TIM1_BKIN(7) / CAN2_RX/ ETH_MII_TXD0/ ETH_RMII_TXD0 Remap 34 52 PB13 I/O FT PB13 SPI2_SCK(8) / I2S2_CK(8) / USART3_CTS(7)/ TIM1_CH1N/CAN2_TX/ ETH_MII_TXD1/ ETH_RMII_TXD1 H8 35 53 PB14 I/O FT PB14 SPI2_MISO(8) / TIM1_CH2N / USART3_RTS(7) G8 36 54 PB15 I/O FT PB15 SPI2_MOSI(8) / I2S2_SD(8) / TIM1_CH3N(7) K9 - 55 PD8 I/O FT PD8 USART3_TX/ ETH_MII_RX_DV/ ETH_RMII_CRS_DV J9 - 56 PD9 I/O FT PD9 USART3_RX/ ETH_MII_RXD0/ ETH_RMII_RXD0 H9 - 57 PD10 I/O FT PD10 USART3_CK/ ETH_MII_RXD1/ ETH_RMII_RXD1 G9 - 58 PD11 I/O FT PD11 USART3_CTS/ ETH_MII_RXD2 K10 - 59 PD12 I/O FT PD12 TIM4_CH1 / USART3_RTS/ ETH_MII_RXD3 J10 - 60 PD13 I/O FT PD13 TIM4_CH2 H10 - 61 PD14 I/O FT PD14 TIM4_CH3 J8 28/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Pin definitions (continued) LQFP64 LQFP100 G10 - 62 Pin name Type(1) BGA100 Pins I / O Level(2) Table 5. Pinouts and pin description Alternate functions(4) Main function(3) (after reset) Default Remap PD15 I/O FT PD15 F10 37 63 PC6 I/O FT PC6 I2S2_MCK/ TIM3_CH1 E10 38 64 PC7 I/O FT PC7 I2S3_MCK TIM3_CH2 F9 39 65 PC8 I/O FT PC8 TIM3_CH3 E9 40 66 PC9 I/O FT PC9 TIM3_CH4 D9 41 67 PA8 I/O FT PA8 USART1_CK/OTG_FS_SOF / TIM1_CH1(8)/MCO C9 42 68 PA9 I/O FT PA9 USART1_TX(7)/ TIM1_CH2(7)/ OTG_FS_VBUS D10 43 69 PA10 I/O FT PA10 USART1_RX(7)/ TIM1_CH3(7)/OTG_FS_ID C10 44 70 PA11 I/O FT PA11 USART1_CTS / CAN1_RX / TIM1_CH4(7)/OTG_FS_DM B10 45 71 PA12 I/O FT PA12 USART1_RTS / OTG_FS_DP / CAN1_TX(7) / TIM1_ETR(7) A10 46 72 PA13 I/O FT JTMS-SWDIO F8 - 73 TIM4_CH4 PA13 Not connected E6 47 74 VSS_2 S VSS_2 F6 48 75 VDD_2 S VDD_2 A9 49 76 PA14 I/O FT JTCK-SWCLK A8 50 77 PA15 I/O FT JTDI SPI3_NSS / I2S3_WS TIM2_CH1_ETR / PA15 SPI1_NSS B9 51 78 PC10 I/O FT PC10 UART4_TX USART3_TX/ SPI3_SCK/I2S3_CK B8 52 79 PC11 I/O FT PC11 UART4_RX USART3_RX/ SPI3_MISO C8 53 80 PC12 I/O FT PC12 UART5_TX USART3_CK/ SPI3_MOSI/I2S3_SD PA14 - - 81 PD0 I/O FT PD0 OSC_IN(9)/CAN1_RX - - 82 PD1 I/O FT PD1 OSC_OUT(9)/CAN1_TX B7 54 83 PD2 I/O FT PD2 C7 - 84 PD3 I/O FT PD3 USART2_CTS D7 - 85 PD4 I/O FT PD4 USART2_RTS B6 - 86 PD5 I/O FT PD5 USART2_TX C6 - 87 PD6 I/O FT PD6 USART2_RX D6 - 88 PD7 I/O FT PD7 USART2_CK TIM3_ETR / UART5_RX Doc ID 15274 Rev 6 29/104 Pinouts and pin description Pin definitions (continued) Pin name Type(1) LQFP100 LQFP64 BGA100 Pins I / O Level(2) Table 5. STM32F105xx, STM32F107xx Alternate functions(4) Main function(3) (after reset) Default Remap A7 55 89 PB3 I/O FT JTDO SPI3_SCK / I2S3_CK PB3 / TRACESWO/ TIM2_CH2 / SPI1_SCK A6 56 90 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1/ SPI1_MISO C5 57 91 PB5 I/O PB5 B5 58 92 PB6 I/O FT PB6 I2C1_SCL(7)/TIM4_CH1(7) USART1_TX/CAN2_TX A5 59 93 PB7 I/O FT PB7 I2C1_SDA(7)/TIM4_CH2(7) USART1_RX D5 60 94 BOOT0 B4 61 95 PB8 PB8 TIM4_CH3(7)/ ETH_MII_TXD3 I2C1_SCL/CAN1_RX I2C1_SDA / CAN1_TX I I/O FT I2C1_SMBA / SPI3_MOSI / TIM3_CH2/SPI1_MOSI/ ETH_MII_PPS_OUT / I2S3_SD CAN2_RX ETH_RMII_PPS_OUT BOOT0 A4 62 96 PB9 I/O FT PB9 TIM4_CH4(7) D4 - 97 PE0 I/O FT PE0 TIM4_ETR C4 - 98 PE1 I/O FT PE1 E5 63 99 VSS_3 S VSS_3 F5 64 100 VDD_3 S VDD_3 1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT = 5 V tolerant. All I/Os are VDD capable. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used. 9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. 30/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 4 Memory mapping Memory mapping The memory map is shown in Figure 5. Figure 5. Memory map AHB Reserved 0x5000 0400 - 0x5FFF FFFF USB OTG FS 0x5000 0000 - 0x5003 FFFF Reserved 0x4003 0000 - 0x4FFF FFFF Ethernet Reserved 0x4002 8000 - 0x4002 9FFF 0x4002 3000 - 0x4002 33FF Reserved 0x4002 2400 - 0x4002 2FFF Flash interface 0x4002 2000 - 0x4002 23FF Reserved RCC Reserved 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0800 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF DMA2 DMA1 Reserved 0xFFFF FFFF 0xE000 0000 0xDFFF FFFF 512-Mbyte block 7 Cortex-M3's internal peripherals APB2 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 Not used 0xB000 0000 0xAFFF FFFF 0x8000 0000 0x7FFF FFFF APB1 512-Mbyte block 3 Not used 0x6000 0000 0x5FFF FFFF 512-Mbyte block 2 Peripherals 0x4000 0000 0x3FFF FFFF 512-Mbyte block 1 SRAM 0x2000 0000 0x1FFF FFFF 512-Mbyte block 0 Code 0x0000 0000 USART1 Reserved SPI1 TIM1 ADC2 ADC1 Reserved Port E Port D Port C Port B Port A EXTI AFIO Reserved DAC PWR 512-Mbyte block 4 Not used Reserved SRAM (aliased by bit-banding) Option bytes System memory Reserved Flash Reserved Aliased to Flash or system memory depending on BOOT pins Doc ID 15274 Rev 6 0x4002 3400 - 0x4002 7FFF CRC 0x4001 3C00 - 0x4001 FFFF 0x4001 3800 - 0x4001 3BFF 0x4001 3400 - 0x4001 37FF 0x4001 3000 - 0x4001 33FF 0x4001 2C00 - 0x4001 2FFF 0x4001 2800 - 0x4001 2BFF 0x4001 2400 - 0x4001 27FF 0x4001 1C00 - 0x4001 23FF 0x4001 1800 - 0x4001 1BFF 0x4001 1400 - 0x4001 17FF 0x4001 1000 - 0x4001 13FF 0x4001 0C00 - 0x4001 0FFF 0x4001 0800 - 0x4001 0BFF 0x4001 0400 - 0x4001 07FF 0x4001 0000 - 0x4001 3FFF 0x4000 7800 - 0x4000 FFFF 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF BKP 0x4000 6C00 - 0x4000 6FFF bxCAN2 0x4000 6800 - 0x4000 6BFF bxCAN1 Reserved 0x4000 6400 - 0x4000 67FF I2C2 0x4000 5800 - 0x4000 5BFF 0x4000 5C00 - 0x4000 63FF I2C1 0x4000 5400 - 0x4000 57FF UART5 UART4 0x4000 5000 - 0x4000 53FF USART3 0x4000 4800 - 0x4000 4BFF 0x4000 4C00 - 0x4000 4FFF USART2 0x4000 4400 - 0x4000 47FF Reserved 0x4000 4000 - 0x4000 43FF SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF Reserved 0x4000 3400 - 0x4000 37FF IWDG 0x4000 3000 - 0x4000 33FF WWDG 0x4000 2C00 - 0x4000 2FFF RTC 0x4000 2800 - 0x4000 2BFF Reserved TIM7 0x4000 1800 - 0x4000 27FF 0x4000 1400 - 0x4000 17FF TIM6 0x4000 1000 - 0x4000 13FF TIM5 0x4000 0C00 - 0x4000 0FFF TIM4 0x4000 0800 - 0x4000 0BFF TIM3 0x4000 0400 - 0x4000 07FF TIM2 0x4000 0000 - 0x4000 03FF 0x3FFF FFFF 0x2001 0000 0x2000 FFFF 0x2000 0000 0x1FFF F800 - 0x1FFF FFFF 0x1FFF B000 - 0x1FFF F7FF 0x1FFF AFFF 0x0804 0000 0x0803 FFFF 0x0800 0000 0x07FF FFFF 0x0004 0000 0x0003 FFFF 0x0000 0000 ai15412b 31/104 Electrical characteristics STM32F105xx, STM32F107xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 6. Pin loading conditions Figure 7. Pin input voltage STM32F10xxx pin STM32F10xxx pin C = 50 pF VIN ai15664 32/104 Doc ID 15274 Rev 6 ai15665 STM32F105xx, STM32F107xx 5.1.6 Electrical characteristics Power supply scheme Figure 8. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 x 100 nF + 1 x 4.7 F VDD 1/2/3/4/5 VDDA VREF 10 nF + 1 F Regulator VSS 10 nF + 1 F VREF+ ADC/ DAC VREF- Analog: RCs, PLL, ... VSSA ai14125d Caution: In Figure 8, the 4.7 F capacitor must be connected to VDD3. 5.1.7 Current consumption measurement Figure 9. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 Doc ID 15274 Rev 6 33/104 Electrical characteristics 5.2 STM32F105xx, STM32F107xx Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 6. Symbol VDD-VSS VIN(2) |VDDx| |VSSX - VSS| VESD(HBM) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five volt tolerant pin VSS - 0.3 VDD + 4.0 Input voltage on any other pin VSS - 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins 50 Variations between all the different ground pins 50 Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 7: Current characteristics for the maximum allowed injected current values. Table 7. Symbol IVDD IVSS Current characteristics Ratings Max. Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines 150 (sink)(1) 150 Output current sunk by any I/O and control pin IIO IINJ(PIN)(2) IINJ(PIN) 25 Output current source by any I/Os and control pin - 25 Injected current on five volt tolerant pins(3) -5/+0 Injected current on any other pin(4) Total injected current (sum of all I/O and control pins) Unit mA 5 (5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See Note: on page 75. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. 4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). 34/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 8. Electrical characteristics Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Operating conditions 5.3.1 General operating conditions Symbol Unit -65 to +150 C 150 C Maximum junction temperature 5.3 Table 9. Value General operating conditions Parameter Conditions Min Max fHCLK Internal AHB clock frequency 0 72 fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 Standard operating voltage 2 3.6 2 3.6 2.4 3.6 1.8 3.6 VDD VDDA (1) VBAT PD PD Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Must be the same potential as VDD(2) Backup operating voltage Unit MHz V V LFBGA100 Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for LQFP100 suffix 7(3) LQFP64 V 500 434 mW 444 Power dissipation at TA = 85 C LQFP100 for suffix 6 or TA = 105 C for LQFP64 suffix 7(4) 434 mW 444 Ambient temperature for 6 suffix version Maximum power dissipation -40 85 Low power dissipation -40 105 Ambient temperature for 7 suffix version Maximum power dissipation -40 105 Low power dissipation -40 125 6 suffix version -40 105 7 suffix version -40 125 (5) C TA TJ (5) C Junction temperature range C 1. When the ADC is used, refer to Table 52: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. Doc ID 15274 Rev 6 35/104 Electrical characteristics 5.3.2 STM32F105xx, STM32F107xx Operating conditions at power-up / power-down Subject to general operating conditions for TA. Table 10. Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.3 Conditions Min Max VDD rise time rate 0 VDD fall time rate 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11. Embedded reset and power control block characteristics Symbol Parameter Conditions Programmable voltage detector level selection VPVD VPVDhyst(2) PVD hysteresis VPOR/PDR Power on/power down reset threshold VPDRhyst (2) TRSTTEMPO (2) Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V 100 Falling edge 1.8(1) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V PDR hysteresis 40 Reset temporization 1 1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production. 36/104 mV Doc ID 15274 Rev 6 2.5 mV 4.5 ms STM32F105xx, STM32F107xx 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.16 1.20 1.26 V -40 C < TA < +85 C 1.16 1.20 1.24 V 5.1 17.1(2) s 10 mV 100 ppm/C ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) VDD = 3 V 10 mV Temperature coefficient 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 9: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Doc ID 15274 Rev 6 37/104 Electrical characteristics Table 13. STM32F105xx, STM32F107xx Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 C 72 MHz 68 68.4 48 MHz 49 49.2 36 MHz 38.7 38.9 24 MHz 27.3 27.9 16 MHz 20.2 20.5 8 MHz 10.2 10.8 72 MHz 32.7 32.9 48 MHz 25 25.2 External clock(3), all 36 MHz peripherals disabled 24 MHz 20.3 20.6 14.8 15.1 16 MHz 11.2 11.7 8 MHz 6.6 7.2 External clock(2), all peripherals enabled IDD Unit TA = 85 C Supply current in Run mode mA 1. Based on characterization, not tested in production. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions IDD Unit TA = 85 C TA = 105 C 72 MHz 65.5 66 48 MHz 45.4 46 36 MHz 35.5 36.1 24 MHz 25.2 25.6 16 MHz 18 18.5 8 MHz 10.5 11 72 MHz 31.4 31.9 48 MHz 27.8 28.2 External clock(3), all 36 MHz peripherals disabled 24 MHz 17.6 18.3 13.1 13.8 16 MHz 10.2 10.9 8 MHz 6.1 7.8 External clock(2), all peripherals enabled Supply current in Run mode fHCLK 1. Based on characterization, tested in production at VDD max, fHCLK max.. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 38/104 Doc ID 15274 Rev 6 mA STM32F105xx, STM32F107xx Table 15. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled Supply current in Sleep mode IDD External clock(3), all peripherals disabled fHCLK Unit TA = 85 C TA = 105 C 72 MHz 48.4 49 48 MHz 33.9 34.4 36 MHz 26.7 27.2 24 MHz 19.3 19.8 16 MHz 14.2 14.8 8 MHz 8.7 9.1 72 MHz 10.1 10.6 48 MHz 8.3 8.75 36 MHz 7.5 8 24 MHz 6.6 7.1 16 MHz 6 6.5 8 MHz 2.5 3 mA 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 16. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2.0 V = 2.4 V = 3.3 V 85 C 105 C Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode, low- IDD speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON, independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current Max 1.1 32 33 600 1300 25 26 590 1280 3 3.8 - - 2.8 3.6 - - 1.9 2.1 5(2) 6.5(2) 1.2 1.4 2.1(2) 2.3(2) A 1. Typical values are measured at TA = 25 C. 2. Based on characterization, not tested in production. Doc ID 15274 Rev 6 39/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 10. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values Consumption (A) 2.5 1.8 V 2V 2.4 V 3.3 V 3.6 V 2 1.5 1 0.5 0 -40 C 25 C 70 C 85 C 105 C Temperature (C) ai17329 Figure 11. Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values 900.00 800.00 Consumption (A) 700.00 600.00 500.00 3.6 V 400.00 3.3 V 300.00 3V 200.00 2.7 V 2.4 V 100.00 0.00 -40 C 25 C 85 C Temperature (C) 40/104 Doc ID 15274 Rev 6 105 C ai17122 STM32F105xx, STM32F107xx Electrical characteristics Figure 12. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at different VDD values 900.00 Consumption (A) 800.00 700.00 600.00 500.00 3.6 V 400.00 3.3 V 300.00 3V 200.00 2.7 V 2.4 V 100.00 0.00 -40 C 25 C 85 C 105 C Temperature (C) ai17123 Figure 13. Typical current consumption in Standby mode versus temperature at different VDD values 4.50 4.00 Consumption (A) 3.50 3.00 2.50 3.6 V 2.00 3.3 V 1.50 3V 2.7 V 1.00 2.4 V 0.50 0.00 -40 C 25 C 85 C 105 C Temperature (C) ai17124 Typical current consumption The MCU is placed under the following conditions: All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 9. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 Doc ID 15274 Rev 6 41/104 Electrical characteristics Table 17. STM32F105xx, STM32F107xx Typical current consumption in Run mode, code with data processing running from Flash Typ(1) Symbol Parameter Conditions External IDD clock(3) Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK All peripherals All peripherals disabled enabled(2) 72 MHz 47.3 28.3 48 MHz 32 19.6 36 MHz 24.6 15.4 24 MHz 16.8 10.6 16 MHz 11.8 7.4 8 MHz 5.9 3.7 4 MHz 3.7 2.9 2 MHz 2.5 2 1 MHz 1.8 1.53 500 kHz 1.5 1.3 125 kHz 1.3 1.2 36 MHz 23.9 14.8 24 MHz 16.1 9.7 16 MHz 11.1 6.7 8 MHz 5.6 3.8 4 MHz 3.1 2.1 2 MHz 1.8 1.3 1 MHz 1.16 0.9 500 kHz 0.8 0.67 125 kHz 0.6 0.5 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 42/104 Doc ID 15274 Rev 6 Unit mA mA STM32F105xx, STM32F107xx Table 18. Electrical characteristics Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions All peripherals All peripherals enabled(2) disabled 72 MHz 28.2 6 48 MHz 19 4.2 36 MHz 14.7 3.4 24 MHz 10.1 2.5 16 MHz 6.7 2 8 MHz 3.2 1.3 4 MHz 2.3 1.2 2 MHz 1.7 1.16 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 36 MHz 13.7 2.6 24 MHz 9.3 1.8 16 MHz Running on high 8 MHz speed internal RC (HSI), AHB prescaler 4 MHz used to reduce the 2 MHz frequency 1 MHz 6.3 1.3 2.7 0.6 1.6 0.5 1 0.46 0.8 0.44 500 kHz 0.6 0.43 125 kHz 0.5 0.42 External clock(3) Supply current in Sleep mode IDD fHCLK Unit mA 1. Typical values are measures at TA = 25 C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with one peripheral clocked on (with only the clock applied) ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Doc ID 15274 Rev 6 43/104 Electrical characteristics Table 19. STM32F105xx, STM32F107xx Peripheral current consumption(1) Peripheral AHB Typical consumption at 25 C ETH_MAC 5.2 OTG_FS 7.7 TIM2 1.5 TIM3 1.5 TIM4 1.5 TIM5 1.5 TIM6 0.6 TIM7 0.3 SPI2 0.2 USART2 0.5 USART3 0.5 UART4 0.5 UART5 0.5 I2C1 0.5 I2C2 0.5 CAN1 0.8 CAN2 0.8 DAC 0.4 GPIO A 0.5 GPIO B 0.5 GPIO C 0.5 GPIO D 0.5 GPIO E 0.5 (2) 2.1 ADC2(2) 2.0 TIM1 1.7 SPI1 0.4 USART1 0.9 Unit mA APB1 APB2 ADC1 mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit in the ADC_CR2 register is set to 1. 44/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 5.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD VDD VHSEL OSC_IN input pin low level voltage VSS 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) OSC_IN rise or fall time(1) Cin(HSE) 5 ns 20 OSC_IN input capacitance(1) 5 DuCy(HSE) Duty cycle IL V pF 45 OSC_IN Input leakage current VSS VIN VDD 55 % 1 A 1. Guaranteed by design, not tested in production. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 21. Low-speed external user clock characteristics Symbol Parameter Conditions Min fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS tw(LSE) tw(LSE) OSC32_IN high or low time(1) 450 Typ Max Unit 32.768 1000 kHz VDD 0.7VDD V tr(LSE) tf(LSE) Cin(LSE) ns OSC32_IN rise or fall time(1) 50 OSC32_IN input capacitance(1) 5 DuCy(LSE) Duty cycle IL 0.3VDD 30 OSC32_IN Input leakage current VSS VIN VDD pF 70 % 1 A 1. Guaranteed by design, not tested in production. Doc ID 15274 Rev 6 45/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 14. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 15. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE External clock source fLSE_ext STM32F10xxx ai14140c High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 3 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 46/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 22. HSE 3-25 MHz oscillator characteristics(1) (2) Symbol fOSC_IN Electrical characteristics Parameter Conditions Oscillator frequency Typ 3 RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) i2 HSE driving current gm Oscillator transconductance tSU(HSE(4) Min RS = 30 Startup time Unit 25 MHz 200 k 30 pF VDD = 3.3 V, VIN = VSS with 30 pF load Startup Max 1 25 VDD is stabilized mA mA/V 2 ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 16. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 fHSE OSC_IN 8 MH z resonator CL2 REXT(1) RF Bias controlled gain OSC_OU T STM32F10xxx ai14128b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal Doc ID 15274 Rev 6 47/104 Electrical characteristics STM32F105xx, STM32F107xx resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. Symbol LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Parameter RF Feedback resistor C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) I2 LSE driving current gm Oscillator Transconductance Conditions Min Typ Max 5 M RS = 30 k 15 pF VDD = 3.3 V, VIN = VSS 1.4 A 5 tSU(LSE)(4) Startup time Unit VDD is stabilized A/V TA = 50 C 1.5 TA = 25 C 2.5 TA = 10 C 4 TA = 0 C 6 TA = -10 C 10 TA = -20 C 17 TA = -30 C 32 TA = -40 C 60 s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. 48/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics Figure 17. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 KH z resonator CL2 RF Bias controlled gain OSC32_OU T STM32F10xxx ai14129b Doc ID 15274 Rev 6 49/104 Electrical characteristics 5.3.7 STM32F105xx, STM32F107xx Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. High-speed internal (HSI) RC oscillator Table 24. Symbol fHSI HSI oscillator characteristics (1) Parameter Conditions Min Frequency Typ 8 DuCy(HSI) Duty cycle Accuracy of the HSI oscillator Factorycalibrated(4) tsu(HSI)(4) HSI oscillator startup time IDD(HSI)(4) HSI oscillator power consumption Unit MHz 45 User-trimmed with the RCC_CR register(2) ACCHSI Max 55 % 1(3) % TA = -40 to 105 C -2 2.5 % TA = -10 to 85 C -1.5 2.2 % TA = 0 to 70 C -1.3 2 % TA = 25 C -1.1 1.8 % 1 2 s 100 A 80 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Refer to application note AN2868 "STM32F10xxx internal RC oscillator (HSI) calibration" available from the ST website www.st.com. 3. Guaranteed by design, not tested in production. 4. Based on characterization, not tested in production. Low-speed internal (LSI) RC oscillator Table 25. LSI oscillator characteristics (1) Symbol fLSI(2) Parameter Frequency tsu(LSI)(3) LSI oscillator startup time IDD(LSI)(3) LSI oscillator power consumption Min Typ Max Unit 30 40 60 kHz 85 s 1.2 A 0.65 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: 50/104 Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 26. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 s Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low power mode) 5.4 Wakeup from Standby mode 50 s s 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 5.3.8 PLL, PLL2 and PLL3 characteristics The parameters given in Table 27 and Table 28 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Min(1) Max(1) Unit PLL input clock(2) 3 12 MHz Pulse width at high level 30 fPLL_OUT PLL multiplier output clock 18 72 MHz fVCO_OUT PLL VCO output 36 144 MHz tLOCK PLL lock time 350 s Jitter Cycle-to-cycle jitter 300 ps Symbol fPLL_IN Parameter ns 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Table 28. PLL2 and PLL3 characteristics Min(1) Max(1) Unit PLL input clock 3 5 MHz Pulse width at high level 30 fPLL_OUT PLL multiplier output clock 40 74 MHz fVCO_OUT PLL VCO output 80 148 MHz tLOCK PLL lock time 350 s Jitter Cycle-to-cycle jitter 400 ps Symbol Parameter (2) fPLL_IN ns 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Doc ID 15274 Rev 6 51/104 Electrical characteristics 5.3.9 STM32F105xx, STM32F107xx Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 29. Symbol tprog tERASE tME IDD Vprog Flash memory characteristics Min(1) Typ Max(1) Unit 16-bit programming time TA = -40 to +105 C 40 52.5 70 s Page (1 KB) erase time TA = -40 to +105 C 20 40 ms Mass erase time TA = -40 to +105 C 20 40 ms Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 A 3.6 V Parameter Conditions Supply current Programming voltage 2 1. Guaranteed by design, not tested in production. Table 30. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 (2) 1 kcycle 10 at TA = 105 C kcycles(2) at TA = 55 C Unit Typ Max 10 20 1. Based on characterization, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 52/104 Doc ID 15274 Rev 6 kcycles Years STM32F105xx, STM32F107xx Electrical characteristics Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 31. They are based on the EMS levels and classes defined in application note AN1709. Table 31. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP100, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK = 75 MHz, conforms to induce a functional disturbance IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 75 MHz, conforms to IEC 61000-4-2 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: Corrupted program counter Unexpected reset Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Doc ID 15274 Rev 6 53/104 Electrical characteristics STM32F105xx, STM32F107xx Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 32. Symbol SEMI 5.3.11 EMI characteristics Parameter Peak level Max vs. [fHSE/fHCLK] Monitored frequency band Conditions VDD = 3.3 V, TA = 25 C, LQFP100 package compliant with IEC61967-2 Unit 8/48 MHz 8/72 MHz 0.1 to 30 MHz 9 9 30 to 130 MHz 26 13 130 MHz to 1GHz 25 31 SAE EMI Level 4 4 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 33. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 C conforming to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 C conforming to JESD22-C101 II 500 Unit V 1. Based on characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 34. Symbol LU 54/104 Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Doc ID 15274 Rev 6 Class II level A STM32F105xx, STM32F107xx 5.3.12 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 35 Table 35. I/O current injection susceptibility Functional susceptibility Symbol IINJ 5.3.13 Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 Unit mA I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 36. Symbol VIL VIH I/O static characteristics Parameter Conditions Min Typ Max Unit Standard IO input low level voltage -0.3 0.28*(VDD-2 V)+0.8 V V IO FT(1) input low level voltage -0.3 0.32*(VDD-2V)+0.75 V V Standard IO input high level voltage 0.41*(VDD-2 V)+1.3 V VDD+0.3 V IO FT(1) input high level voltage VDD > 2 V VDD 2 V 5.5 0.42*(VDD-2 V)+1 V Doc ID 15274 Rev 6 V 5.2 55/104 Electrical characteristics Table 36. I/O static characteristics Symbol Vhys Ilkg STM32F105xx, STM32F107xx Parameter Conditions Unit mV IO FT Schmitt trigger voltage hysteresis(2) 5% VDD(3) mV Weak pulldown equivalent resistor(5) (4) VSS VIN VDD Standard I/Os 1 VIN= 5 V, I/O FT 3 All pins except for PA10 A 30 VIN = VSS 50 k PA10 All pins except for PA10 40 VIN = VDD 8 11 15 30 40 50 k PA10 8 11 I/O pin capacitance CIO Max 200 Weak pullup equivalent resistor(5) RPD Typ Standard IO Schmitt trigger voltage hysteresis(2) Input leakage current RPU Min 15 5 pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 18 and Figure 19 for standard I/Os, and in Figure 20 and Figure 21 for 5 V tolerant I/Os. Figure 18. Standard I/O input characteristics - CMOS port 6)(6), 6 6 $$ NT 6 )( UIREME DARD REQ /3 STAN #- 7)(MIN 7),MAX 6 $$ 6 )( T 6 ),6 $$ RD REQUIREMEN #-/3 STANDA )NPUT RANGE NOT GUARANTEED 6 6), $$ 6$$ 6 AIB 56/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics Figure 19. Standard I/O input characteristics - TTL port 6)(6), 6 7)(MIN 44, REQUIREMENTS 6)( 6 6 $$ 6 )( 7),MAX )NPUT RANGE NOT GUARANTEED 6 ),6 $$ 44, REQUIREMENTS 6),6 6$$ 6 AI Doc ID 15274 Rev 6 57/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 20. 5 V tolerant I/O input characteristics - CMOS port 6)(6), 6 6 $$ TS 6 )( UIREMEN ARD REQ 3 STAND #-/ 6 ),6 $$ T 6 ),6 $$ REQUIRMEN /3 STANDARD #- 6 )(6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AIB Figure 21. 5 V tolerant I/O input characteristics - TTL port 6)(6), 6 44, REQUIREMENT 6 )(6 6 6 )( $$ 7)(MIN 7),MAX )NPUT RANGE NOT GUARANTEED 6 ), 6 $$ 44, REQUIREMENTS 6 ),6 6$$ 6 AI - 58/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/-20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 37. Symbol Output voltage characteristics Parameter VOL(1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V Min Max Unit 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. Doc ID 15274 Rev 6 59/104 Electrical characteristics STM32F105xx, STM32F107xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 38, respectively. Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 38. I/O AC characteristics(1) MODEx[1:0] Symbol bit value(1) Parameter Conditions Min fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out - tEXTIpw frequency(2) Output high to low level fall time Output low to high level rise time Unit 2 MHz 125(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 125(3) fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 Max 10 MHz 25(3) CL = 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) Pulse width of external signals detected by the EXTI controller 10 ns ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 22. 3. Guaranteed by design, not tested in production. 60/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics Figure 22. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 36). Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 39. Symbol NRST pin characteristics Parameter Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage -0.5 0.8 VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis VF(NRST) V 200 Weak pull-up equivalent resistor(2) RPU (1) Unit VIN = VSS 30 NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 40 mV 50 k 100 ns ns 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Doc ID 15274 Rev 6 61/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 23. Recommended NRST pin protection VDD External reset circuit(1) RPU NRST(2) Internal reset Filter 0.1 F STM32F10x ai14132d 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 39. Otherwise the reset will not be taken into account by the device. 5.3.15 TIM timer characteristics The parameters given in Table 40 are guaranteed by design. Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 40. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max 1 tTIMxCLK 13.9 ns Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz 0 fTIMxCLK/2 MHz 0 36 MHz 16 bit 65536 tTIMxCLK 910 s 65536 x 65536 tTIMxCLK 59.6 s Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4 and TIM5 timers. 62/104 Doc ID 15274 Rev 6 Unit STM32F105xx, STM32F107xx 5.3.16 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. The STM32F105xx and STM32F107xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 41. Refer also to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 41. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) Start condition hold time 4.0 0.6 tsu(STA) Repeated Start condition setup time 4.7 0.6 tsu(STO) Stop condition setup time 4.0 0.6 s tw(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 s Cb Capacitive load for each bus line s ns 300 s 400 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a mulitple of 10 MHz in order to reach I2C fast mode maximum clock 400 kHz. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Doc ID 15274 Rev 6 63/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 24. I2C bus AC waveforms and measurement circuit VDD 4 .7 k VDD 4 .7 k 100 100 IC bus STM32F10x SDA SCL Start repeated Start Start tsu(STA) SDA tf(SDA) tr(SDA) th(STA) tsu(SDA) tw(SCLL) tsu(STO:STA) Stop th(SDA) SCL tw(SCLH) tr(SCL) tsu(STO) tf(SCL) ai14133d 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 42. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 2 1. RP = External pull-up resistance, fSCL = I C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application. 64/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 43 for SPI or in Table 44 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 43. Symbol fSCK 1/tc(SCK) SPI characteristics Parameter Conditions Min 18 Slave mode 18 8 ns 70 % MHz SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 tsu(NSS) NSS setup time Slave mode 4 tPCLK th(NSS) NSS hold time Slave mode 2 tPCLK SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 Master mode 4 Slave mode 5 Master mode 5 Slave mode 5 tsu(MI) 60 Data input setup time tsu(SI) th(MI) Data input hold time th(SI) ns ta(SO) Data output access time Slave mode, fPCLK = 20 MHz tv(SO) Data output valid time Slave mode (after enable edge) 34 tv(MO) Data output valid time Master mode (after enable edge) 8 th(SO) th(MO) Unit Master mode SPI clock frequency tr(SCK) tf(SCK) tw(SCKH) tw(SCKL) Max 3*tPCLK Slave mode (after enable edge) 32 Master mode (after enable edge) 10 Data output hold time Doc ID 15274 Rev 6 65/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) tSU(NSS) SCK Input CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 26. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 66/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15274 Rev 6 67/104 Electrical characteristics Table 44. STM32F105xx, STM32F107xx I2S characteristics Symbol Parameter fCK 1/tc(CK) I2S clock frequency tr(CK) tf(CK) I2S clock rise and fall time tw(CKH)(1) I2S clock high time Conditions Min Max Master data: 16 bits, audio freq = 48 K 1.52 1.54 Slave capacitive load CL = 50 pF I S clock low time Master fPCLK = 16 MHz, audio freq = 48 K tv(WS) (1) WS valid time Master mode th(WS) 2 (1) WS hold time tsu(WS) (1) th(WS) (1) DuCy(SCK) WS setup time MHz 0 tw(CKL)(1) 6.5 8 317 320 333 336 3 I2S2 0 I2S3 0 I2S2 4 I2S3 9 ns Master mode Slave mode WS hold time Slave mode 0 I2S slave input clock duty cycle Slave mode 30 tsu(SD_MR) (1) Unit 70 I2S2 8 I2S3 10 I2S2 3 I2S3 8 I2S2 2 I2S3 4 I2S2 2 I2S3 4 Slave transmitter (after enable edge) I2S2 23 I2S3 33 Slave transmitter (after enable edge) I2S2 29 I2S3 27 Master transmitter (after enable edge) I2S2 5 I2S3 2 Master transmitter (after enable edge) I2S2 11 I2S3 4 % Master receiver Data input setup time tsu(SD_SR) (1) Slave receiver th(SD_MR)(1) Master receiver Data input hold time th(SD_SR) (1) tv(SD_ST) (1)(3) Slave receiver Data output valid time th(SD_ST) (1) Data output hold time tv(SD_MT) (1) Data output valid time th(SD_MT) (1) Data output hold time 1. Based on design simulation and/or characterization results, not tested in production. 68/104 Doc ID 15274 Rev 6 ns STM32F105xx, STM32F107xx Electrical characteristics Figure 28. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 29. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Doc ID 15274 Rev 6 69/104 Electrical characteristics STM32F105xx, STM32F107xx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). Table 45. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 s 1. Guaranteed by design, not tested in production. Table 46. USB OTG FS DC electrical characteristics Symbol VDD Input levels Parameter Conditions USB OTG FS operating voltage Min.(1) Typ. Max.(1) Unit 3.0(2) 3.6 VDI(3) Differential input sensitivity I(USBDP, USBDM) 0.2 VCM(3) Differential common mode range Includes VDI range 0.8 2.5 VSE(3) Single ended receiver threshold 1.3 2.0 VOL Static output level low RL of 1.5 k to 3.6 V(4) VOH Static output level high RL of 15 k to VSS(4) Output levels Pull-down resistance on PA11, PA12 RPD RPU Pull-down resistance on PA9 V V 0.3 V 2.8 3.6 17 21 24 0.65 1.1 2.0 VIN = VDD Pull-up resistance on PA12 VIN = VSS 1.5 1.8 2.1 Pull-up resistance on PA9 VIN = VSS 0.25 0.37 0.55 k 1. All the voltages are measured from the local ground potential. 2. The STM32F105xx and STM32F107xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG FS drivers Figure 30. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S 70/104 tf tr ai14137 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics USB OTG FS electrical characteristics(1) Table 47. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm Rise/ fall time matching VCRS Output signal crossover voltage 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). Ethernet characteristics Table 48 showns the Ethernet operating voltage. Table 48. Ethernet DC electrical characteristics Symbol Input level Parameter VDD Ethernet operating voltage Min.(1) Max.(1) Unit 3.0 3.6 V 1. All the voltages are measured from the local ground potential. Table 49 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 31 shows the corresponding timing diagram. Figure 31. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) ai15666c Table 49. Symbol Dynamic characteristics: Ethernet MAC signals for SMI Rating Min Typ Max Unit tMDC MDC cycle time (1.71 MHz, AHB = 72 MHz) 583 583.5 584 ns td(MDIO) MDIO write data valid time 13.5 14.5 15.5 ns tsu(MDIO) Read data setup time 35 ns th(MDIO) 0 ns Read data hold time Table 50 gives the list of Ethernet MAC signals for the RMII and Figure 32 shows the corresponding timing diagram. Doc ID 15274 Rev 6 71/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 32. Ethernet RMII timing diagram RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667 Table 50. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max tsu(RXD) Receive data setup time 4 ns tih(RXD) Receive data hold time 2 ns tsu(DV) Carrier sense set-up time 4 ns tih(DV) Carrier sense hold time 2 ns td(TXEN) Transmit enable valid delay time 8 10 16 ns td(TXD) Transmit data valid delay time 7 10 16 ns Table 51 gives the list of Ethernet MAC signals for MII and Figure 32 shows the corresponding timing diagram. Figure 33. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 72/104 Unit Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 51. Electrical characteristics Dynamic characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 10 ns tih(RXD) Receive data hold time 10 ns tsu(DV) Data valid setup time 10 ns tih(DV) Data valid hold time 10 ns tsu(ER) Error setup time 10 ns tih(ER) Error hold time 10 ns td(TXEN) Transmit enable valid delay time 14 16 18 ns td(TXD) Transmit data valid delay time 13 16 20 ns CAN (controller area network) interface Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 52. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) A fADC ADC clock frequency 0.6 14 MHz fS(2) Sampling rate 0.05 1 MHz 823 kHz 17 1/fADC VREF+ V 50 k RADC(2) Sampling switch resistance 1 k CADC(2) Internal sample and hold capacitor 8 pF tCAL(2) Calibration time fTRIG(2) External trigger frequency VAIN 160(1) fADC = 14 MHz 0 (VSSA or VREFtied to ground) Conversion voltage range(3) RAIN(2) External input impedance See Equation 1 and Table 53 for details fADC = 14 MHz Doc ID 15274 Rev 6 5.9 s 83 1/fADC 73/104 Electrical characteristics Table 52. STM32F105xx, STM32F107xx ADC characteristics (continued) Symbol Parameter tlat(2) Injection trigger conversion latency tlatr(2) Regular trigger conversion latency tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) Conditions Min Typ Max Unit 0.214 s 3(4) 1/fADC 0.143 s 2(4) 1/fADC 0.107 17.1 s 1.5 239.5 1/fADC 1 s 18 s fADC = 14 MHz fADC = 14 MHz fADC = 14 MHz 0 fADC = 14 MHz 0 1 14 to 252 (tS for sampling +12.5 for successive approximation) 1/fADC 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 52. Equation 1: RAIN max formula TS R AIN < ------------------------------------------------------------- - R ADC N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 53. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (s) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Based on characterization, not tested in production. 74/104 RAIN max (k) Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 54. Symbol Electrical characteristics ADC accuracy - limited test conditions(1) Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(2) fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 3 V to 3.6 V TA = 25 C Measurements made after ADC calibration 1.3 2 1 1.5 0.5 1.5 0.7 1 0.8 1.5 Typ Max(3) 2 5 1.5 2.5 1.5 3 1 2 1.5 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Based on characterization, not tested in production. Table 55. ADC accuracy(1) (2) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 k, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 3. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Doc ID 15274 Rev 6 75/104 Electrical characteristics STM32F105xx, STM32F107xx Figure 34. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4093 (2) ET 7 (1) 6 5 4 ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) EO EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 35. Typical connection diagram using the ADC STM32F10xxx VDD RAIN(1) Sample and hold ADC converter VT 0.6 V RADC(1) AINx VAIN Cparasitic VT 0.6 V IL1 A 12-bit converter CADC(1) ai14139d 1. Refer to Table 52 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 76/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ (See note 1) 1 F // 10 nF V DDA 1 F // 10 nF V SSA/V REF(See note 1) ai14380c 1. VREF+ and VREF- inputs are available only on 100-pin packages. Figure 37. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA (See note 1) 1 F // 10 nF VREF-/VSSA (See note 1) ai14381c 1. VREF+ and VREF- inputs are available only on 100-pin packages. Doc ID 15274 Rev 6 77/104 Electrical characteristics STM32F105xx, STM32F107xx 5.3.18 DAC electrical specifications Table 56. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.6 V VSSA Ground 0 0 V RLOAD(1) Resistive load with buffer ON 5 RO(1) Impedance output with buffer OFF 15 k When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M CLOAD(1) Capacitive load 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(1) with buffer ON k 0.2 V DAC_OUT Higher DAC_OUT voltage with buffer ON max(1) DAC_OUT Lower DAC_OUT voltage min(1) with buffer OFF DAC_OUT Higher DAC_OUT voltage with buffer OFF max(1) IDDVREF+ DAC DC current consumption in quiescent mode (Standby mode) IDDA DAC DC current consumption in quiescent mode (Standby mode) DNL(2) INL(2) 78/104 Differential non linearity Difference between two consecutive code-1LSB) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) VREF+ must always be below VDDA VDDA - 0.2 0.5 V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) to (0xEAB) at VREF+ = 2.4 V mV It gives the maximum output excursion of the DAC. VREF+ - 1LSB V 220 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 380 A With no load, middle code (0x800) on the inputs 480 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs 0.5 LSB Given for the DAC in 10-bit configuration. 2 LSB Given for the DAC in 12-bit configuration. 1 LSB Given for the DAC in 10-bit configuration. 4 LSB Given for the DAC in 12-bit configuration. Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 56. Symbol Offset(2) Gain error(2) Electrical characteristics DAC characteristics (continued) Parameter Min Unit 10 mV Given for the DAC in 12-bit configuration 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V 0.5 % Given for the DAC in 12bit configuration 4 s CLOAD 50 pF, RLOAD 5 k 1 MS/s CLOAD 50 pF, RLOAD 5 k 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. -67 -40 dB No RLOAD, CLOAD = 50 pF Gain error 3 Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Wakeup time from off state tWAKEUP(2) (Setting the ENx bit in the DAC Control register) PSRR+ (1) Max Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Settling time (full scale: for a 10-bit input code transition (2) between the lowest and the tSETTLING highest input codes when DAC_OUT reaches final value 1LSB Update rate(2) Typ Power supply rejection ratio (to VDDA) (static DC measurement Comments 1. Guaranteed by design, not tested in production. 2. Guaranteed by characterization, not tested in production. Figure 38. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. Doc ID 15274 Rev 6 79/104 Electrical characteristics 5.3.19 STM32F105xx, STM32F107xx Temperature sensor characteristics Table 57. TS characteristics Symbol TL(1) Parameter tSTART(2) TS_temp(3)(2) Typ Max Unit 1 2 C 4.0 4.3 4.6 mV/C 1.34 1.43 1.52 V 10 s 17.1 s VSENSE linearity with temperature Avg_Slope(1) Average slope V25(1) Min Voltage at 25 C Startup time 4 ADC sampling time when reading the temperature 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 80/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 15274 Rev 6 81/104 Package characteristics STM32F105xx, STM32F107xx Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline Table 58. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) mm Dim. Min Typ A A1 Max Min 1.700 Max 0.0026 0.270 0.0004 A2 1.085 0.0017 A3 0.30 0.0005 A4 0.80 0.0012 b 0.45 0.50 0.55 0.0007 0.0008 0.0009 D 9.85 10.00 10.15 0.0153 0.0155 0.0157 D1 E 7.20 9.85 10.00 0.0111 10.15 0.0153 0.0155 E1 7.20 0.0111 e 0.80 0.0012 F 1.40 0.0022 ddd 0.12 0.0002 eee 0.15 0.0002 fff 0.08 0.0001 N (number of balls) 100 1. Values in inches are converted from mm and rounded to 4 decimal digits. 82/104 Typ Doc ID 15274 Rev 6 0.0157 STM32F105xx, STM32F107xx Package characteristics Figure 40. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print Dpad Dsm Doc ID 15274 Rev 6 83/104 Package characteristics STM32F105xx, STM32F107xx Figure 42. Recommended footprint(1)(2) Figure 41. LQFP100, 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE k 75 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 26 Pin 1 1 identification 25 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 59. LQPF100 - 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ Min 1.60 A1 0.05 0.15 Max 0.063 0.002 0.0059 A2 1.40 1.35 1.45 0.0551 0.0531 0.0571 b 0.22 0.17 0.27 0.0087 0.0067 0.0106 0.09 0.20 0.0035 0.0079 c D 16.00 15.80 16.20 0.6299 0.622 0.6378 D1 14.00 13.80 14.20 0.5512 0.5433 0.5591 D3 12.00 E 16.00 15.80 16.20 0.6299 0.622 0.6378 E1 14.00 13.80 14.20 0.5512 0.5433 0.5591 E3 12.00 e 0.50 L 0.60 0.0177 0.0295 L1 1.00 k 3.5 0 7 ccc 0.4724 0.4724 0.0197 0.45 0.75 0.0394 0 7 0.08 3.5 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 84/104 0.0236 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Package characteristics Figure 44. Recommended footprint(1)(2) Figure 43. LQFP64 - 64 pin low-profile quad flat package outline(1) A 48 33 A2 0.3 A1 E 49 b E1 12.7 32 0.5 10.3 e 10.3 64 17 1.2 1 D1 16 c 7.8 L1 D L 12.7 ai14909 ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 60. LQFP64 - 64 pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15274 Rev 6 85/104 Package characteristics 6.2 STM32F105xx, STM32F107xx Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 35. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 61. Package thermal characteristics Symbol JA JA 6.2.1 Parameter Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch Value Unit 46 C/W Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.8 mm pitch 40 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 86/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx 6.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 62: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 61 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 82 C + (46 C/W x 447 mW) = 82 C + 20.6 C = 102.6 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 62: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 15274 Rev 6 87/104 Package characteristics STM32F105xx, STM32F107xx Using the values obtained in Table 61 TJmax is calculated as follows: - For LQFP100, 46 C/W TJmax = 115 C + (46 C/W x 134 mW) = 115 C + 6.2 C = 121.2 C This is within the range of the suffix 7 version parts (-40 < TJ < 125 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 62: Ordering information scheme). Figure 45. LQFP100 PD max vs. TA 700 PD (mW) 600 500 Suffix 6 400 Suffix 7 300 200 100 0 65 75 85 95 105 115 TA (C) 88/104 Doc ID 15274 Rev 6 125 135 STM32F105xx, STM32F107xx Part numbering 7 Part numbering Table 62. Ordering information scheme Example: STM32 F 105 R C T 6 V xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 105 = connectivity, USB OTG FS 107= connectivity, USB OTG FS & Ethernet Pin count R = 64 pins V = 100 pins Flash memory size 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory Package H = BGA T = LQFP Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Software option Internal code or Blank Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Doc ID 15274 Rev 6 89/104 Application block diagrams Appendix A A.1 STM32F105xx, STM32F107xx Application block diagrams USB OTG FS interface solutions Figure 46. USB OTG FS device mode STM32F105xx/STM32F107xx OTG PHY USB OTG Full-speed core DM HNP V BUS VSS ID USB Micro-B connector DP USB Full-speed transceiver To host DP DM VBUS VSS SRP VDD 5 V to VDD Regulator(1) ai15653b 1. Use a regulator if you want to build a bus-powered device. 90/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Application block diagrams Figure 47. Host connection STM32F105xx/STM32F107xx OTG PHY USB OTG Full-speed core DM HNP V BUS VSS ID USB Std-A connector DP USB full-speed/ low-speed transceiver VDD(2) SRP GPIO GPIO + IRQ Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN ai15654b 1. STMPS2141STR needed only if the application has to support bus-powered devices. Doc ID 15274 Rev 6 91/104 Application block diagrams STM32F105xx, STM32F107xx Figure 48. OTG connection (any protocol) STM32F105xx/STM32F107xx OTG PHY DM ID USB OTG Full-speed core HNP V BUS VSS ID USB Micro-AB connector DP USB full-speed/ low-speed transceiver VDD SRP GPIO GPIO + IRQ Current-limited power distribution 5 V switch OVRCR STMPS2141STR(1) flag EN ai15655b 1. STMPS2141STR needed only if the application has to support bus-powered devices. A.2 Ethernet interface solutions Figure 49. MII mode using a 25 MHz crystal STM32F107xx MCU Ethernet MAC 10/100 HCLK(1) IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL Ethernet PHY 10/100 MII = 15 pins MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII + MDC = 17 pins MDIO MDC PPS_OUT(2) XTAL 25 MHz OSC HCLK PLL PHY_CLK 25 MHz XT1 ai15656 1. HCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP, optional signal. 92/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Application block diagrams Figure 50. RMII with a 50 MHz oscillator Ethernet PHY 10/100 STM32F107xx MCU Ethernet MAC 10/100 RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII = 7 pins RMII + MDC = 9 pins RMII_REF_CLK IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator MDIO MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz OSC 50 MHz PLL HCLK PHY_CLK 50 MHz XT1 50 MHz ai15657 1. HCLK must be greater than 25 MHz. Figure 51. RMII with a 25 MHz crystal and PHY with PLL STM32F107xx MCU Ethernet MAC 10/100 Ethernet PHY 10/100 RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] HCLK(1) RMII_CRX_DV RMII_REF_CLK IEEE1588 PTP Timer input trigger Timestamp TIM2 comparator RMII = 7 pins REF_CLK MDIO RMII + MDC = 9 pins MDC /2 or /20 2.5 or 25 MHz synchronous 50 MHz XTAL 25 MHz OSC PLL PLL HCLK PHY_CLK 25 MHz XT1 ai15658 1. HCLK must be greater than 25 MHz. Doc ID 15274 Rev 6 93/104 Application block diagrams STM32F105xx, STM32F107xx Figure 52. RMII with a 25 MHz crystal STM32F107xx MCU RMII_TX_EN Ethernet MAC 10/100 RMII_TXD[1:0] RMII_RXD[1:0] HCLK RMII_CRX_DV IEEE1588 PTP 50 MHz Timer input trigger Time stamp TIM2 comparator XTAL 25 MHz Ethernet PHY 10/100 RMII_REF_CLK RMII = 7 pins 50 MHz MDIO RMII + MDC = 9 pins MDC 50 MHz OSC PLLS XT1/XT2 NS DP83848(1) ai15659b 1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU. 94/104 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx A.3 Application block diagrams Complete audio player solutions Two solutions are offered, illustrated in Figure 53 and Figure 54. Figure 53 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I2S accuracy on the master clock (0.5% error maximum, see the Serial peripheral interface section in the reference manual for details). Figure 53. Complete audio player solution 1 STM32F105/STM32F107 XTAL 14.7456 MHz Cortex-M3 core 72 MHz SPI LCD touch screen GPIO Control buttons Program memory OTG (host mode) + PHY USB Mass-storage device File System DAC + Audio ampli I2S Audio CODEC User application MMC/ SDCard SPI ai15660 Figure 54 shows storage media to audio Codec/amplifier streaming with SOF synchronization of input/output audio streaming using a hardware Codec. Figure 54. Complete audio player solution 2 STM32F105/STM32F107 XTAL 14.7456 MHz Cortex-M3 core 72 MHz SPI LCD touch screen GPIO Control buttons Program memory USB Mass-storage device SOF MMC/ SDCard OTG + PHY File System I2S User application SPI Audio CODEC Audio ampli SOF synchronization of input/output audio streaming ai15661 Doc ID 15274 Rev 6 95/104 Application block diagrams A.4 STM32F105xx, STM32F107xx USB OTG FS interface + Ethernet/I2S interface solutions With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 55 illustrate the solution. Figure 55. USB OTG FS + Ethernet solution OSC STM32F107 MCU 25 MHz XTAL Div by 5 PLL2MUL x8 SYSCLK Up to 72 MHz PLLVCO (2 xPLLCLK Div by 5 OTG Div by 3 PLLMUL x9 48 MHz USB PHY Sel Ethernet PHY PLL3MUL x10 MCO I2S Up to 50 MHz 2% accuracy Sel With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I2S (Audio) interfaces. Figure 56 illustrate the solution. Figure 56. USB OTG FS + I2S (Audio) solution STM32F105 /STM32F107MCU OSC 14.7456 MHz XTAL Div by 4 PLL2MUL x8 Up to 71.88 MHz SYSCLK PLLVCO (2 xPLLCLK Div by 4 PLLMUL x6.5 Sel Ethernet PHY MCO PLL3MUL x20 Div by 3 OTG 47.9232 MHz USB PHY 0.16% accuracy PLL3VCO (2 xPLL3CLK MCLK I2S Up to 147.456 MHz Less than 0.5% accuracy on MCLK and SCLK 96/104 Doc ID 15274 Rev 6 SCLK STM32F105xx, STM32F107xx Table 63. Application block diagrams PLL configurations Crystal value in PREDIV2 PLL2MUL MHz (XT1) Application PLLSRC PREDIV1 PLLMUL USB I2Sn MCO (main prescaler clock PLL3MUL clock (PLLVCO output) input output) Ethernet only 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 NA PLL3ON x10 NA XT1 (MII) PLL3 (RMII) Ethernet + OTG 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 /3 PLL3ON x10 NA XT1 (MII) PLL3 (RMII) Ethernet + OTG + basic audio 25 /5 PLL2ON x8 PLL2 /5 PLLON x9 /3 PLL3ON x10 PLL XT1 (MII) PLL3 (RMII) Ethernet + OTG + Audio class 14.7456 I2S(1) /4 PLL2ON x12 PLL2 /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA ETH PHY must use its own crystal OTG only 8 NA PLL2OFF XT1 /1 PLLON x9 /3 PLL3OFF NA NA OTG + basic audio 8 NA PLL2OFF XT1 /1 PLLON x9 /3 PLL3OFF PLL NA OTG + Audio class I2S(1) 14.7456 /4 PLL2ON x12 PLL2 /4 PLLON x6.5 /3 PLL3ON x20 PLL3 VCO Out NA Audio class I2S 14.7456 only(1) /4 PLL2ON x12 PLL2 /4 PLLON x6.5 NA PLL3ON x20 PLL3 VCO out NA 1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz. Table 64 give the IDD run mode values that correspond to the conditions specified in Table 63. Doc ID 15274 Rev 6 97/104 Application block diagrams Table 64. Symbol IDD STM32F105xx, STM32F107xx Applicative current consumption in Run mode, code with data processing running from Flash parameter Conditions(1) Max(2) 85 C 105 C External clock, all peripherals enabled except ethernet, HSE = 8 MHz, fHCLK = 72 MHz, no MCO 57 63 64 External clock, all peripherals enabled except ethernet, HSE = 14.74 MHz, fHCLK = 72 MHz, no MCO 60.5 67 68 External clock, all peripherals enabled except OTG, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 25 MHz 53 60.7 61 60.5 65.5 66 External clock, all peripherals enabled, HSE = 25 MHz, fHCLK = 72 MHz, MCO = 50 MHz 64 69.7 70 External clock, all peripherals enabled, HSE = 50 MHz(3), fHCLK = 72 MHz, no MCO 62.5 67.5 68 External clock, only OTG enabled, HSE = 8 MHz, fHCLK = 48 MHz, no MCO 26.7 None None External clock, only ethernet enabled, HSE = 25 MHz, fHCLK = 25 MHz, MCO = 25 MHz 14.3 None None External clock, all peripherals enabled, Supply current HSE = 25 MHz, f HCLK = 72 MHz, MCO in run mode = 25 MHz 1. VDD = 3.3 V. 2. Based on characterization, not tested in production. 3. External oscillator. 98/104 Typ(2) Doc ID 15274 Rev 6 Unit mA STM32F105xx, STM32F107xx Revision history Revision history Table 65. Document revision history Date Revision 18-Dec-2008 1 Initial release. 2 I/O information clarified on page 1. Figure 4: STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view corrected. Section 2.3.8: Boot modes updated. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Pin definitions. Consumption values modified in Section 5.3.5: Supply current characteristics. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Table 27: PLL characteristics modified and Table 28: PLL2 and PLL3 characteristics added. 20-Feb-2009 Changes Doc ID 15274 Rev 6 99/104 Revision history STM32F105xx, STM32F107xx Table 65. Document revision history (continued) Date 19-Jun-2009 100/104 Revision Changes 3 Section 2.3.8: Boot modes and Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support updated. Section 2.3.24: Remap capability added. Figure 1: STM32F105xx and STM32F107xx connectivity line block diagram and Figure 5: Memory map updated. In Table 5: Pin definitions: - I2S3_WS, I2S3_CK and I2S3_SD default alternate functions added - small changes in signal names - Note 6 modified - ETH_MII_PPS_OUT and ETH_RMII_PPS_OUT replaced by ETH_PPS_OUT - ETH_MII_MDIO and ETH_RMII_MDIO replaced by ETH_MDIO - ETH_MII_MDC and ETH_RMII_MDC replaced by ETH_MDC Figures: Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled and Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled removed. Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM are to be determined. Figure 12 and Figure 13 show typical curves. PLL1 renamed to PLL. IDD supply current in Stop mode modified in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 11: Typical current consumption in Stop mode with regulator in Run mode versus temperature at different VDD values, Figure 13: Typical current consumption in Standby mode versus temperature at different VDD values and Figure 13: Typical current consumption in Standby mode versus temperature at different VDD values updated. Table 17: Typical current consumption in Run mode, code with data processing running from Flash, Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM and Table 19: Peripheral current consumption updated. fHSE_ext modified in Table 20: High-speed external user clock characteristics. Min PLL input clock (fPLL_IN), fPLL_OUT min and fPLL_VCO min modified in Table 27: PLL characteristics. ACCHSI max values modified in Table 24: HSI oscillator characteristics. Table 31: EMS characteristics and Table 32: EMI characteristics updated. Table 43: SPI characteristics updated. Modified: Figure 28: I2S slave timing diagram (Philips protocol)(1), Figure 29: I2S master timing diagram (Philips protocol)(1) and Figure 31: Ethernet SMI timing diagram. BGA100 package removed. Section 6.2: Thermal characteristics added. Small text changes. Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Table 65. Revision history Document revision history (continued) Date 14-Sep-2009 Revision Changes 4 Document status promoted from Preliminary data to full datasheet. Number of DACs corrected in Table 3: STM32F105xx and STM32F107xx family versus STM32F103xx family. Note 5 added in Table 5: Pin definitions. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Values added to Table 13: Maximum current consumption in Run mode, code with data processing running from Flash, Table 14: Maximum current consumption in Run mode, code with data processing running from RAM and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 10: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. Values modified in Table 17: Typical current consumption in Run mode, code with data processing running from Flash and Table 18: Typical current consumption in Sleep mode, code running from Flash or RAM. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CL1 and CL2 replaced by C in Table 22: HSE 3-25 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Note 1 modified below Figure 16: Typical application with an 8 MHz crystal. Conditions removed from Table 26: Low-power mode wakeup timings. Standards modified in Section 5.3.10: EMC characteristics on page 52, conditions modified in Table 31: EMS characteristics. Jitter maximum values added to Table 27: PLL characteristics and Table 28: PLL2 and PLL3 characteristics. RPU and RPD modified in Table 36: I/O static characteristics. Condition added for VNF(NRST) parameter in Table 39: NRST pin characteristics. Note removed and RPD, RPU values added in Table 46: USB OTG FS DC electrical characteristics. Table 48: Ethernet DC electrical characteristics added. Parameter values added to Table 49: Dynamic characteristics: Ethernet MAC signals for SMI, Table 50: Dynamic characteristics: Ethernet MAC signals for RMII and Table 51: Dynamic characteristics: Ethernet MAC signals for MII. CADC and RAIN parameters modified in Table 52: ADC characteristics. RAIN max values modified in Table 53: RAIN max for fADC = 14 MHz. Table 56: DAC characteristics modified. Figure 38: 12-bit buffered /non-buffered DAC added. Table 64: Applicative current consumption in Run mode, code with data processing running from Flash added. Small text changes. Doc ID 15274 Rev 6 101/104 Revision history STM32F105xx, STM32F107xx Table 65. Document revision history (continued) Date 11-May-2010 01-Aug-2011 102/104 Revision Changes 5 Added BGA package. Table 5: Pin definitions: ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for PD9 and PD10, respectively. Note added to ETH_MII_RX_DV, ETH_MII_RXD0, ETH_MII_RXD1, ETH_MII_RXD2 and ETH_MII_RXD3 Updated Table 36: I/O static characteristics on page 55 Added Figure 18: Standard I/O input characteristics - CMOS port to Figure 21: 5 V tolerant I/O input characteristics - TTL port Updated Table 43: SPI characteristics on page 65. Updated Table 44: I2S characteristics on page 68. Updated Table 48: Ethernet DC electrical characteristics on page 71. Updated Table 49: Dynamic characteristics: Ethernet MAC signals for SMI on page 71. Updated Table 50: Dynamic characteristics: Ethernet MAC signals for RMII on page 72 Updated Figure 55: USB OTG FS + Ethernet solution on page 96. Updated Figure 56: USB OTG FS + I2S (Audio) solution on page 96 6 Changed SRAM size to 64 KB on all parts. Updated PD0 and PD1 description in Table 5: Pin definitions on page 26 Updated footnotes below Table 6: Voltage characteristics on page 34 and Table 7: Current characteristics on page 34 Updated tw min in Table 20: High-speed external user clock characteristics on page 45 Updated startup time in Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 48 Added Section 5.3.12: I/O current injection characteristics on page 55 Updated Table 36: I/O static characteristics on page 55 Add Interna code V to Table 62: Ordering information scheme on page 89 Doc ID 15274 Rev 6 STM32F105xx, STM32F107xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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