VIPER53ESPTR-E - STMICROELECTRONICS

January 2006 DocRev1 1/31

VIPer53EDIP - E

VIPer53ESP - E

OFF-line Primary Switc h

Features

■Switching frequency up to 300kHz

■Curren t mode control with adjustable limitation

■Soft start and shut-dow n control

■Autom atic burst mode in standby condition

(“Blue Angel“ compliant )

■Underv oltage lockout with Hysteresis

■Integrated start-up current source

■Ov er-temperature protection

■Ov erload and short-circuit control

■Overv oltage pr otection

■In compliance with the 2002 /95/EC Europ ean

Directive

Description

The VIPer53E combines an enhanced current

mode PWM controller with a high voltage

MDMesh Power MOSFET in the same package.

Typical applications cover offline power supplies

with a secondary power capability ranging up to

30W in wide rang e input voltage, or 50W in single

European voltage range and DIP-8 package and

40W in wide rang e input voltage, or 65W in single

European voltage range and PowerSO-10

package, with the following benefi t s:

– Ov erload and short-circuit events

controll ed by feedback mon itoring and

delayed dev ice reset;

– Efficient standby mode by enhanced pulse

skipping.

– Integrat ed start-up cu rre nt source is

disabled during normal operation to reduce

the input power.

DIP-8PowerSO-10

www.st.com

Block diagram

OSCILLATOR

150/400ns

BLANKING

OVERTEMP.

DETECTOR

8.4/

11.5V

VDD

OSC DRAIN

COMP SOURCE

PWM

LATCH

ON/OFF

BLANKING TIME

SELECTION

PWM

COMPARATOR

CURRENT

AMPLIFIER

R3 R4 R5

OVERLOAD

COMPARATOR

18V

125k

0.5V

STANDBY

COMPARATOR

OVERVOLTAGE

COMPARATOR

UVLO

COMPARATOR H

COMP

0.5V

4.4V

4.5V

TOVL

Vcc

COMP

Contents VIPer53EDIP - E / VIPer53ESP - E

2/31 DocRev1

Contents

1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Rectangular U-I Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Secondary Feedback Configuration Example . . . . . . . . . . . . . . . . . . . . 9

6 Current Mode Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8 High Voltage Start-up Current S ource . . . . . . . . . . . . . . . . . . . . . . . . . . 13

9 Short-Circuit and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . 15

10 Regulation Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Special Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

12 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

13 Operation pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

VIPer53EDIP - E / VIPer53ESP - E Electrical data

DocRev1 3/31

1 Electrical data

1.1 Maximum rating

Stres sing the device above the rating listed in the “Abs ol ute Maxim um Ratings” table may

cause permanent damage to the device. These ar e stress ratings only and operation of the

device at these or any o ther condi tions above those indicated in the Operat ing sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditi ons for

extended periods may aff ect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

1.2 Thermal data

Table 1. Absolute maxi mum rating

Symbol Parameter Value Unit

VDS Conti nuous Drain Source Voltage (TJ= 25 ... 125°C) (1) -0.3 ... 620 V

IDConti nuous Drain Current Inte rnally limi ted A

VDD S upply Voltage 0 ... 19 V

VOSC OSC Input Voltage Range 0 ... V DD V

ICOMP

ITOVL COMP and T O VL Input Curr ent Range (1)

1. In order to improve the ruggedness of the device versus eventual drain overvoltages, a resistance of 1kΩ

should be inserted in series with the TOVL pin.\

-2 .. . 2 m A

VESD

E lectrostatic Dis charge:

Machine M odel (R = 0Ω; C = 200pF)

Charged Device Model 200

1.5 V

TJJunction Operating Temper ature Internally li m ited °C

TC Case O perating Temper ature -40 to 150 °C

TSTG Stor age Temperature -55 to 150 °C

Tabl e 2. Thermal data

Symbol Parameter PowerSO-10 (1)

1. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected

to the DRAIN pin.

DIP-8 (2)

2. When mounted on a standard single-sided FR4 board with 50mm² of Cu (at least 35 mm thick) connected

to the devic e ta b.

Unit

RthJC Thermal Resistance Junction-case Max 2 20 °C/W

RthJA Thermal Resistance Ambient-case Max 60 80 °C/W

Electri cal character istics VIPer53E DIP - E / VIP er53 ESP - E

4/31 DocRev1

2 Electrical characteristics

TJ = 25°C, VDD = 13V, unless otherwise specified

Tabl e 3. Power sectio n

Symbol Parameter Test conditions Min. Typ. Max. Unit

BVDSS Drain-Source

Voltage ID = 1mA; VCOMP = 0V 620 V

IDSS Off Stat e Dr ain

Current VDS = 500V ; VCOMP = 0V; Tj = 125°C 150 µA

RDS(on) Static Drain-Source

On State Resis tance

ID = 1A; VCOMP = 4.5V; VTOVL = 0V

TJ = 25°C

TJ = 100°C 0.9 1

1.7

Ω

tfv Fall Time ID = 0.2A; VIN = 300V (1)

1. On clamped inductive load

100 ns

trv Rise T i me ID = 1A; VIN = 300V (1) 50 ns

Coss Drain Capacitance VDS = 25V 170 pF

CEon Effect ive Output

Capacitance 200V < V DSon < 400V (2)

2. This parameter can be used to compute the energy dissipated at turn on Eton according to the in itial drain

to so urc e volt ag e V DSon and the following formula:

60 pF

Tabl e 4. Oscillator Sectio n

Symbol Par ameter Test Conditions Min. Typ. Max . Unit

FOSC1 Oscillator Frequency

Ini tia l A c curacy RT = 8kΩ; CT = 2.2nF

Figure 15 on page 23 95 100 105 kHz

FOSC2 Oscillator Frequency

Total Variation

RT = 8kΩ; CT = 2.2nF

Figure 17 on page 24

VDD = VDDon ... VDDovp;

TJ = 0 ... 100°C

93 100 107 kHz

VOSChi Oscillator Peak

Voltage 9V

VOSClo Osc ill at o r Valley

Voltage 4V

Eton 1

---CEon 3002VDSon

300

----------------

⎝⎠

⎛⎞

1.5

⋅⋅⋅=

VIPe r53EDIP - E / VIPer53ESP - E Elec trica l characteristics

DocRev1 5/31

Tabl e 5. Supply Section

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDSstart Drain Voltage Starting

Threshold VDD = 5 V; IDD = 0mA 34 50 V

IDDch1 Startup Charging Current VDD = 0 ... 5V; VDS = 100V

Figure 9 on page 22 -12 mA

IDDch2 Startup Charging Current VDD = 1 0V; VDS = 100VFigure 9. -2 mA

IDDchoff Startup Charging Current

in Ther ma l Shut down VDD = 5 V; VDS = 100VFigure 11.

TJ > TSD - THYST 0mA

IDD0 Operating Supply Cur rent

No t S witc h in g Fsw = 0kHz; VCOMP = 0V 811mA

IDD1 Operating Supply Cur rent

Switching Fsw=100kHz 9mA

VDDoff VDD Undervoltage

Shutdown Threshold Figure 9 on page 22 7.5 8.4 9.3 V

VDDon VDD Startup Threshold Figure 9. 10.2 11.5 12.8 V

VDDhyst VDD Threshold

Hysteresis Figure 9. 2.6 3.1 V

VDDovp VDD Overvoltage

Shutdown Threshold Figure 9. 17 18 19 V

Table 6. Pwm Comparator Section

S ymbol Parameter Test Conditions Min. Typ. Max. Uni t

HCOMP ∆VCOMP / ∆IDPEAK VCOMP = 1 ... 4 V Figure 14.

dID/dt = 0 1.7 2 2.3 V/A

VCOMPos VCOMP Offset dID/dt = 0 Fig ure 14. 0.5 V

IDlim Peak Drain Curren t

Limitation

ICOMP = 0mA; VTOVL = 0V

Figure 14.

dID/dt = 0 1.7 2 2.3 A

IDmax Drain Current

Capability VCOMP = VCOMPovl; VTOVL = 0V

dID/dt = 0 1.6 1.9 2.3 A

tdCurrent Sense Delay

to Turn-Off ID = 1A 250 ns

VCOMPbl VCOMP Blanking Time

Change Threshold F igure 10 on page 22 1V

tb1 Blanking Time VCOMP < VCOMPBLFigure 10. 300 400 500 ns

tb2 Blanking Time VCOMP > VCOMPBLFigure 10. 100 150 200 ns

tONmin1 Min imum On Ti me VCOMP < VCOMPBL 450 600 750 ns

Electri cal character istics VIPer53E DIP - E / VIP er53 ESP - E

6/31 DocRev1

Tabl e 8. Over temperatu re Protection Section

Table 9. Typical Output Power Capability

tONmin2 Min imum On Ti me VCOMP > VCOMPBL 250 350 450 ns

VCOMPoff VCOMP Shutdown

Threshold Figure 13 on page 23 0.5 V

VCOMPhi VCOMP High Level ICOMP=0mA (1) 4.5 V

ICOMP COMP Pull Up Current VCOMP= 2.5V 0.6 mA

1. In order to ensure a correct stability of the internal current source, a 10nF capacitor (minimum value 8nF)

should always be present on the COMP pin.

Tabl e 7. Overload Protec tion Sect ion

Sym bol Parameter Test Conditions Min. Typ. Max. Unit

VCOMPovl VCOMP Ov erl oad

Threshold ITOVL = 0mA Figure 7 on page 2 0

(1)

1. VCOMPovl is always lower than VCOMPhi

4.35 V

VDIFFovl VCOMPhi to VCOMPovl

Voltage Differenc e

VDD = VDDoff ... VDDreg;

ITOVL= 0 mA

Figure 7. (1) 50 150 250 mV

VOVLth VTOVL Overload

Threshold Figure 7. 4V

tOVL Overload Delay COVL = 100nF Figure 7. 8ms

Symbol Parameter Test Conditions Min. Typ. Max. Unit

TSD Thermal Shutdown

Temperature Figu re 11 on page 22 140 160 °C

THYST Thermal Shutdown

Hysteresis Figure 11 on page 22 40 °C

Type European

(195 - 265Vac) US / Wide range

(85 - 265Vac)

VIPer53EDIP-E 50W 30W

VIPer53ESP-E 65W 40W

Table 6. Pwm Comparator Section

S ymbol Parameter Test Conditions Min. Typ. Max. Uni t

VIPer53EDIP - E / VIPer53ESP - E Pin connections and function

DocRev1 7/31

3 Pin connections and function

Figure 1. Pin connection (top view)

Figure 2. Current and volta ge conven tions

Table 10 . Pin func ti on

Pin Name Pin Function

VDD

Power suppl y of the control circuit s. Al so provides the char ging current of the exter nal

capacitor dur ing start-up.

The functions of this pin are managed by fo ur threshold voltages:

- VDDon: Volt age value at whi ch the device st arts swi tching (Typically 11.5 V).

- VDDoff : Voltage value at whic h the device stops switchi ng (Typic ally 8.4 V).

- VDDovp: Trig geri ng voltage of the overvoltage pr otection (Trimm ed to 18 V).

S OURCE Power MOSFET source and cir cuit ground refer ence.

DRAIN Power MOSFET drain. Also used by the internal high voltage current source during

the start-up phase, to charge t he external VDD capacitor.

COMP

Allows the setting of the dynamic characteristi c of the converter through an external

passive network. The useful voltage range extend s fr om 0.5V to 4.5V. The Power

MOSFET is always off bel ow 0.5V, and the overload protection is triggered if the

volt age ex ceed s 4.35V. This act ion is del ayed by th e timing cap acitor connect ed to the

TOVL pin.

TOVL Allows the connection of an external capacit or f or delaying t he overload protection,

which is triggered by a voltage on the COMP pin hig her than 4.4V.

OSC Allows the setting of the swi tching frequency through an external Rt-Ct network .

OURCE

TOVLCOMP

VDD

DRA

OURCE

OSC

VDD

OVL

OSC

COMP

SOURC

DRAIN

DIP-8 PowerSO-10

15V

VDD

OSC

DRAIN

SOURCECOMPTOVL

OSC

TOVL

COMP

Rect angular U-I Output char acteristics VIPer53E DIP - E / VIP er53 ESP - E

8/31 DocRev1

4 Rect angular U-I Output character istics

Fi gur e 3 . Off Line P ower S upp l y With Optocoupler Feedback

R4 D3

D4 C8

C10

AC IN

DC O U

C11

VDD

OSC

DRAIN

SOURCECOMP TOV L

CONTROL

C12

10nF

VIPe r53EDIP - E / VIPer53ESP - E Secondary Feedb ack Conf iguration Examp le

DocRev1 9/31

5 Seco ndary Fee dback Configuration Exam ple

The secondary feedback is implemented through an optocoupler driven by a programmable

zener diode (TL431 type) as shown in Figure 3 on page 8

The optocoupler is connected in parallel with the compens ation network on the COMP pin

which delivers a constan t biasing current of 0.6mA to the o ptotransist or. This current does

not depend on the compensation voltage, and so it does not depend on the output load

either. Consequent ly, the gain of the optocoupler ensures a constant biasing of the TL431

device (U3), which is respon sible for secondary regulation. If the optocouple r gain is

sufficien tly low, no additional comp onents are required to a minimum current biasing of U3.

Additionally, the low biasing current protects th e optocoup ler from premature failure.

The constant current b iasing can be used to simplify the secondary circuit: in stead of a

TL431, a simple zener and resistance network in series with the optocoupler diode c an

insure a good secondary regulation. Current flowing in this branch remains constant just as

it does by usi ng a TL431, so typical load regulation of 1% can be achieved from zero to full

output current with this simple configuration.

Since the dynamic characteristics of the converter are set on the seconda ry side through

components associated to U3, the compensation network has only a role of gai n

st abilization for the optocoupler, and it s value can be freely chosen. R5 can be set to a fixed

value of 2.2kΩ, of fering the possibil ity of using C7 as a soft start capacitor: When starting up

the converter, the VIPer53E dev ice delivers a constant current of 0.6m A on the COMP pin,

creating a constant vol tage of 1.3V in R5 and a rising slope across C7. This voltage shape,

together with the operating range of 0.5V to 4.5V provides a soft startup of the converter.

The rising speed of the output voltag e can be set through the value of C7. T he C4 and C6

values must be adjusted accordingly in order to ensure a correct startup.

Current Mode Topology VIPer53EDIP - E / VIPer53ESP - E

10/31 DocRev1

6 Current Mode Topology

The VIPer53E implements the conventiona l current mode control metho d for re gulating the

output voltage. This kind of feedback includes two nested regulation loops:

The inner loop controls the peak primary current cycle by cycle. When the Power MOSFET

output transist or is on, the induct or current (primary side of the transformer) is monitored

with a SenseFET technique and converted into a voltage. When VS reaches VCOMP, the

power switch is turned off. This structure is com pletely integrated as shown on the Block

Diagram of Figure on page 1, with the current amplifier, the PWM comparator, the blanking

time function and the PWM latch. The following formula giv es the peak current in the Power

MOSFE T accord ing to the compensa tion voltage:

The outer loop defi nes the level at which the inner loop regulates peak current in the power

switch. For this purpose, VCOMP is driven by the feedback network (TL431 through an

optocoupler in secondary feedb ack configuration, see F igure 3 on page 8) and is sets

ac co rdingly t h e peak drain current fo r each switch i n g cycle.

As the in ner loop regulates the peak primary current in the primary side of the transformer,

all input vo ltage changes are compe nsated for before impacting the output voltag e. This

results in an improved line regulation, instantaneous correction to line changes, and better

stability for the voltage regulation loop.

Current mode topology also provides a good converter start-up control. The compensation

voltage can b e controlled to increase slowly during the start-up phase, so th e peak primary

current will f ollow this soft voltage slope to provide a smooth output voltage rise, without any

overshoot. The simpler voltage mode structure whic h only controls the duty cycle, leads

generally to h igh current at start-u p with th e risk of tra nsformer saturation.

An integrated blanking filter inhib its the PWM comparator output for a short time after the

integrated Power MOSFET is switched on. This function prevents anomalous or premature

termination of the switching pulse in the case of current spikes caused by primary side

transformer capacitance or seconda ry side rectifier reverse recovery time when working in

continuous mode.

IDpeak VCOMP VCOMPos

–

HCOMP

--------------------------------------------------=

VIPer53EDIP - E / VIPer53ESP - E Standby Mode

DocRev1 11/31

7 Standby Mode

The device offers a special feature to address the low l oad condition. The corres pondin g

function described hereafter consist s of reducing the s witchi ng frequency by going into burst

mode, with the following benef its:

– It red uc es the switching losses, thus providing low consumption on the mains lines.

The device is compliant with “Blue An gel” and other similar standards, req uiring less

than 0.5 W of inpu t power when in standby.

– It allows the regulation of the output v oltage, even if the load corresponds to a duty

cycle that the device is not able to generate becau se of the internal blanking time,

and associated minimum turn on.

For this purpose, a comparator monitores the COMP pin voltage, and maintains the PWM

latch and the Power MOSFET in the Off state as long as VCOMP remains below 0.5V (See

Block Diagram on page 2). If the output load requires a duty cycl e below the one defined by

the minimum turn on of the device, the VCOMP net decreases it s volt age until it reaches this

0.5V threshold (VCOMPoff). The Power MOSFET can be completely Off for some cycles, and

resumes normal operation as soon as VCOMP is higher than 0.5V. The out put voltage is

regulated in burst mode. The corresponding ripple is not higher than the nominal one at full

load.

In addition, th e minimum turn on time which defines the frontier between normal operation

and burst mode changes according to VCOMP value. Below 1.0V (VCOMPbl), the blanking

time increases to 400ns, whereas for higher voltages, it is 150ns Figure 10 on page 22 The

minimum turn on times resulting from these v alues ar e respectively 600 ns and 350 ns,

when taking into accou nt internal propagation time. This brutal change induces an

hysteresis between normal operation and burst mode as shown on Figure 10 on page 22

When the output power decreases, th e syste m reaches point 2 where VCOMP equals

VCOMPbl. The minimum turn-on time passes immediately from 350ns to 600ns, exceeding

the effec tive turn-on time that should be needed at this output power level. Therefore the

regulation loop will quickly d rive VCOMP to VCOMPoff (Point 3) in order to pass into burst

mode and to control the output voltage . The correspondi ng hysteresis can be seen on the

switching frequency which passes from FSWnom which is t he normal switching frequency set

by the components connected to the OSC pin and to FSW stby. Note: This frequenc y is

actually an equivalent number of switching pulses per second, rather than a fi xed switching

frequency since the device is working in burst m ode.

As long as t he power remains below PRST t he output of the regulation l oop remains stuck at

VCOMPsd and the converter works in burst mode. Its “de nsity” increases (i.e. the num ber of

missing cycles d ecreases) as the power appro aches P RST and finally resumes normal

operation at point 1. The hysteresis cannot be seen on the switching frequency , but it can be

seen in the sudden surge of the COMP pin volt age from point 3 to point 1 at that power

level.

The power points value PRST and PSTBY are defined by the following formulas:

PRST 1

---FSWnom

•tb1td+()•2V2

•IN 1

-------•=

PSTBY 1

---FSWnom

•Ip2VCOMPbl

()•Lp•=

Standby Mode VIPer53EDIP - E / VIPer53ESP - E

12/31 DocRev1

Where Ip(VCOMPbl2) is the peak Power MOSFE T current corresponding to a compensation

voltage of VCOMPbl (1V). Note: The power point PSTBY where the converter is going into

burst mode does not depend on the input voltage.

The standby frequency FSWstby is given by :

The ratio between the nominal and standby switching frequencies can be as high as 4,

depending on the Lp value and input voltage.

Figure 4. .Standby Mode Implementation

PSWstby

STBY

PRST

-----------------FSWnom

•=

COMP

COMPsd

COMPbl

COMPoff

600ns

350ns

SWnom

SWstby

STBY

RST

Minimum 1

ton

tu r n on

VIPer53EDIP - E / VIPer53ESP - E High Voltage Start-up Current Source

DocRev1 13/ 31

8 High Voltage St art-up Cu rrent Source

An integrated high voltage current source provides a bias current from the DRAIN pin during

the start-up phase. This current is par tially absorbed by internal control circ uits in standby

mode with reduced consumption, and also supplies the external ca pacitor connected to the

VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the

UVLO logic, the device turns into active m ode and starts s witching. The sta rt-up current

generator is switched off , and the converter should normally provide the needed current on

the VDD p in through the auxiliary winding of the transformer, as shown on Figure 3 on

page 8.

The external capacitor CVDD on the VDD pin must be sized according to the time needed by

the converter to start-up, when the device starts switching. This time tss depends on many

param eters , including transformer design, output capacitors, soft start feature, and

compensa tion network implem ented on the COMP pin and possible secondary feedbac k

circuit. The following formula can be used for defining the minimum cap acitor needed:

Figure 9 on pag e 22 shows a typical start-up event. VDD starts from 0V with a charging

current IDDch1 at about 9 mA. When about VDDoff is reached, the charging current is reduc ed

down to IDDch2 which is about 0.6mA. This lower curr ent leads to a slope change on the VDD

rise. Device starts switching for VDD equal to VDDon, and the auxiliary winding delivers some

energy to VDD capacitor after the start-up time tss.

The charging current change at VDDoff a ll o ws a fa s t comp lete start-u p ti me tSDU, and

maintains a low restart d uty cycle. This is especially useful for short circuits and overloads

conditions, as described in the follo wing sec tion.

CVDD IDD1 tss⋅

VDDhyst

------------------------>

High Voltage Start-up Current Source VIPer53EDIP - E / VIPer53 ESP - E

14/31 DocRev1

Figure 5. Start-up Waveforms

IDD

IDD1

tSS

IDDch2

IDDch1

VDDsd

VDDst

VDDreg

VDD

tSU

VIPer53EDIP - E / VIPer53ESP - E Short-Circuit and Overload Protection

DocRev1 15/ 31

9 Short-Circuit and Overload Protection

A VCOMPovl t hreshold of about 4.4V has been implemented on the COMP pin. When VCOMP

goes above this level, the capacitor connected on the TOVL pin begins to charg e. When

reaching typically VOVLth (4V), the internal MOSFET driver is dis abled and the device stops

switching. This st ate is latched because of to the regulation loop which maintains the COMP

pin voltage above th e V COMPo vl threshold. Since the VDD pin does not receive any more

energy from the auxiliary winding, its voltage drops down until it reaches VDDoff and the

device is reset, r echarging the VDD c ap a ci to r fo r a new restart cycl e . No te: If VCOMP drop s

below the VCOMPovl threshold for any reason during the VDD drop, the device re su mes

switching immediately.

The device enters an endless restart sequence if the overload or short circuit condition is

maintained. The restart duty cycle DRST is defined as the time ratio for which the device tries

to restart, thus delivering its full power capability to the output. In order to keep the whole

converter in a safe state during this event, DRST mus t be kept as l ow as possible, without

compromising the real start-up of the converter. A typical value of about 10% is generally

suf fici ent. For this purpose, both VDD and TOVL capacitors can be used to satisfy the

following conditi ons:

Refer to the previous sta rt-up sec tion for the def inition of tss, and CVDD must also be

checked against the limit given in this section. The maximum value of the two calculus will

be adopted.

All this behavior can be observed on Figure 2 on page 7. In Figure 7 on page 20 the value of

the drain current Id for VCOMP = V COMPovl is shown. The correspondi ng parameter IDmax is

the drain current to take into account for design purposes. Since IDmax represents the

maximum value for which the overload protection is not triggered, it defines the power

capability of the power supply.

COVL 12.5 10 6–tss⋅⋅>

CVDD 810

DRST

-------------- 1–

⎝⎠

⎛⎞

COVL IDDch2

⋅

VDDhyst

------------------------------------⋅⋅ ⋅>

Regulation Loop Stability VIPer53EDIP - E / VIPer53ESP - E

16/31 DocRev1

10 Regulation Loop Stability

The complete converter open loop transfer function can be built from both power cell an d

the feedback network transfe r functions. A theoretical example can be seen in Figure 1 1 on

page 22 for a discontinuous mode flybac k loaded by a simple resistor.

A typical schematic corresponding to this situation can be seen on Figu re 3 on page 8 . The

transfer function of the power cell is represented as G(s) in .Figure 11 on page 22 It exhibits

a pole which depends on the output load and on the output capacitor value. As the load of a

converter may change, two curves are shown for two different values of output resistan ce

value, RL1 and R L2. A zero at higher f requency values then appears, due to the output

capacitor ES R. Note: The overall transfer function does not depend on the input voltage

because of the current m ode control. A typical regulation loop is shown on Figure 3 on

page 8 and has a fixed behavior represented by F(s) on Figure 11 on page 22. A double

zero due to the R1-C1 network on the COMP pin and to the integrator built around the TL431

and R2-C2 is set at the same value as the maximum load RL2 pole.

The total transfer function is shown as F(s). G(s) at the bottom of Figure 11 on page 22. For

maximum load (plain line), the load pole begins e xactly where the zeros of the COMP pin

and the TL431 stop, and this results in a first order decreasing slope until it reaches the zero

of the output capacitor ESR. The point where the complete transfer function has a unity gain

is known as the regulation bandwidth and has a double interest:

– The higher it is, the faster the reaction will be to an eventual load change, and the

smaller the output voltage cha nge w ill be.

– The phase shift in the comp lete syste m at this point has to be less than 135° to

ensure good stability. Ge nerally, a first-order slope gives 90° of phase shift, and a

second-order gives 180°.

In Figure 3 on page 8, the u nity gain is reached in a first order slope, so the stability is

ensured.

The dynamic load regulation is improved by increasing the regulation bandwidt h, but some

limitations have to be res pected :

1. As the transfer function above zero due the ESR capacitor is not reliable (the ESR itself

is not well spe cified, and other parasitic effects may take p lace), the bandwidth should

always be lower than the minimum of FC and ESR zero

2. As the highest bandwidth is obtained with the highest output power (plain line with RL2

load in Figure 3, the above criteria will be ch ecked for this c ondition and allows the

value of R4 if R1 is set to a fixed value (e.g., (2.2kΩ).

As the highest bandwidth is obtained with the highest output power (Plain li ne with RL2 load

in Figure 3), the above criteria wi ll be checked for this condition and allows to define the

value of R4, if R1 is set fixed (2.2kΩ, for instance). The following formula ca n be derived:

Go is the c urrent transfer ratio of the optocoupler.

R4PMAX

POUT2

---------------------GOR1

⋅

FBW2 RL2 COUT

⋅⋅

--------------------------------------------------------⋅=

POUT2 VOUT

RL2

-----------------=

with:

PMAX 1

---LPILIM

2FSW

⋅⋅ ⋅=

and:

VIPer53EDIP - E / VIPer53ESP - E Regulation Loop Stability

DocRev1 17/ 31

The lowest load gives another condition for stability: The frequency FBW1 must not

encounter the third order slope generated by the load pole, the R1-C1 network on the

COMP pin and the R2-C2 network at the level of the TL43 1 on seconda ry side. This

condition can be met by adjusting both C1 and C2 values:

The above formula gives a minimum value for C1. It ca n be then increased to provide a

natural soft start function as this c apacitor is charged by the current ICOMP at start-u p.

C1RL1 COUT

⋅

6.3 GO

--------- R1

⋅⋅

-----------------------------------POUT1

PMAX

---------------------⋅>

C2RL1 COUT

⋅

6.3 GO

--------- R1R2

⋅⋅⋅

-----------------------------------------------POUT1

PMAX

---------------------⋅>

POUT1 VOUT

RL1

-------------------=

with:

Special Recommendations VIPer53EDIP - E / VIPer53ESP - E

18/31 DocRev1

11 Special Recommendations

10nF capacitor (minimum value: 8nF) should always be connected to the COMP pin to

ensure correct stability of the internal current source Figure 12 on page 22.

In order to improve the ruggedness of the device versus eventual drain overvoltages, a

resistance of 1kΩ should be inserted in series with t he TOVL pin, as shown on Figure 12 on

page 22

Note: This resistance does not impact the overload delay, as its value is negligible prior to the

internal pull-up resistance (about 125k

Ω

VIPer53EDIP - E / VIPer53ESP - E So ftw are Imp lementation

DocRev1 19/ 31

12 Software Implementation

All the abov e cons iderations and som e others are included included in ST design software

which provides all of the needed c om ponents around the VIPer device for specified output

configurations, and is available on www.st.com.

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

20/31 DocRev1

13 Operation pictures

Figure 6. Rise and Fall time

Figure 7. Overl oaded Event

300

CLD

C<<C

OSS

VDD

OSC

DRAIN

SOURCECOMP TOVL

CONTROL

90%

10%

Normal

operation

VTOVL

VCOMP

VDD

VDDon

VDDoff

VDS

Switching

Not

switching

Abnormal

operation

VOVLth tOVL

VDIFFovl

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

DocRev1 21/ 31

F ig ure 8. Co m p lete Convert er Tr an sfer F unction

FS. GS

πRL1 COUT

⋅⋅

------------------------------------------

πRL2 COUT

⋅⋅

------------------------------------------

2πESR COUT

⋅⋅ ⋅

---------------------------------------------------

FBW2

FBW1

3.2 PMAX

POUT2

---------------------⋅

3.2 PMAX

POUT1

---------------------⋅

-------⋅

2πRCOMP CCOMP

⋅⋅ ⋅

--------------------------------------------------------------------

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

22/31 DocRev1

Figu re 9. Star t-u p VDD current Figure 10. Blanking Time

Figu re 11. T hermal S hutd ow n Fig ure 12 . Ove rvol tage E ve nt

IDD

VDD

VDDhyst

VDDoff VDDon

IDD0

IDDch1

IDDch2

VDS = 100 V

FSW = 0 kHz

COMP

COMPbl

COMPhi

VDD

VCOMP

VDDon

TSD

TSD-THYST

Automatic

startup

Abnormal

operation

VDS

VCOMP

VDD

VDDovp

Switching

Not

switching

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

DocRev1 23/ 31

Figure 15. Oscillator Schematic

Figu re 13. Sh utdo wn A ct i on Fig ure 14. Com p Pi n Gai n and Off set

COMP

OSC

COMPoff

OSChi

OSClo

COMP

Dpeak

COMPos

COMPhi

Slope = 1 / H

COMP

Dlim

COMPovl

Dmax

320 Ω

SOURCE

OSC

VDD

PWM

section

Vcc

Operation pictures VIPer53EDIP - E / VIPer53ESP - E

24/31 DocRev1

The switching frequency settings shown on the graphic here below is val id within the

following boundaries:

Rt > 2kΩ

FSW = 300kHz

Figure 16. Oscillator Settings

Figure 17. Typic al Frequency Variatio n vs. Junction Tem perature

11010

300

100

Frequency (kHz)

Ω

)

1nF

2.2nF

4.7nF

10nF

22nF

-20 0 20 40 60 80 100 12

0.96

0.98

1.02

1.04

Normalised Freque ncy

Temperature (°C)

VIPer53EDIP - E / VIPer53ESP - E Operation pictures

DocRev1 25/ 31

Figure 18. Typ ic al Current Limitation vs. Junction Temperature

-20 0 20 40 60 80 100 12

0.96

0.98

1.02

1.04

No rm a lis ed IDlim

Temperature (°C)

Mech anical Data VIPer53E DIP - E / VIPer53ESP - E

26/31 DocRev1

14 Mechanical Data

In order to meet environ men tal requirements, ST offers these dev ices in ECOPAC K®

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK spec ifications are available at: www.st.com.

VIPer53EDIP - E / VIPer53ESP - E Mechanical Da ta

DocRev1 27/ 31

Figure 19. Package Dimensions

Tabl e 11. DIP8 Mech anical Data

Dimensions

Ref. Databook (mm )

Nom. Min Max

A5.33

A1 0.38

A2 2.92 3.30 4.95

b 0.36 0.46 0.56

b2 1.14 1.52 1.78

c 0.20 0.25 0.36

D 9.02 9.27 10.16

E 7.62 7.87 8.26

E1 6.10 6.35 7.11

e2.54

eA 7.62

eB 10.92

L 2.92 3.30 3.81

Package W eight Gr. 470

Mech anical Data VIPer53E DIP - E / VIPer53ESP - E

28/31 DocRev1

Figure 20. Package Dimensions

Tabl e 12. PowerSO-10 Mechanical Data

Dimensions

Ref. Databook (mm )

Nom. Min Max

A 3.35 3.65

A1 0.00 0.10

B 0.40 0.60

c 0.35 0.55

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50

E1 7.20 7.40

E2 7.20 7.60

E3 6.10 6.35

E4 5.90 6.10

e 1.27

F 1.25 1.35

H 13.80 14.40

h 0.50

L 1.20 1.80

q 1.70

α 0° 8°

VIPer53EDIP - E / VIPer53ESP - E Order codes

DocRev1 29/ 31

15 Order codes

Ta ble 13. Order co des

Part Number Package Shipment

VIPer53 ESPTR - E PowerSO-10 Tape and reel

VIPer 53ESP - E PowerSO-1 0 Tube

VIPer53EDIP - E DIP-8 Tube

Revision history VIPer53EDIP - E / VIPer53ESP - E

30/31 DocRev1

16 Revision history

Table 14. Document revision history

Date Revision Changes

12-Jan-2006 1Initial re le a s e.

VIPer53EDIP - E / VIPer53ESP - E Revision history

DocRev1 31/ 31

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