MC74HC273A Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. http://onsemi.com MARKING DIAGRAMS 20 20 PDIP-20 N SUFFIX CASE 738 Features * * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 264 FETs or 66 Equivalent Gates Pb-Free Packages are Available* MC74HC273AN AWLYYWWG 1 1 20 20 1 SOIC-20 DW SUFFIX CASE 751D 74HC273A AWLYYWWG 1 20 20 1 HC 273A ALYWG G TSSOP-20 DT SUFFIX CASE 948E 1 20 1 20 SOEIAJ-20 F SUFFIX CASE 967 1 74HC273A AWLYWWG A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2005 July, 2005 - Rev. 10 1 Publication Order Number: MC74HC273A/D MC74HC273A PIN ASSIGNMENT RESET 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q5 Q3 9 12 Q4 Q6 GND 10 11 CLOCK LOGIC DIAGRAM D0 D1 D2 D3 DATA INPUTS D4 D5 D6 D7 CLOCK RESET 3 2 4 5 7 6 8 9 13 12 14 17 18 11 1 15 16 19 Q0 Q1 Q2 Q3 Q4 NONINVERTING OUTPUTS Q7 FUNCTION TABLE Inputs PIN 20 = VCC PIN 10 = GND IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIII IIII III IIIIIIIIIIIIIIIIII Design Criteria Value Units Internal Gate Count* 66 ea Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 mW .0075 pJ Speed Power Product Output Reset Clock D Q L H H H H X X H L X X L H L No Change No Change L *Equivalent to a two-input NAND gate. ORDERING INFORMATION Package Shipping MC74HC273AN PDIP-20 18 Units / Rail MC74HC273ANG PDIP-20 (Pb-Free) 18 Units / Rail MC74HC273ADW SOIC-20 WIDE 38 Units / Rail MC74HC273ADWG SOIC-20 WIDE (Pb-Free) 38 Units / Rail MC74HC273ADWR2 SOIC-20 WIDE 1000 Tape & Reel MC74HC273ADWR2G SOIC-20 WIDE (Pb-Free) 1000 Tape & Reel MC74HC273ADT TSSOP-20* 75 Units / Rail MC74HC273ADTG TSSOP-20* 75 Units / Rail MC74HC273ADTR2 TSSOP-20* 2500 Tape & Reel MC74HC273ADTR2G TSSOP-20* 2500 Tape & Reel MC74HC273AF SOEIAJ-20 40 Units / Rail MC74HC273AFG SOEIAJ-20 (Pb-Free) 40 Units / Rail MC74HC273AFEL SOEIAJ-20 2000 Tape & Reel MC74HC273AFELG SOEIAJ-20 (Pb-Free) 2000 Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC74HC273A IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIII IIIII III IIII IIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII III III III IIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII III IIII IIIIIIIIIIIIII III III IIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII II IIIIIIIII III IIII IIII IIII IIII IIIIIIIIII II IIIIIIIII III IIII IIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII II IIIIIIIII III IIII IIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V - 55 to 25_C Symbol Parameter v 85_C v 125_C Unit VIH Minimum High-Level Input Voltage Vout = VCC - 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage Vin = VIH |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 Test Conditions Vin = VIH VOL Maximum Low-Level Output Voltage |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA Vin = VIL |Iout| v 20 mA Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA http://onsemi.com 3 V MC74HC273A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIII IIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C v 85_C v 125_C Unit Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 mA IOZ Maximum Three-State Leakage Current Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND 6.0 0.5 5.0 10 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). IIII IIIIIIIIIIIIIIIIII III IIIIIIIIII II IIII IIIIIIIIIIIIIIIIII III IIIIIIIIII II IIII IIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIII IIIIIIII IIIIII IIII IIIIIIIIIIIIIIIIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIII IIIIIIII IIIIII II IIII IIIIIIIIIIIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIII III IIII IIII IIII II IIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 15 30 35 5.0 10 24 28 4.0 8.0 20 24 MHz tPLH tPHL Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 3.0 4.5 6.0 145 90 29 25 180 120 36 31 220 140 44 38 ns tPHL Maximum Propagation Delay, Reset to Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 145 90 29 25 180 120 36 31 220 140 44 38 ns tTLH tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns Cin Maximum Input Capacitance 10 10 10 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD 48 Power Dissipation Capacitance (Per Enabled Output)* * Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2f http://onsemi.com 4 pF + ICC VCC . For load considerations, see Chapter 2 of the MC74HC273A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII IIIIII IIIIIIII IIIIIIIIIIIII IIIIIIIIIIII IIII IIIIIIIIIIIII II IIIII IIIII IIIII III III III III III III IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIII IIII IIIIIIIIIIIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIII IIII IIIIIIIIIIIII II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIII III III III III III III III III II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol Parameter Figure VCC Volts - 55 to 25_C Min Max v 85_C Min Max v 125_C Min Max Unit tsu Minimum Setup Time, Data to Clock 3 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns th Minimum Hold Time, Clock to Data 3 2.0 3.0 4.5 6.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 ns trec Minimum Recovery Time, Reset Inactive to Clock 2 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 ns tw Minimum Pulse Width, Clock 1 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns tw Minimum Pulse Width, Reset 2 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns Maximum Input Rise and Fall Times 1 2.0 3.0 4.5 6.0 tr, tf http://onsemi.com 5 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns MC74HC273A SWITCHING WAVEFORMS CLOCK tw tf tr VCC 90% 50% 10% tw GND 1/fmax Q 50% trec 90% 50% 10% CLOCK tTLH 50% tTHL Figure 1. tsu GND th VCC 50% GND D0 Figure 3. D1 D2 TEST POINT OUTPUT DEVICE UNDER TEST GND VCC 50% CLOCK VCC Figure 2. VALID DATA GND tPHL Q tPHL tPLH VCC 50% RESET DATA INPUTS D3 D4 CL* D5 D6 *Includes all probe and jig capacitance Figure 4. Test Circuit D7 3 4 7 8 13 14 17 18 C DR C DR C DR C DR C DR C DR C DR C DR Q Q Q Q Q Q Q Q 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 11 1 Figure 5. Expanded Logic Diagram http://onsemi.com 6 NONINVERTING OUTPUTS MC74HC273A PACKAGE DIMENSIONS PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. -A- 20 11 1 10 B L C -T- K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) M T A M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 M SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G 20 11 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q A B M D 18X e A1 SEATING PLANE C T http://onsemi.com 7 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74HC273A PACKAGE DIMENSIONS TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 IIII IIII IIII 11 J J1 B L -U- PIN 1 IDENT SECTION N-N 1 10 0.25 (0.010) N 0.15 (0.006) T U S M A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C D G H DETAIL E 0.100 (0.004) -T- SEATING PLANE http://onsemi.com 8 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC273A PACKAGE DIMENSIONS SOEIAJ-20 F SUFFIX CASE 967-01 ISSUE O 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D VIEW P e A c DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) http://onsemi.com 9 MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032 MC74HC273A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 http://onsemi.com 10 For additional information, please contact your local Sales Representative. MC74HC273A/D