150 mA, Low Quiescent Current,
CMOS Linear Regulator
Data Sheet ADP121
Rev. G
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FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 150 mA
Low quiescent current
IGND = 11 µA with 0 A load
IGND = 30 µA with 150 mA load
Low shutdown current: <1 µA
Low dropout voltage
90 mV @ 150 mA load
High PSRR
70 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 µV rms at VOUT = 1.2 V
No noise bypass capacitor required
Output voltage accuracy: ±1%
Stable with a small 1 µF ceramic output capacitor
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Post regulation
TYPICAL APPLICATION CIRCUITS
NC = NO CONNECT
1
2
3
5
4
06901-001
C
OUT
1µF
C
IN
1µF
V
OUT
= 1. 8VV
IN
= 2. 3V VOUT
NC
VIN
GND
EN
OFF
ON
Figure 1. ADP121 TSOT with Fixed Output Voltage, 1.8 V
VIN VOUT
EN GND
06901-002
C
OUT
1µF
C
IN
1µF
V
OUT
= 1. 8V
V
IN
= 2.3V
OFF
ON
Figure 2. ADP121 WLCSP with Fixed Output Voltage, 1.8 V
GENERAL DESCRIPTION
The ADP121 is a quiescent current, low dropout, linear regulator
that operates from 2.3 V to 5.5 V and provides up to 150 mA of
output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide
input voltage range. The low 30 A of quiescent current at full
load makes the ADP121 ideal for battery-operated portable
equipment.
The ADP121 is available in output voltages ranging from 1.2 V
to 3.3 V. The parts are optimized for stable operation with small
1 µF ceramic output capacitors. The ADP121 delivers good
transient performance with minimal board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP121 is available
in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch halide-free
WLCSP packages and utilizes the smallest footprint solution to
meet a variety of portable applications.
ADP121 Data Sheet
Rev. G | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Recommended Specifications: Input and Output Capacitors 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations ............................................................ 14
PCB Layout Considerations ...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/12—Rev. F to Rev. G
Change to Ordering Guide ............................................................. 19
7/12—Rev. E to Rev. F
Updated Outline Dimensions ........................................................ 18
Change to Ordering Guide ............................................................. 19
8/11—Rev. D to Rev. E
Changes to Figure 22 ........................................................................ 9
Changes to Ordering Guide .......................................................... 19
1/10—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 19
11/09—Rev. B to Rev. C
Changes to Figure 1, Figure 2, and General Description
Section ................................................................................................ 1
Changes to Table 3 ............................................................................. 5
Changes to Figure 46 Caption and Figure 47 Caption .............. 17
Changes to Ordering Guide .......................................................... 19
9/09—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
3/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections .............. 1
Changes to Input and Output Capacitor Parameter ..................... 4
Changes to Figure 17 to Figure 20 ................................................... 9
Changes to Figure 49 ...................................................................... 17
Added Figure 50 ............................................................................. 17
Changes to Ordering Guide .......................................................... 19
7/08—Revision 0: Initial Version
Data Sheet ADP121
Rev. G | Page 3 of 20
SPECIFICATIONS
VIN = (VOUT + 0.5 V) or 2.3 V, whichever is greater; EN = VIN; IOUT = 10 mA; CIN = COUT = 1 µF; TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE V
IN
T
J
= −40°C to +125°C 2.3 5.5 V
OPERATING SUPPLY CURRENT I
GND
I
OUT
= 0 µA 11 µA
I
OUT
= 0 µA, T
J
= −40°C to +125°C 21 µA
I
OUT
= 10 mA 15 µA
I
OUT
= 10 mA, T
J
= −40°C to +125°C 29 µA
I
OUT
= 150 mA 30 µA
I
OUT
= 150 mA, T
J
= −40°C to +125°C 40 µA
SHUTDOWN CURRENT I
GND-SD
EN = GND 0.1 µA
EN = GND, T
J
= −40°C to +125°C 1.5 µA
FIXED OUTPUT VOLTAGE ACCURACY V
OUT
I
OUT
= 10 mA −1 +1 %
100 µA < IOUT < 150 mA,
V
IN
= (V
OUT
+ 0.5 V) to 5.5 V
−2 +2 %
100 µA < IOUT < 150 mA,
VIN = (VOUT + 0.5 V) to 5.5 V
T
J
= −40°C to +125°C
−3 +3 %
REGULATION
Line Regulation ∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 5.5 V, IOUT = 1 mA
T
J
= −40°C to +125°C
−0.03 +0.03 %/V
Load Regulation
1
∆V
OUT
/∆I
OUT
I
OUT
= 1 mA to 150 mA 0.001 %/mA
IOUT = 1 mA to 150 mA
T
J
= −40°C to +125°C
0.005 %/mA
DROPOUT VOLTAGE
2
V
DROPOUT
V
OUT
= 3.3 V
TSOT I
OUT
= 10 mA 8 mV
I
OUT
= 10 mA, T
J
= −40°C to +125°C 12 mV
I
OUT
= 150 mA 120 mV
IOUT = 150 mA, TJ = −40°C to +125°C
180
mV
WLCSP I
OUT
= 10 mA 6 mV
I
OUT
= 10 mA, T
J
= −40°C to +125°C 9 mV
I
OUT
= 150 mA 90 mV
I
OUT
= 150 mA, T
J
= −40°C to +125°C 135 mV
START-UP TIME3 T
START-UP
V
OUT
= 3.3 V 120 µs
CURRENT-LIMIT THRESHOLD
4
I
LIMIT
160 225 350 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TSSD
TJ rising
150
°C
Thermal Shutdown Hysteresis TS
SD-HYS
15 °C
EN INPUT
EN Input Logic High
VIH
2.3 V ≤ VIN ≤ 5.5 V
1.2
V
EN Input Logic Low V
IL
2.3 V ≤ V
IN
≤ 5.5 V 0.4 V
EN Input Leakage Current V
I-LEAKAGE
EN = VIN or GND 0.05 µA
EN = VIN or GND, T
J
= −40°C to +125°C 1
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLO
RISE
2.25 V
Input Voltage Falling UVLO
FAL L
1.5 V
Hysteresis UVLO
HYS
120 mV
OUTPUT NOISE OUT
NOISE
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 3.3 V 65 µV rms
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 2.5 V 52 µV rms
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 1.2 V 40 µV rms
ADP121 Data Sheet
Rev. G | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR 10 kHz, V
IN
= 5 V, V
OUT
= 3.3 V 60 dB
10 kHz, V
IN
= 5 V, V
OUT
= 2.5 V 66 dB
10 kHz, V
IN
= 5 V, V
OUT
= 1.2 V 70 dB
1 Based on an end-point calculation using 1 mA and 100 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.3 V.
3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value.
4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITORS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT AND OUTPUT CAPACITOR1
Minimum Input and Output Capacitance
CMIN
TA = −40°C to +125°C
0.70
µF
Capacitor ESR R
ESR
T
A
= −40°C to +125°C 0.001 1 Ω
1 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP121
Rev. G | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +6.5 V
VOUT to GND −0.3 V to VIN
EN to GND −0.3 V to +6.5 V
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature Range −40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP121 can be damaged when the junction
temperature limits are exceeded. Monitoring the ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. TJ of the device is dependent on
the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). TJ is calculated from TA and PD using the
following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance, θJA, is based on
modeling and calculation using a four-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4” × 3”, circuit
board. Refer to JESD 51-7 and JESD 51-9 for detailed
information on the board construction. For additional
information, see AN-617 Application Note, MicroCSPTM
Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
measured in °C / W. ΨJB is based on modeling and calculation
using a four-layer board. The JESD51-12 Guidelines for Reporting
and Using Package Thermal Information states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-
world applications. Maximum TJ is calculated from the board
temperature (TB) and PD using the following formula:
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θ
JA
Ψ
Unit
5-Lead TSOT 170 43 °C/W
4-Ball 0.4 mm Pitch WLCSP 260 58 °C/W
ESD CAUTION
ADP121 Data Sheet
Rev. G | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
TOP VIEW
(Not t o Scale)
1
2
3
5
4
06901-003
VIN
GND
EN
VOUT
NC
1 2
A
B
TOP VIEW
(Not t o Scale)
06901-004
VIN VOUT
EN GND
Figure 3. 5-Lead TSOT Pin Configuration Figure 4. 4-Ball WLCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
TSOT WLCSP
1 A1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or larger capacitor.
2 B2 GND Ground.
3 B1 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
4 N/A NC No Connect. Not connected internally.
5
A2
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
Data Sheet ADP121
Rev. G | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
1.804
1.802
1.800
1.798
1.796
1.794
1.792
1.790
1.788
1.786
V
OUT
(V)
–40°C –5°C 25°C
85°C 125°C
TJ (° C)
06901-005
VOUT = 1. 8V
VIN = 2.3V
ILOAD = 10µA
ILOAD = 100µA
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 150mA
Figure 5. Output Voltage vs. Junction Temperature
1.806
1.804
1.802
1.800
1.798
1.796
1.794
0.001 0.01 0.1 110 100 1000
I
LOAD
(mA)
V
OUT
(V)
06901-006
V
OUT
= 1.8V
V
IN
= 2.3V
T
A
= 25° C
Figure 6. Output Voltage vs. Load Current
1.806
1.804
1.802
1.800
1.798
1.796
1.794
V
OUT
(V)
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
V
IN
(V)
06901-007
I
LOAD
= 10µA
I
LOAD
= 100µA
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
V
OUT
= 1.8V
T
A
= 25° C
Figure 7. Output Voltage vs. Input Voltage
40
35
30
25
20
15
10
5
0
GROUND CURRENT ( µA)
–40°C –5°C 25°C 85°C 125°C
T
J
(° C)
06901-008
V
OUT
= 1.8V
V
IN
= 2.3V
I
LOAD
= 10µA
I
LOAD
= 100µA
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 150mA
Figure 8. Ground Current vs. Junction Temperature
35
30
25
20
15
10
5
0
0.001 0.01 0.1 110 100 1000
I
LOAD
(mA)
GROUND CURRENT ( µA)
06901-009
V
OUT
= 1.8V
V
IN
= 2.3V
T
A
= 25° C
Figure 9. Ground Current vs. Load Current
35
30
25
20
15
10
5
0
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
V
IN
(V)
GROUND CURRENT ( µA)
06901-010
V
OUT
= 1.8V
T
A
= 25° C
I
LOAD
= 10µA
I
LOAD
= 100µA
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 100mA
I
LOAD
= 150mA
Figure 10. Ground Current vs. Input Voltage
ADP121 Data Sheet
Rev. G | Page 8 of 20
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
SHUT DOWN CURRE NT (µ A)
06901-011
VIN = 2.30
VIN = 2.50
VIN = 3.00
VIN = 3.50
VIN = 4.20
VIN = 5.50
Figure 11. Shutdown Current vs. Temperature at Various Input Voltages
120
140
160
180
100
80
60
40
20
0110 100 1000
I
LOAD
(mA)
V
DROPOUT
(mV)
06901-018
T
A
= 25° C
V
OUT
= 3.3V
V
OUT
= 2.5V
Figure 12. Dropout Voltage vs. Load Current, TSOT
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60
V
IN
(V)
V
OUT
(V)
06901-019
V
OUT
= 3.3V
T
A
= 25° C
V
OUT
@ 1mA
V
OUT
@ 10mA
V
OUT
@ 20mA
V
OUT
@ 50mA
V
OUT
@ 100mA
V
OUT
@ 150mA
Figure 13. Output Voltage vs. Input Voltage (In Dropout), TSOT
100
80
60
40
140
120
20
0110 100 1000
ILOAD (mA)
VDROPOUT (mV)
06901-012
TA = 25° C
VOUT = 3. 3V
VOUT = 2. 5V
Figure 14. Dropout Voltage vs. Load Current, WLCSP
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60
V
IN
(V)
V
OUT
(V)
06901-013
V
OUT
= 3.3V
T
A
= 25° C
V
OUT
@ 1mA
V
OUT
@ 10mA
V
OUT
@ 20mA
V
OUT
@ 50mA
V
OUT
@ 100mA
V
OUT
@ 150mA
Figure 15. Output Voltage vs. Input Voltage (In Dropout), WLCSP
60
50
40
30
20
10
0
3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60
V
IN
(V)
GROUND CURRENT ( µA)
06901-020
V
OUT
= 3.3V
T
A
= 25° C
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 20mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 150mA
Figure 16. Ground Current vs. Input Voltage (In Dropout)
Data Sheet ADP121
Rev. G | Page 9 of 20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
06901-014
VRIPPLE = 50mV
VIN = 5V
VOUT = 1. 2V
COUT = 1µ F 150mA
100mA
10mA
1mA
100µA
0µA
Figure 17. Power Supply Rejection Ratio vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
06901-015
VRIPPLE = 50mV
VIN = 5V
VOUT = 1. 8V
COUT = 1µ F
150mA
100mA
10mA
1mA
100µA
0µA
Figure 18. Power Supply Rejection Ratio vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
06901-016
VRIPPLE = 50mV
VIN = 5V
VOUT = 3. 3V
COUT = 1µ F
150mA
100mA
10mA
1mA
100µA
0µA
Figure 19. Power Supply Rejection Ratio vs. Frequency
0
–20
–40
–60
–80
–100
–12010 100 1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
PSRR ( dB)
06901-017
3.3V/150mA
3.3V/100µA 1.2V/150mA
1.2V/100µA 1.8V/150mA
1.8V/100µA
Figure 20. Power Supply Rejection Ratio vs. Frequency at Various Output
Voltages and Load Currents
10
1
0.1
010 100 1k 10k 100k
FRE QUENCY ( Hz )
NOISE (µV/√Hz)
06901-021
1.2V
1.8V
3.3V
Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 µF
70
60
50
40
30
20
10
0
0.001 0.01 0.1 110 100 1000
ILOAD (mA)
OUTNOISE (µV rms)
06901-022
3.3V
2.5V
1.8V
1.5V
1.2V
Figure 22. Output Noise vs. Load Current and Output Voltage, VIN = 5 V, COUT = 1 μF
ADP121 Data Sheet
Rev. G | Page 10 of 20
06901-024
(40µs/DIV)
(150mA/DIV)(50mV/DIV)
I
LOAD
V
OUT
V
IN
= 5V
V
OUT
= 1.8V
1mA TO 150mA LOAD STEP ,
2.5A/µs
Figure 23. Load Transient Response, CIN = COUT = 1 μF
06901-025
(40µs/DIV)
(150mA/DIV)(50mV/DIV)
I
LOAD
V
OUT
V
IN
= 5V
V
OUT
= 1.8V
1mA TO 150mA LOAD STEP ,
2.5A/µs
Figure 24. Load Transient Response, CIN = COUT = 4.7 μF
06901-037
(4µs/DIV)
(1V/DIV)(10mV/DIV)
VIN
VOUT
VOUT = 1. 8V ,
CIN = COUT = 1µF
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
Figure 25. Line Transient Response, Load Current = 150 mA
06901-038
(10µs/DIV)
(1V/DIV)(10mV/DIV)
VIN
VOUT
VOUT = 1. 8V ,
CIN = COUT = 1µF
4V TO 5V INPUT VOLTAGE STEP,
2V/µs
Figure 26. Line Transient Response, Load Current = 1 mA
Data Sheet ADP121
Rev. G | Page 11 of 20
THEORY OF OPERATION
The ADP121 is a low quiescent current, low dropout linear
regulator that operates from 2.3 V to 5.5 V and provides up
to 150 mA of output current. Drawing a low 30 μA quiescent
current (typical) at full load makes the ADP121 ideal for battery-
operated portable equipment. Shutdown current consumption
is typically 100 nA.
Optimized for use with small 1 µF ceramic capacitors,
the ADP121 provides excellent transient performance.
0.8V RE FERENCE
SHO RT CIRCUIT ,
UVL O, AND
THERMAL
PROTECT
SHUTDOWN
R1
R2
VOUTVIN
GND
EN
06901-023
Figure 27. Internal Block Diagram
Internally, the ADP121 consists of a reference, an error amplifier,
a feedback voltage divider, and a PMOS pass transistor. Output
current is delivered via the PMOS pass device, which is con-
trolled by the error amplifier. The error amplifier compares the
reference voltage with the feedback voltage from the output and
amplifies the difference. If the feedback voltage is lower than
the reference voltage, the gate of the PMOS device is pulled
lower, allowing more current to flow and increasing the output
voltage. If the feedback voltage is higher than the reference
voltage, the gate of the PMOS device is pulled higher, allowing
less current to flow and decreasing the output voltage.
The ADP121 is available in output voltages ranging from 1.2 V to
3.3 V. The ADP121 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is
high, VOUT turns on; when EN is low, VOUT turns off. For
automatic startup, EN can be tied to VIN.
ADP121 Data Sheet
Rev. G | Page 12 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP121 is designed for operation with small, space-saving
ceramic capacitors, but functions with most commonly used
capacitors as long as care is taken with the effective series resistance
(ESR) value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum of 0.70 µF capacitance with an
ESR of 1 Ω or less is recommended to ensure stability of the
ADP121. The transient response to changes in the load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP121 to
large changes in the load current. Figure 28 and Figure 29 show
the transient responses for output capacitance values of 1 µF and
4.7 µF, respectively.
06901-039
CH1 MEAN
115.7mA
(400ns/DIV)
(150mA/DIV)(50mV/DIV)
I
LOAD
V
OUT
V
OUT
= 1.8V ,
C
IN
= C
OUT
= 1µF
1mA TO 150mA LOAD STEP ,
2.5A/µs
Figure 28. Output Transient Response, COUT = 1 µF
06901-040
(400ns/DIV)
(150mA/DIV)(50mV/DIV)
I
LOAD
V
OUT
V
OUT
= 1.8V ,
C
IN
= C
OUT
= 4.7µF
1mA TO 150mA LOAD STEP ,
2.5A/µs
Figure 29. Output Transient Response, COUT = 4.7 µF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance is encountered. If output
capacitance greater than 1 µF is required, the input capacitor
should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the
ADP121, as long as it meets the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with a different behavior
over temperature and applied voltage. Capacitors must have an
adequate dielectric to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recomm ended. Y5V and Z5U dielectrics are not
recommended, due to their poor temperature and dc bias
characteristics.
Figure 30 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera-
ture range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
00 2 4 6 8 10
VOLT AGE (V)
CAPACI TANCE (µF)
06901-036
Figure 30. Capacitance vs. Voltage Bias Characteristic
Data Sheet ADP121
Rev. G | Page 13 of 20
Equation 1 can be used to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V from the graph in Figure 30.
Substituting these values in Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP121, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP121 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.2 V. This ensures that the inputs of the
ADP121 and the output behave in a predictable manner during
power-up.
ENABLE FEATURE
The ADP121 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. Figure 31 shows a
rising voltage on EN crossing the active threshold, and then
VOUT turns on. When a falling voltage on EN crosses the
inactive threshold, VOUT turns off.
06901-026
40ms/DIV
500mV/DIV
EN
VIN = 5V
VOUT = 1. 8V
CIN = COUT = 1µF
ILOAD = 100mA VOUT
Figure 31. ADP121 Typical EN Pin Operation
As shown in Figure 31, the EN pin has built in hysteresis. This
prevents on/off oscillations that may occur due to noise on the
EN pin as it passes through the threshold points.
The active/inactive thresholds of the EN pin are derived from
the VIN voltage. Therefore, these thresholds vary with changing
input voltage. Figure 32 shows typical EN active/inactive
thresholds when the input voltage varies from 2.3 V to 5.5 V.
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
TYPICAL EN THRESHOLDS (V)
2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
VIN (V)
EN ACT IVE
EN I NACTIV E
06901-027
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
The ADP121 utilizes an internal soft start to limit the inrush
current when the output is enabled. The start-up time for the
1.8 V option is approximately 120 µs from the time the EN
active threshold is crossed to when the output reaches 90% of its
final value. The start-up time is somewhat dependant on the
output voltage setting and increases slightly as the output
voltage increases.
6
5
4
3
2
1
0020 40 60 80 100 120 140 160 180 200
TIME (µs)
VOLT S (V)
06901-041
1.2V
1.8V
3.3V
EN
Figure 33. Typical Start-Up Time
ADP121 Data Sheet
Rev. G | Page 14 of 20
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP121 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP121 is designed to current limit when the
output load reaches 225 mA (typical). When the output load
exceeds 225 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C, the output is turned on again and output current is
restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP121 current limits, so that only 225 mA is con-
ducted into the short. If self-heating of the junction is great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates turning off the output and reducing the
output current to zero. As the junction temperature cools and
drops below 135°C, the output turns on and conducts 225 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and
150°C causes a current oscillation between 225 mA and 0 mA
that continues as long as the short remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP121 does not dissipate a lot of heat
due to high efficiency. However, in applications with a high
ambient temperature and high supply voltage to an output voltage
differential, the heat dissipated in the package is large enough
that it can cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP121 must not exceed 125°C. To e nsu re that the junction
temperature stays below this maximum value, the user needs to
be aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction-and-ambient air (θJA). The θJA number is dependent
on the package assembly compounds used and the amount of
copper to which the GND pins of the package are soldered on the
PCB. Table 6 shows typical θJA values for various PCB copper
sizes and Table 7 shows the typical ΨJB values for the ADP121.
Table 6. Typical θJA Values
Copper Size (mm
2
) TSOT (°C/W) WLCSP (°C/W)
0
1
170 260
50 152 159
100 146 157
300 134 153
500 131 151
1 Device soldered to minimum size pin traces.
Table 7. Typical ΨJB Values
TSOT (°C/W) WLCSP (°C/W)
42.8
58.4
The junction temperature of the ADP121 can be calculated
from the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement for
the PCB to ensure that the junction temperature does not rise
above 125°C. Figure 34 to Figure 47 show junction temperature
calculations for different ambient temperatures, load currents,
VIN-to-VOUT differentials, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, can be used to estimate the
junction temperature rise. TJ is calculated from TB and PD using
the formula
TJ = TB + (PD × ΨJB) (5)
Data Sheet ADP121
Rev. G | Page 15 of 20
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-028
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 34. TSOT, 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-029
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 35. TSOT, 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-030
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 36. TSOT, 0 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-031
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 37. TSOT, 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-032
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 38. TSOT, 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-033
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 39. TSOT, 0 mm2 of PCB Copper, TA = 50°C
ADP121 Data Sheet
Rev. G | Page 16 of 20
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-042
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-043
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-044
MAX JUNCTION
TEMPERATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 100mA
I
LOAD
= 150mA
I
LOAD
= 50mA
I
LOAD
= 75mA
Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-045
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-046
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION T E M P E RATURE
Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-047
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
MAX JUNCTION
TEMPERATURE
Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C
Data Sheet ADP121
Rev. G | Page 17 of 20
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-048
MAX JUNCTION T E M P E RATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
Figure 46. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C
140
120
100
80
60
40
20
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
– V
OUT
(V)
JUNCTION TEM P E RATURE, T
J
(° C)
06901-049
MAX JUNCTION T E M P E RATURE
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 25mA
I
LOAD
= 50mA
I
LOAD
= 75mA
I
LOAD
= 100mA
I
LOAD
= 150mA
Figure 47. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP121. However,
as can be seen from Table 6 and Table 7, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use 0402 or 0603 size capacitors and
resistors to achieve the smallest possible footprint solution on
boards where area is limited.
VIN VOUT
GND
EN
GND
GNDGND
06901-034
C2C1 U1
J1
ANALOG DEVICES
ADP121-xx-EVALZ
Figure 48. Example of TSOT PCB Layout
06901-050
Figure 49. Example of WLCSP PCB Layout—Top Side
06901-051
Figure 50. Example of WLCSP PCB Layout—Bottom Side
ADP121 Data Sheet
Rev. | Page 18 of 20
OUTLINE DIMENSIONS
100708-A
*COM P LIANT T O JEDE C S TANDARDS MO-193- AB WITH
THE E X CE P TION O F PACKAGE HEIG HT AND T HICKNESS .
1.60 BSC 2.80 BS C
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*1.00 MAX
*0.90 MAX
0.70 MIN
2.90 BS C
5 4
1 2 3
SEATING
PLANE
Figure 51. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
0.860
0.820 S Q
0.780
BOTTOM VIEW
(BALL SI DE UP)
TOP VIEW
(BALL SI DE DOW N)
A
12
B
BALLA1
IDENTIFIER
0.40
REF
0.660
0.600
0.540 END VIEW
0.280
0.260
0.240
0.381
0.356
0.331
SEATING
PLANE 0.230
0.200
0.170
COPLANARITY
0.05
07-10-2012-A
Figure 52. 4-Ball Wafer Level Chip Scale- Package [WLCSP]
(CB-4-2)
Dimensions show in millimeters
Data Sheet ADP121
Rev. G | Page 19 of 20
ORDERING GUIDE
Model1
Tem pera tu re
Range
Output
Voltage (V)2 Package Description
Package
Option3 Branding
ADP121-AUJZ12R7 −40°C to +125°C 1.2 5-Lead TSOT UJ-5 LC0
ADP121-AUJZ15R7 −40°C to +125°C 1.5 5-Lead TSOT UJ-5 LC1
ADP121-AUJZ18R7 −40°C to +125°C 1.8 5-Lead TSOT UJ-5 LC7
ADP121-AUJZ20R7 −40°C to +125°C 2.0 5-Lead TSOT UJ-5 LC9
ADP121-AUJZ25R7 −40°C to +125°C 2.5 5-Lead TSOT UJ-5 LCA
ADP121-AUJZ28R7 −40°C to +125°C 2.8 5-Lead TSOT UJ-5 LA3
ADP121-AUJZ30R7 −40°C to +125°C 3.0 5-Lead TSOT UJ-5 LA4
ADP121-AUJZ33R7 −40°C to +125°C 3.3 5-Lead TSOT UJ-5 LA5
ADP121-ACBZ12R7 −40°C to +125°C 1.2 4-Ball WLCSP CB-4-2 LC0
ADP121-ACBZ15R7 −40°C to +125°C 1.5 4-Ball WLCSP CB-4-2 LC1
ADP121-ACBZ165R7 −40°C to +125°C 1.65 4-Ball WLCSP CB-4-2 LC4
ADP121-ACBZ18R7 −40°C to +125°C 1.8 4-Ball WLCSP CB-4-2 LC7
ADP121-ACBZ188R7 −40°C to +125°C 1.875 4-Ball WLCSP CB-4-2 LC8
ADP121-ACBZ20R7 −40°C to +125°C 2.0 4-Ball WLCSP CB-4-2 LC9
ADP121-ACBZ25R7 −40°C to +125°C 2.5 4-Ball WLCSP CB-4-2 LCA
ADP121-ACBZ28R7 −40°C to +125°C 2.8 4-Ball WLCSP CB-4-2 LCD
ADP121-ACBZ30R7 −40°C to +125°C 3.0 4-Ball WLCSP CB-4-2 LCF
ADP121-ACBZ33R7 −40°C to +125°C 3.3 4-Ball WLCSP CB-4-2 LCG
ADP121CB-1.2-EVALZ 1.2 ADP121 1.2 V Output Evaluation Board
ADP121CB-1.5-EVALZ 1.5 ADP121 1.5 V Output Evaluation Board
ADP121CB-1.8-EVALZ 1.8 ADP121-1 1.8 V Output Evaluation Board
ADP121CB-2.0-EVALZ 2.0 ADP121-1 2.0 V Output Evaluation Board
ADP121CB-2.5-EVALZ 2.5 ADP121-1 2.5 V Output Evaluation Board
ADP121CB-2.8-EVALZ 2.8 ADP121-1 2.8 V Output Evaluation Board
ADP121CB-3.0-EVALZ 3.0 ADP121-1 3.0 V Output Evaluation Board
ADP121CB-3.3-EVALZ 3.3 ADP121-1 3.3 V Output Evaluation Board
ADP121UJZ-REDYKIT Evaluation Board Kit
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
3 The WLCSP package option is halide free.
ADP121 Data Sheet
Rev. G | Page 20 of 20
NOTES
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06901-0-8/12(G)