W9812G2GH
1M X 4 BANKS X 32BITS SDRAM
Publication Release Date:May 19, 2008
- 1 - Revision A09
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER...................................................................................................... 3
4. PIN CONFIGURATION............................................................................................................... 4
5. PIN DESCRIPTION..................................................................................................................... 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................ 7
7.2 Programming Mode Register ......................................................................................... 7
7.3 Bank Activate Command................................................................................................ 7
7.4 Read and Write Access Modes...................................................................................... 7
7.5 Burst Read Command.................................................................................................... 8
7.6 Burst Write Command.................................................................................................... 8
7.7 Read Interrupted by a Read........................................................................................... 8
7.8 Read Interrupted by a Write........................................................................................... 8
7.9 Write Interrupted by a Write ........................................................................................... 8
7.10 Write Interrupted by a Read........................................................................................... 8
7.11 Burst Stop Command..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode.................................................................... 9
7.13 Addressing Sequence of Interleave Mode..................................................................... 9
7.14 Auto-precharge Command........................................................................................... 10
7.15 Precharge Command................................................................................................... 10
7.16 Self Refresh Command................................................................................................ 10
7.17 Power Down Mode....................................................................................................... 11
7.18 No Operation Command .............................................................................................. 11
7.19 Deselect Command...................................................................................................... 11
7.20 Clock Suspend Mode ................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
8.1 Simplified Stated Diagram ........................................................................................... 13
9. ELECTRICAL CHARACTERISTICS......................................................................................... 14
9.1 Absolute Maximum Ratings ......................................................................................... 14
9.2 Recommended DC Operating Conditions.................................................................... 14
W9812G2GH
Publication Release Date:May 19, 2008
- 2 - Revision A09
9.3 Capacitance ................................................................................................................. 15
9.4 DC Characteristics ....................................................................................................... 15
9.5 AC Characteristics and Operating Condition ............................................................... 16
10. TIMING WAVEFORMS............................................................................................................. 19
10.1 Command Input Timing................................................................................................ 19
10.2 Read Timing................................................................................................................. 20
10.3 Control Timing of Input/Output Data ............................................................................ 21
10.4 Mode Register Set Cycle ............................................................................................. 22
11. OPERATING TIMING EXAMPLE ............................................................................................. 23
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ..................................... 23
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) .......... 24
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ..................................... 25
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) .......... 26
11.5 Interleaved Bank Write (Burst Length = 8)................................................................... 27
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)........................................ 28
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3).............................................. 29
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) .................................. 30
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ....................................... 31
11.10 Auto-precharge Write (Burst Length = 4)..................................................................... 32
11.11 Auto Refresh Cycle ...................................................................................................... 33
11.12 Self Refresh Cycle ....................................................................................................... 34
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................ 35
11.14 Power Down Mode....................................................................................................... 36
11.15 Auto-precharge Timing (Read Cycle) .......................................................................... 37
11.16 Auto-precharge Timing (Write Cycle)........................................................................... 38
11.17 Timing Chart of Read to Write Cycle ........................................................................... 39
11.18 Timing Chart of Write to Read Cycle ........................................................................... 39
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)........................................... 40
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)........................................... 40
11.21 CKE/DQM Input Timing (Write Cycle).......................................................................... 41
11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 42
12. PACKAGE SPECIFICATION .................................................................................................... 43
12.1 86L TSOP (II)-400 mil .................................................................................................. 43
13. REVISION HISTORY ................................................................................................................ 44
W9812G2GH
Publication Release Date:May 19, 2008
- 3 - Revision A09
1. GENERAL DESCRIPTION
W9812G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology,
W9812G2GH delivers a data bandwidth of up to 200M words per second (-5). For different application,
W9812G2GH is sorted into the following speed grades: -5/-6/-6C/-6I and -75. The –5 is compliant to
the 200MHz/CL3 specification. The –6/-6C/-6I is compliant to the 166MHz/CL3 specification. (The
grade of and -6C/-6I is tIH=0.8nS and the -6I grade which is guaranteed to support -40°C ~ 85°C.). The
-75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9812G2GH is ideal for main memory in
high performance applications.
2. FEATURES
• 3.3V ± 0.3 V for -5/-6/-6I/-75 grade power supply
2.7V～3.6V for -6C grade power supply
2.3V～2.7V, @ tCK >10nS for -6C grade power supply
• Up to 200 MHz Clock Frequency
• 1,048,576 Words × 4 banks × 32 bits organization
• Self Refresh Mode
• CAS Latency: 2 and 3
• Burst Length: 1, 2, 4, 8 and full page
• Burst Read, Single Writes Mode
• Byte Data Controlled by DQM0-3
• Auto-precharge and Controlled Precharge
• 4K Refresh cycles/64 mS
• Interface: LVTTL
• Packaged in TSOP II 86-pin , using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER SPEED MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
W9812G2GH-5 200MHz/CL3 2mA 0°C ~ 70°C
W9812G2GH-6 166MHz/CL3 2mA 0°C ~ 70°C
W9812G2GH-6C 166MHz/CL3 2mA 0°C ~ 70°C
W9812G2GH-6I 166MHz/CL3 2mA -40°C ~ 85°C
W9812G2GH-75 133MHz/CL3 2mA 0°C ~ 70°C
W9812G2GH
Publication Release Date:May 19, 2008
- 4 - Revision A09
4. PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
78
79
80
81
82
83
84
85
86
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
A11
BS0
BS1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
W9812G2GH
Publication Release Date:May 19, 2008
- 5 - Revision A09
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION DESCRIPTION
25-27, 60-66, 24,21 A0−A11 Address
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
22,23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2,4,5,7,8,10,11,13,74,
76,77,79,80,82,83,85,
31,33,34,36,37,39,40,
42,45,47,48,50,51,53,
54,56
DQ0−DQ31 Data Input/
Output Multiplexed pins for data output and input.
20 CS Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
19 RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock, RAS , CAS and WE define the operation to be
executed.
18 CAS
Column
Address Strobe Referred to RAS
17 WE Write Enable Referred to RAS
16,71,28,59 DQM0~3
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
68 CLK Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
67 CKE Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
1,15,29,43 VDD Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
44,58,72,86 VSS Ground Ground for input buffers and logic circuit inside DRAM.
3,9,35,41,49,55,75,81 VDDQ Power (+3.3V)
for I/O buffer
Separated power from VDD, to improve DQ noise
immunity.
6,12,32,38,46,52,78,
84 VSSQ Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
14,30,57,69,70,73 NC No Connection No connection
W9812G2GH
Publication Release Date:May 19, 2008
- 6 - Revision A09
6. BLOCK DIAGRAM
DQ0
DQ31
DQMn
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
A11
BS0
BS1
.
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
AND
EMRS
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA
CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE: The cell array configuration is 4096 * 256 * 32
DMn
ROW DECODER ROW DECODER
ROW DECODERROW DECODER
W9812G2GH
Publication Release Date:May 19, 2008
- 7 - Revision A09
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD +0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required
followed by a precharge of all banks using the precharge command. To prevent data contention on the
DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required
before or after programming the Mode Register to ensure proper subsequent operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max).
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among
W9812G2GH
Publication Release Date:May 19, 2008
- 8 - Revision A09
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
7.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
7.6 Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
W9812G2GH
Publication Release Date:May 19, 2008
- 9 - Revision A09
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full page.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency
in a burst read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page
burst write operation, then any residual data from the burst write cycle will be ignored.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1 A8 A7 A6 A5 A4 A3 A2 A1
A
0
Data 2 A8 A7 A6 A5 A4 A3 A2
A
1 A0 BL = 4
Data 3 A8 A7 A6 A5 A4 A3 A2
A
1
A
0
Data 4 A8 A7 A6 A5 A4 A3
A
2 A1 A0 BL = 8
Data 5 A8 A7 A6 A5 A4 A3
A
2 A1
A
0
Data 6 A8 A7 A6 A5 A4 A3
A
2
A
1 A0
Data 7 A8 A7 A6 A5 A4 A3
A
2
A
1
A
0
W9812G2GH
Publication Release Date:May 19, 2008
- 10 - Revision A09
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a
read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation
two clocks delay from the last burst write cycle. This delay is referred to as Write tWR. The bank
undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0 and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode. The period between the Auto Refresh command and the next
command is specified by tRC.
W9812G2GH
Publication Release Date:May 19, 2008
- 11 - Revision A09
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS , and WE signals become don’t
cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W9812G2GH
Publication Release Date:May 19, 2008
- 12 - Revision A09
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND DEVICE
STATE CKEn-1 CKEn DQM BS0, 1 A10 A0−A9
A11 CS
RAS
CAS
WE
Bank Active Idle H x x v v v L L H H
Bank Precharge Any H x x v L x L L H L
Precharge All Any H x x x H x L L H L
Write Active
(3) H x x v L v L H L L
Write with Auto-precharge Active (3) H x x v H v L H L L
Read Active
(3) H x x v L v L H L H
Read with Auto-precharge Active (3) H x x v H v L H L H
Mode Register Set Idle H x x v v v L L L L
No – Operation Any H x x x x x L H H H
Burst Stop Active (4) H x x x x x L H H L
Device Deselect Any H x x x x x H x x x
Auto - Refresh Idle H H x x x x L L L H
Self - Refresh Entry Idle H L x x x x L L L H
Self Refresh Exit idle
(
S.R.
)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock suspend Mode Entry Active H L x x x x x x x x
Power Down Mode Entry Idle
Active (5)
H
H
L
L
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Clock Suspend Mode Exit Active L H x x x x x x x x
Power Down Mode Exit
Any
(power
down)
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
H
x
H
x
x
Data write/Output Enable Active H x L x x x x x x x
Data Write/Output Disable Active H x H x x x x x x x
Notes:
(1) v = valid x = Don’t care L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W9812G2GH
Publication Release Date:May 19, 2008
- 13 - Revision A09
8.1 Simplified Stated Diagram
Mode
Register
Set
IDLE CBR
Refresh
Self
Refresh
ROW
ACTIVE
Power
Down
Precharge
POWER
ON
Active
Power
Down
WRITE
WRITE
SUSPEND
WRITEA
WRITEA
SUSPEND
READ
SUSPEND
READ
READA
SUSPEND
READA
Precharge
MRS REF
ACT
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
SELF
SELF exit
CKE
CKE
Write with
Read
Write
Auto precharge
Auto precharge
Read with
Write
Write
Read
PRE(precharge termination)
PRE(precharge termination)
Read
BST
BST
PRE
Manual input
Automatic sequence
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto-precharge
READA = Read with Auto-precharge
W9812G2GH
Publication Release Date:May 19, 2008
- 14 - Revision A09
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER SYMBOL RATING UNIT NOTES
Input, Column Output Voltage VIN, VOUT -0.3~VDD+ 0.3V V 1
Power Supply Voltage VDD, VDDQ -0.3~4.6V V 1
Operating Temperature(-5/-6/-6C/-75) TOPR 0 ~ 70 °C 1
Operating Temperature (-6I) TOPR -40 ~ 85 °C 1
Storage Temperature TSTG -55 ~ 150 °C 1
Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation PD 1 W 1
Short Circuit Output Current IOUT 50 mA 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70°C for -5/-6/-6C/-75, TA = -40 to 85°C for -6I)
PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES
Power Supply Voltage (-5/-6/-75) VDD 3.0 3.3 3.6 V
Power Supply Voltage (for I/O Buffer)
(-5/-6/-75) VDDQ3.0 - 3.6 V
Power Supply Voltage (-6C) VDD 2.7 3.3 3.6 V
Power Supply Voltage (for I/O Buffer)
( -6C) VDDQ2.7 - 3.6 V
Power Supply Voltage (-6C @ tCK>10nS) VDD 2.3 2.5 2.7 V
Power Supply Voltage (for I/O Buffer)
(-6C @ tCK>10nS) VDDQ2.3 - 2.7 V
Input High Voltage VIH 2 - VDD +0.3 V 1
Input Low Voltage VIL -0.3 - +0.8 V 2
Input High Voltage
(-6C @ VDD=2.3V~2.7V) VIH 0.8* VDDQ- VDD +0.3 V 1
Input Low Voltage
(-6C @ VDD=2.3V~2.7V) VIL -0.3 - 0.2* VDDQ V 2
Output logic high voltage VOH 2.4 - - V
IOH= -2mA
Output logic low voltage VOL - - 0.4 V
IOL= 2mA
Output logic high voltage
(-6C @ VDDQ=2.3V~2.7V) VOH 2 - - V
IOH= -2mA
Output logic low voltage
(-6C @ VDDQ=2.3V~2.7V) VOL - - 0.4 V
IOL= 2mA
Input leakage current II(L) -5 - 5 µA 3
Output leakage current Io(L) -5 - 5 µA 4
W9812G2GH
Publication Release Date:May 19, 2008
- 15 - Revision A09
Note:
1. VIH (max.) = VDD/VDDQ+1.2V for pulse width < 5 nS.
2. VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS.
3. Any input 0V<VIN<VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Output disabled, 0V ≤ VOUT ≤ VDDQ
9.3 Capacitance
(VDD =3.3V±0.3V for -5/-6/-6I/-75, VDD=2.7V-3.6V for -6C, TA = 25 °C, f = 1 MHz)
PARAMETER SYM. MIN. MAX. UNIT
Input Capacitance
(A0 to A10, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) CI 3.8 pf
Input Capacitance (CLK) CCLK 3.5 pf
Input/Output capacitance (DQ0−DQ31) CIO 4 6.5 pf
Note: These parameters are periodically sampled and not 100% tested.
9.4 DC Characteristics
(VDD = 3.3V±0.3V for -5/-6/-75, VDD=2.7V-3.6V for -6C, on TA = 0°~70°C, VDD = 3.3V±0.3V for -6I on TA = -40°~85°C)
MAX.
PARAMETER SYM. -5 -6/-6C/-6I -75
UNIT NOTES
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst operation
1 Bank Operation
IDD1 150 130 110 3
Standby Current
tCK = min., CS = VIH
VIH/L = VIH (min.)/VIL (max.)
CKE = VIH IDD2 55 45 35 3
Bank: Inactive State CKE = VIL
(Power Down mode) IDD2P 2 2 2 3
Standby Current
CLK = VIL, CS = VIH
VIH/L=VIH (min.)/VIL (max.)
CKE = VIH IDD2S 15 15 15
Bank: Inactive State CKE = VIL
(Power Down mode) IDD2PS 2 2 2 mA
No Operating Current
tCK = min., CS = VIH (min.) CKE = VIH IDD3 75 70 65
Bank: Active State (4 Banks) CKE = VIL
(Power Down mode) IDD3P 15 15 15
Burst Operating Current
(tCK = min.)
Read/Write command cycling
IDD4 220 200 180 3, 4
Auto Refresh Current
(tCK = min.)
Auto refresh command cycling
IDD5 250 230 210 3
Self Refresh Current
Self refresh mode
(CKE = 0.2V)
IDD6 2 2 2
W9812G2GH
Publication Release Date:May 19, 2008
- 16 - Revision A09
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V± 0.3V, TA = 0 to 70°C for -5/-6/-75, VDD=2.7V-3.6V for -6C, TA = 0 to 70°C, VDD = 3.3V± 0.3V, TA = -40 to 85°C
for -6I) (Notes: 5, 6, 7, 8, 9, 10)
-5 -6 -6C/-6I -75
PARAMETER SYM. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT
N
OTE
S
Ref/Active to Ref/Active Command
Period tRC 55 60 60 65
Active to precharge Command Period tRAS 40 100000 42 100000 42 100000 45 100000 nS
Active to Read/Write Command Delay
Time tRCD 15 18 18 20
Read/Write(a) to Read/Write(b)
Command Period tCCD 1 1 1 1 tCK
Precharge to Active Command Period tRP 15 18 18 20
Active(a) to Active(b) Command
Period tRRD 10 12 12 15 nS
CL* = 2 2 2 -- 2
Write Recovery
Time CL* = 3
tWR 2 2 2 2
tCK
CL* = 2 10 1000 10 1000 10 1000 10 1000
CL* = 3 5 1000 6 1000 6 1000 7.5 1000
CLK Cycle Time CL* = 3
(VDD=2.3V~2.7V)
tCK
-- -- -- -- 10 1000 -- --
CLK High Level width tCH 2 2 2 2.5 8
CLK Low Level width tCL 2 2 2 2.5 8
CL* = 2 6 6 6 6 Access Time
from CLK CL* = 3 tAC 4.5 5 5 5.4 9
Output Data Hold Time tOH 3 3 3 3 9
CL* = 2 6 6 6 6 Output Data
High Impedance
Time CL* = 3 tHZ 4.5 5 5 5.4 7
Output Data Low Impedance Time tLZ 0 0 0 0 9
Power Down Mode Entry Time tSB 0 5 0 6 0 6 0 7.5 nS
Transition Time of CLK (Rise and Fall) tT 1 1 1 1
Data-in Set-up Time tDS 1.5 1.5 1.5 1.5 8
Data-in Hold Time 1.0 1.0 0.8 1.0 8
Data-in Hold Time (VDD=2.3V~2.7V) tDH -- -- 1.0 --
Address Set-up Time tAS 1.5 1.5 1.5 1.5 8
Address Hold Time 1.0 1.0 0.8 1.0 8
Address Hold Time (VDD=2.3V~2.7V) tAH -- -- 1.0 --
CKE Set-up Time tCKS 1.5 1.5 1.5 1.5 8
CKE Hold Time 1.0 1.0 0.8 1.0 8
CKE Hold Time (VDD=2.3V~2.7V) tCKH -- -- 1.0 --
Command Set-up Time tCMS 1.5 1.5 1.5 1.5 8
Command Hold Time 1.0 1.0 0.8 1.0 8
Command Hold Time
(VDD=2.3V~2.7V)
tCMH -- -- 1.0 --
Refresh Time tREF 64 64 64 64 mS
Mode register Set Cycle Time tRSC 10 12 12 15 nS
Exit self refresh to ACTIVE command tXSR 70 72 72 75 nS
*CL = CAS Latency
W9812G2GH
Publication Release Date:May 19, 2008
- 17 - Revision A09
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS
‧2.7V~3.6V power supply for -6C speed grades.
‧2.3V~2.7V, @ tCK >10nS power supply for -6C speed grades.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC Testing Conditions
PARAMETER CONDITIONS
Output Reference Level 1.4V
Output Reference Level (-6C, VDD/VDDQ=2.3V~2.7V) 1.2V
Output Load See diagram below
Transition Time (tT: tr/tf) of Input Signal 1/1 nS
Input Reference Level 1.4V
Input Reference Level (-6C, VDD/VDDQ=2.3V~2.7V) 1.2V
50 ohms
AC TEST LOAD (1)
Z = 50 ohmsoutput
30pF
1.4V
50 ohms
AC TEST LOAD (2)
Z = 50 ohmsoutput
30pF
1.2V
(-6C, VDD/VDDQ=2.3V～2.7V)
W9812G2GH
Publication Release Date:May 19, 2008
- 18 - Revision A09
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
8. Assumed input rise and fall time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
(The tT maximum can’t be more than 10nS for low frequency application.)
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
W9812G2GH
Publication Release Date:May 19, 2008
- 19 - Revision A09
10. TIMING WAVEFORMS
10.1 Command Input Timing
CLK
A0-A11
BS0, 1
V
IH
V
IL
t
CMH
t
CMS
t
CH
t
CL
t
T
t
T
t
CKS
t
CKH
t
CKH
t
CKS
t
CKS
t
CKH
CS
RAS
CAS
WE
CKE
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
t
CK
W9812G2GH
Publication Release Date:May 19, 2008
- 20 - Revision A09
10.2 Read Timing
Read CAS Latency
t
AC
t
LZ
t
AC
t
OH
t
HZ
t
OH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
DQ
Valid
Data-Out
Valid
Data-Out
W9812G2GH
Publication Release Date:May 19, 2008
- 21 - Revision A09
10.3 Control Timing of Input/Output Data
t
CMH
t
CMS
t
CMH
t
CMS
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CKH
t
CKS
t
CKH
t
CKS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DS
t
DS
t
DH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
t
CMH
t
CMS
t
CMH
t
CMS
t
OH
t
AC
t
OH
t
AC
t
OH
t
HZ
t
LZ
t
AC
t
OH
t
AC
t
CKH
t
CKS
t
CKH
t
CKS
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
t
OH
t
AC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0 -31
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0 -31
CLK
Control Timing of Input Data
Control Timing of Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0 -31
CKE
CLK
DQ0 -31 OPEN
W9812G2GH
Publication Release Date:May 19, 2008
- 22 - Revision A09
10.4 Mode Register Set Cycle
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8 Reserved
A0
A7
A0A9 A0
Write Mode
A10
A0A11
BS0
"0"
"0"
A0
A3 A0
Addressing Mode
A00 A0Sequential
A01 A0Interleave
A0A9 Single Write Mode
A00 A0Burst read and Burst write
A01 A0Burst read and single write
A0
A0A2 A1 A0
A00 0 0
A0
0 0 1
A00 1 0
A00 1 1
A01 0 0
A0
1 0 1
A0
1 1 0
A01 1 1
A0Burst Length
A0Sequential A0Interleave
1 A01
A0
2A0
2
A04 A04
A08 A08
A0
Reserved A0
Reserved
A0Full Page
A0CAS Latency
A0Reserved
A0Reserved
2
A03
Reserved
A0A6 A5 A4
A00 0 0
A0
0 1 0
A00 1 1
A01 0 0
A00 0 1
t
RSC
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
AS
t
AH
CLK
CS
RAS
CAS
WE
A0-A11
BS0,1
Register
set data
next
command
A0
Reserved
"0"
"0"
BS1
"0"
"0"
W9812G2GH
Publication Release Date:May 19, 2008
- 23 - Revision A09
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RP
t
RAS
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active Read
Active Read
Active
Active
Active
Read
Read
Precharge
Precharge
Precharge
RAa RBb RAc RBd RAe
RAa CAw RBb CBx RAc CAy RBd CBz RAe
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G2GH
Publication Release Date:May 19, 2008
- 24 - Revision A09
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RCD
t
AC
t
AC
t
AC
t
AC
t
RRD
t
RRD
t
RRD
t
RRD
Active Read
Active Read
Active
Active
Active
Read
Read
t
RC
RAa RBb RAc RBd RAe
DQ
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
AP* AP*
RAa CAw RBb CBx RAc CAy RBd RAe
CBz
W9812G2GH
Publication Release Date:May 19, 2008
- 25 - Revision A09
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active Read
Precharge Active Read
Precharge Active
t
AC
t
AC
Read
Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G2GH
Publication Release Date:May 19, 2008
- 26 - Revision A09
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
A0-A9,
A11
Bank #0
Idle
Bank #1
Bank #2
Bank #3
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0
RAa
RAa
CAx
RBb
RBb CBy
RAc
RAc CAz
* AP is the internal precharge start timing
Active Read
Active
Active Read
t
CAC
t
CAC
t
CAC
CLK
DQ
CKE
DQM
A10
WE
CAS
RAS
CS
Read
AP*
AP*
BS1
BS0
t
RAS
t
RP
W9812G2GH
Publication Release Date:May 19, 2008
- 27 - Revision A09
11.5 Interleaved Bank Write (Burst Length = 8)
01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
Write
Precharge
Active
Active Write
Precharge
Active Write
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Idle
Bank #0
Bank #1
Bank #2
Bank #3
t
RAS
W9812G2GH
Publication Release Date:May 19, 2008
- 28 - Revision A09
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RC
t
RAS
t
RP
t
RAS
t
RCD
t
RCD
t
RCD
t
RRD
t
RRD
RAa
RAa CAx
RBb
RBb CBy
RAb
RAc
ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2
CAz
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active Write Write
Active
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
Active Write AP*
W9812G2GH
Publication Release Date:May 19, 2008
- 29 - Revision A09
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
CCD
t
CCD
t
CCD
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
RRD
RAa
RAa CAI
RBb
RBb CBx CAy CAm CBz
a0 a1 a2 a3 bx0 bx1 Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3
* AP is the internal precharge start timing
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active Read
Active Read
Read Read
Read
Precharge
t
AC
t
AC
t
AC
t
AC
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
AP*
W9812G2GH
Publication Release Date:May 19, 2008
- 30 - Revision A09
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
0123456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
t
RAS
t
RP
t
RCD
t
WR
RAa
RAa CAx CAy
ax0 ax1 ax2 ax3 ax4 ax5 ay1
ay0 ay2 ay4
ay3
QQ Q Q Q Q DDD
D
D
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0
WE
CAS
RAS
CS
BS1
Active Read Write Precharge
t
AC
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G2GH
Publication Release Date:May 19, 2008
- 31 - Revision A09
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
t
RCD
t
RCD
t
AC
Active Read AP* Active Read
RAa RAb
RAa CAw RAb CAx
aw0 aw1 aw2 aw3
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
t
AC
AP*
bx0 bx1 bx2 bx3
W9812G2GH
Publication Release Date:May 19, 2008
- 32 - Revision A09
11.10 Auto-precharge Write (Burst Length = 4)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS1
WE
CAS
RAS
CS
BS0
t
RC
t
RC
t
RAS
t
RP
t
RAS
t
RP
RAa
t
RCD
t
RCD
RAb RAc
RAa CAw RAb CAx RAc
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
Active
Active Write AP* Active Write AP*
* AP is the internal precharge start timing
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G2GH
Publication Release Date:May 19, 2008
- 33 - Revision A09
11.11 Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
All Banks
Prechage
Auto
Refresh Auto Refresh (Arbitrary Cycle)
t
RC
t
RP
t
RC
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
WE
CAS
RAS
CS
BS0,1
W9812G2GH
Publication Release Date:May 19, 2008
- 34 - Revision A09
11.12 Self Refresh Cycle
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
(CLK = 100 MHz)
CLK
DQ
CKE
DQM
A0-A9,
A11
A10
BS0,1
WE
CAS
RAS
CS
tCKS
tSB tCKS tCKS
All Banks
Precharge Self Refresh
Entry
Arbitrary Cycle
tRP
Self Refresh Cycle
tXSR
No Operation / Command Inhibit
Self Refresh
Exit
W9812G2GH
Publication Release Date:May 19, 2008
- 35 - Revision A09
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BS0
BS1
A10
A0-A9,
A11
DQM
CKE
DQ
t
RCD
RBa
RBa
CBv CBw CBx CBy CBz
av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3
QQ Q Q D DD QQQQ
t
AC
t
AC
Read Read
Single WriteActive
Bank #0
Idle
Bank #1
Bank #2
Bank #3
W9812G2GH
Publication Release Date:May 19, 2008
- 36 - Revision A09
11.14 Power Down Mode
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
RAa CAa RAa CAx
RAa RAa
ax0 ax1 ax2 ax3
tSB
tCKS tCKS tCKS
tSB
tCKS
Active Standby
Power Down mode
Precharge Standby
Power Down mode
Active NOP Precharge NOP Active
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
CLK
DQ
CKE
DQM
A0-A9
A11
A10
BS
WE
CAS
RAS
CS
Read
W9812G2GH
Publication Release Date:May 19, 2008
- 37 - Revision A09
11.15 Auto-precharge Timing (Read Cycle)
Read AP
0 1110987654321
Q0
Q0
Read AP Act
Q1
Read AP Act
Q1 Q2
AP ActRead
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
t
RP
Q0
Read AP Act
Q0
Read AP Act
Q1
Q0
Read AP Act
Q1 Q2 Q3
Read AP Act
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(2) CAS Latency=3
t
RP
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W9812G2GH
Publication Release Date:May 19, 2008
- 38 - Revision A09
11.16 Auto-precharge Timing (Write Cycle)
Act
01 32
(1) CAS Latency = 2
(a) burst length = 1
DQ
45 76891110
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command
tRP
D1
(d) burst length = 8
DQ
Write
D0
ActAP
Command
tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
(2) CAS Latency = 3
(a) burst length = 1
DQ
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command
tRP
D1
(d) burst length = 8
DQ
Write
D0
AP
Command
tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
tWR
tWR
tWR
tWR
tWR
tWR
tWR
tWR
12
Act
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
Act
Act
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Note )
CLK
W9812G2GH
Publication Release Date:May 19, 2008
- 39 - Revision A09
11.17 Timing Chart of Read to Write Cycle
Note: The Output data must be masked by DQM to avoid I/O conflict
1110987654321
0
(1) CAS Latency=2
In the case of Burst Length = 4
Read
Read
Write
Write
DQ
DQ
( b ) Command
DQM
DQM
D0 D1 D2 D3
D0 D1 D2 D3
( a ) Command
(2) CAS Latency=3
Read Write
Read Write
D0 D1 D2 D3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
D0 D1 D2 D3
11.18 Timing Chart of Write to Read Cycle
ReadWrite
01110987654321
Q0
Read
Q1 Q2 Q3
Read
Read
Write
Write
Q0 Q1 Q2 Q3
Write
Q0 Q1 Q2 Q3
D0 D1
DQ
DQ
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
( a ) Command
( b ) Command
DQM
DQM
In the case of Burst Length=4
(1) CAS Latency=2
(2) CAS Latency=3
D0
D0 D1
Q0 Q1 Q2 Q3D0
W9812G2GH
Publication Release Date:May 19, 2008
- 40 - Revision A09
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
Read BST
0 1110987654321
DQ
Q0 Q1 Q2 Q3
BST
( a ) CAS latency =2
Command
( b )CAS latency = 3
(1) Read cycle
Q4
(2) Write cycle
Command
Read
Command
Q0 Q1 Q2 Q3 Q4
Q0 Q1 Q2 Q3 Q4
DQ
DQ
Write BST
Note: represents the Burst stop command
BST
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
01 111098765432
(1) Read cycle
(a) CAS latency =2
Command
Q0 Q1 Q2 Q3 Q4
PRCGRead
(b) CAS latency =3
Command
Q0 Q1 Q2 Q3 Q4
PRCGRead
DQ
DQ
(2) Write cycle
(a) CAS latency =2
Command
Q0 Q1 Q2 Q3 Q4
PRCG
Write
(b) CAS latency =3
Command
Q0 Q1 Q2 Q3 Q4
Write
DQ
DQ
DQM
DQM
PRCG
tWR
tWR
W9812G2GH
Publication Release Date:May 19, 2008
- 41 - Revision A09
11.21 CKE/DQM Input Timing (Write Cycle)
7
6
5432
1
CKE MASK
( 1 )
D1 D6D5D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5432
1
( 2 )
D1 D6D5D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
76
543
2
1
( 3 )
D1 D6
D5D4D3D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK CKE MASK
CKE MASK
Internal
CLK
CLK
CLK
W9812G2GH
Publication Release Date:May 19, 2008
- 42 - Revision A09
11.22 CKE/DQM Input Timing (Read Cycle)
7
6
5432
1
( 1 )
Q1 Q6
Q4Q3Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open Open
7
6
5432
1
Q1 Q6Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
( 2 )
765432
1
Q1 Q6
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Q5
Q4
( 3 )
Q4
CLK
CLK
CLK
Q3
W9812G2GH
Publication Release Date:May 19, 2008
- 43 - Revision A09
12. PACKAGE SPECIFICATION
12.1 86L TSOP (II)-400 mil
SEATING PLANE
E
D
A2
A1
A
b
ZD
1 43
86 44
e
HE
Y
L
C
L1
q
ZD 0.61 0.024
0.002
0.007
MAX.MIN. NOM.
A2
b
A
A1
0.17
1.00
0.05
0.27
1.20
0.15
SYM.
DIMENSION
(MM)
MAX.MIN. NOM.
e0.50 0.020
0.016
L0.40 0.50 0.60 0.020 0.024
0.396
E10.06 10.16 10.26 0.400 0.404
0.871
D22.2222.12 22.62 0.875 0.905
0.039
0.011
0.047
0.006
DIMENSION
(INCH)
L1 0.80 0.032
c0.12 0.005
0.45511.7611.56 11.96 0.463 0.471
HE
Y0.10 0.004
Controlling Dimension: Millimeters
0.21 0.008
W9812G2GH
Publication Release Date:May 19, 2008
- 44 - Revision A09
13. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A01 Mar. 24, 2006 All Create new document
A02 Sep. 08, 2006 10 Exit Auto Refresh to next command is specified by tRC
A03 Sep. 27, 2006 18 Modify Characteristics Notes 8 and add Notes 9 (tT)
A04 Oct. 03, 2006 16 Add tXSR timing specification
A05 Nov. 10, 2006 3,14,15,16,17 Add -6C grade
A06 Jun. 06, 2007 3,14,15,16 Add -6I grade
A07 Aug. 13, 2007 16
Revise transient time tT AC test condition and
calculate formula for compensation consideration in
Notes 6, 8 of AC Characteristics and Operating
Condition
A08 Feb. 14, 2008 3,14,15,16,17 Add -6F grade and remove AC Testing Conditions
table in Notes 6
3,14,15,16 Add -5 grade and remove -6F grade
A09 May 19, 2008 3,14,15,16,17 Change power supply voltage -6C grade from
3.0V~3.6V to 2.7V~3.6V
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
