MC10H646, MC100H646 PECL/TTL-TTL 1:8 Clock Distribution Chip Description The MC10H/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the ON Semiconductor H646 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The single supply H646 is similar to the H643, which is a dual supply 1:8 version of the same function. The H646 was designed specifically to drive series terminated transmission lines. Special techniques were used to match the HIGH and LOW output impedances to about 7.0 W. This simplifies the choice of the termination resistor for series terminated applications. To match the HIGH and LOW output impedances, it was necessary to remove the standard IOS limiting resistor. As a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. The H646 device meets all of the requirements for driving the 60 MHz and 66 MHz Intel Pentium(R) Microprocessor. The device has no PLL components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for point-to-point clock distribution to simplify board layout and optimize signal integrity. The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to TTL loads on a daughter board. When used in conjunction with the MC10/100E111, very low skew, very wide clock trees can be designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single chip. For correct operation, the unused input pins should be left open. The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied. The output buffers of the H646 can drive two series terminated, 50 W transmission lines each. This capability allows the H646 to drive up to 16 different point-to-point clock loads. Refer to the Applications section for a more detailed discussion in this area. The 10H version is compatible with MECLTM 10H ECL logic levels. The 100H version is compatible with 100K levels. http://onsemi.com PLCC-28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxH646G AWLYYWW xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Features * * * * * * * * * * PECL/TTL-TTL Version of Popular ECLinPSTM E111 Low Skew Guaranteed Skew Spec Tri-State Enable Differential Internal Design VBB Output * Single Supply Extra TTL and ECL Power/Ground Pins Matched High and Low Output Impedance Meets Specifications Required to Drive Intel(R) Pentium(R) Microprocessors Pb-Free Packages are Available* *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 November, 2006 - Rev. 5 1 Publication Order Number: MC10H646/D Q4 OGND Q5 OVT Q6 OGND Q7 MC10H646, MC100H646 25 24 23 22 21 20 19 Table 1. PIN DESCRIPTION PIN 17 IVT Q2 28 16 IGND OVT 1 15 VCCE Q1 2 14 VCCE OGND 3 13 VBB Q0 4 12 ECLK TCLK 5 6 7 8 9 10 11 ECLK 27 VEE OGND VEE EN VEE 18 IGND 26 IVT Q3 FUNCTION OGND OVT IGND IVT VEE VCCE ECLK, ECLK TTL Output Ground (0 V) TTL Output VCC (+5.0 V) Internal TTL GND (0 V) Internal TTL VCC (+5.0 V) ECL VEE (0 V) ECL Ground (5.0 V) Differential Signal Input (PECL) VBB Reference Output Signal Outputs (TTL) Tri-State Enable Input (TTL) VBB Q0-Q7 EN Figure 1. Pinout: PLCC-28 (Top View) EN Q0 Q1 Table 2. TRUTH TABLE TCLK Q2 TCLK ECLK ECLK EN Q Q3 GND GND H L X L H GND GND X H L GND GND X H H H H L L H H L Z ECLK ECLK Q4 L = Low Voltage Level; H = High Voltage Level; Z = Tristate Q5 Q6 Q7 Figure 2. Logic Diagram http://onsemi.com 2 MC10H646, MC100H646 Power versus Frequency per Bit 700 IVT01 INTERNAL TTL POWER PDynamic = CL VSwing VCC PTotal = PStatic + PDynamic 600 OVT01 300pF POWER, mW 500 Q0A 200pF 400 300 100pF 200 INTERNAL TTL GROUND OGND0 100 IGND01 0 50pF No Load 0 20 40 60 80 100 120 FREQUENCY, MHz Figure 4. Power versus Frequency (Typical) Figure 3. Output Structure Table 3. 10H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%) 0C Symbol Characteristic Min Condition Typ 25C Max Min Typ 255 85C Max Min Typ Unit 175 mA IINH Input HIGH Current IIL Input LOW Current VIH Input HIGH Voltage IVT = IVO = VCCE = 5.0 V (Note 1) 3.83 4.16 3.87 4.19 3.94 4.28 V VIL Input LOW Voltage IVT = IVO = VCCE = 5.0 V (Note 1) 3.05 3.52 3.05 3.52 3.05 3.555 V VBB Output Reference Voltage IVT = IVO = VCCE = 5.0 V (Note 1) 3.62 3.73 3.65 3.75 3.69 3.81 V 0.5 175 Max 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0 V Table 4. 100H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%) 0C Symbol Characteristic Min Condition Typ 25C Max Min 255 Typ 85C Max Min Max Unit 175 mA IINH Input HIGH Current IIL Input LOW Current VIH Input HIGH Voltage IVT = IVO = VCCE = 5.0 V (Note 2) 3.835 4.12 3.835 4.12 3.835 3.835 V VIL Input LOW Voltage IVT = IVO = VCCE = 5.0 V (Note 2) 3.19 3.525 3.19 3.525 3.19 3.525 V VBB Output Reference Voltage IVT = IVO = VCCE = 5.0 V (Note 2) 3.62 3.74 3.62 3.74 3.62 3.74 V 0.5 175 Typ 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0 V http://onsemi.com 3 MC10H646, MC100H646 Table 5. DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%) 0C Symbol Characteristic 25C 85C Condition Min Max Min Max Min Max Unit VOH Output HIGH Voltage IOH = 24 mA 2.6 - - 2.6 - - 2.6 - - V VOL Output LOW Voltage IOL = 48 mA - 0.5 - 0.5 - 0.5 V IOS Output Short Circuit Current (Note 3) - - - - - - mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not include a limiting IOS resistor. Table 6. TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%) 0C Symbol Characteristic Condition Min 25C Max 2.0 Min 2.0 85C Max Min Max VIH VIL Input HIGH Voltage Input LOW Voltage IIH Input HIGH Current VIN = 2.7 V VIN = 7.0 V 20 100 20 100 20 100 mA IIL Input LOW Current VIN = 0.5 V -0.6 -0.6 -0.6 mA VOH Output HIGH Voltage IOH = -3.0 mA IOH = -24 mA VOL Output LOW Voltage IOL = 24 mA 0.5 0.5 0.5 V VIK Input Clamp Voltage IIN = -18 mA -1.2 -1.2 -1.2 V 0.8 2.5 2.0 0.8 2.5 2.0 2.0 Unit 0.8 2.5 2.0 V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 7. DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%) 0C Symbol ICCL ICCH Characteristic Power Supply Current Condition Total all OVT, IVT, and VCCE pins ICCZ Min Max 25C Typ Max 185 166 175 154 210 Min 85C Min Max Unit 185 185 mA 175 175 mA 210 210 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 4 MC10H646, MC100H646 Table 8. AC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V 5%) 0C Symbol Characteristic Condition 25C 85C Min Max Min Max Min Max Unit tPLH Propagation Delay ECLK to Q TCLK to Q 4.8 5.1 5.8 6.4 5.0 5.3 6.0 6.4 5.6 5.7 6.6 7.0 ns tPHL Propagation Delay ECLK to Q TCLK to Q 4.4 4.7 5.4 6.0 4.4 4.8 5.4 5.9 4.8 5.2 5.8 6.5 ns tSK(O) Output Skew tSK(PR) Process Skew tSK(P) Pulse Skew tr, tf Rise/Fall Time tPW Output Pulse Width tStability Clock Stability (Notes 7, 9) $75 $75 $75 ps FMAX Maximum Input Frequency (Notes 8, 9) 80 80 80 MHz Q0, Q3, Q4, Q7 Q1, Q2, Q5 Q0-Q7 (Notes 4, 9) 350 350 500 350 350 500 350 350 500 ps ECLK to Q TCLK to Q (Notes 5, 9) 1.0 1.3 1.0 1.1 1.0 1.3 ns 1.0 1.0 1.0 ns 1.5 ns DtPLH - tPHL 0.3 66 MHz @ 2.0 V 66 MHz @ 0.8 V 60 MHz @ 2.0 V 60 MHz @ 0.8 V (Notes 6, 9) 1.5 5.5 5.5 6.0 6.0 0.3 1.5 5.5 5.5 6.0 6.0 0.3 5.5 5.5 6.0 6.0 ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Output skew defined for identical output transitions. 5. Process skew is valid for VCC = 5.0 V 5%. 6. Parameters guaranteed by tSK(P) and tr, tf specification limits. 7. Clock stability is the period variation between two successive rising edges. 8. For series terminated lines. See Applications section for FMAX enhancement techniques. 9. All AC specifications tested driving 50 W series terminated transmission lines at 80 MHz. ORDERING INFORMATION Package Shipping MC10H646FN PLCC-28 37 Units / Rail MC10H646FNG PLCC-28 (Pb-Free) 37 Units / Rail MC10H646FNR2 PLCC-28 500 / Tape & Reel MC10H646FNR2G PLCC-28 (Pb-Free) 500 / Tape & Reel MC100H646FN PLCC-28 37 Units / Rail MC100H646FNG PLCC-28 (Pb-Free) 37 Units / Rail MC100H646FNR2 PLCC-28 500 / Tape & Reel MC100H646FNR2G PLCC-28 (Pb-Free) 500 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MC10H646, MC100H646 Resource Reference of Application Notes AN1405/D - ECL Clock Distribution Techniques AN1406/D - Designing with PECL (ECL at +5.0 V) AN1503/D - ECLinPSt I/O SPiCE Modeling Kit AN1504/D - Metastability and the ECLinPS Family AN1568/D - Interfacing Between LVDS and ECL AN1672/D - The ECL Translator Guide AND8001/D - Odd Number Counters Design AND8002/D - Marking and Date Codes AND8020/D - Termination of ECL Logic Devices AND8066/D - Interfacing with ECLinPS AND8090/D - AC Characteristics of ECL Devices http://onsemi.com 6 MC10H646, MC100H646 PACKAGE DIMENSIONS PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E B Y BRK -N- 0.007 (0.180) U T L-M M 0.007 (0.180) M N S T L-M S S N S D Z -M- -L- W 28 D X V 1 G1 A 0.007 (0.180) R 0.007 (0.180) C M M T L-M T L-M S S N S N S H 0.007 (0.180) N S S G J 0.004 (0.100) -T- SEATING T L-M S N T L-M S N S K PLANE F VIEW S G1 M K1 E S T L-M S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 --- http://onsemi.com 7 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 --- 0.007 (0.180) M T L-M S N S MC10H646, MC100H646 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc. Pentium is a registered trademark of Intel Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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