Virtex: Detailed Functional Description - Xilinx, Inc.

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Product Specification 1-800-255-7778 1

Architectural Description

Virtex Array

The Virtex user-programmable gate array, shown in

Figure 1, comprises two major conf igurable elements: co n-

figurable logic blocks (CLBs) and input/output blocks

(IOBs).

• CLBs provide the functi ona l elem ents for construc ting

logic

• IOBs provide the interface between the package pins

and the CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an arra y of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a V ersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the per iphery of the device. This routing

improves I/O routability and facilitates pin locking.

The Virtex architecture also includes the following circuits

that connect to the GRM.

• Dedicated bloc k memories of 4096 bits each

• Clock DLLs for clock-distribution delay compensation

and clock domain control

• 3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

V alues stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memor y cells on power-up, and can reload if

necessary to change the function of the device.

Input/Output Block

The Virtex IOB, Figure 2, features SelectIO™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

The three IOB stor age elements function either as edge- trig-

gered D-type flip-flops or as level sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). F or each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

The output buffer and all of the IOB control signals have

independent polarity controls.

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

forms of over-voltage pr ote ction ar e provide d, on e tha t per -

mits 5 V compliance, and one that does not. For 5 V compli-

ance, a Zener-like structure connected to ground turns on

when the output rises to approximately 6.5 V. When PCI

3.3 V compliance is required, a conv entional clamp diode is

connected to the output supply voltage, VCCO.

Optional pull-up and pull-down resistors and an optional

weak-keeper circu it are attac hed to each pa d. Pr ior to c on-

figuration, all pins not involved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-keeper circuits are inactive , but inputs can option-

ally be pulled up.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

level prior to configuration.

All Vir tex IOBs support IEEE 1149.1-compatible boundary

scan testing.

0Virtex™ 2.5 V

Field Programmable Gate Arrays

DS003-2 (v2.6 ) Ju ly 19, 2001 03Product Specification

Figure 1: Virtex Architecture Overview

vao_b.eps

IOBs

DLL

DLLDLL

DLL

VersaRing

CLBs

BRAMs

Virtex™ 2.5 V Field Programmable Gate Arrays R

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2 1-800-255-7778 Product Specification

Figure 2: Virtex Input/Output Block (IOB)

OBUFT

IBUF

Vref

ds022_02_091300

CLK

ICE

OCE

TCE D

CE Q

PAD

Programmable

Delay

Weak

Keeper

Table 1: Supported Select I/O Standards

I/O Standard Input Reference

Voltage (VREF)Output Source

Voltage (VCCO)Board Termination

Voltage (VTT)5V Tolerant

LVTTL 2 – 24 mA N/A 3.3 N/A Yes

LVCMOS2 N/A 2.5 N/A Yes

PCI, 5 V N/A 3.3 N/A Yes

PCI, 3.3 V N/A 3.3 N/A No

GTL 0.8 N/A 1.2 No

GTL+ 1.0 N/A 1.5 No

HSTL Class I 0.75 1.5 0.75 No

HSTL Class III 0.9 1.5 1.5 No

HSTL Class IV 0.9 1.5 1.5 No

SSTL3 Class I &II 1.5 3.3 1.5 No

SSTL2 Class I & II 1.25 2.5 1.25 No

CTT 1.5 3.3 1.5 No

AGP 1.32 3.3 N/A No

Virtex™ 2.5 V Field Programmable Gate Arrays

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Product Specification 1-800-255-7778 3

Input Path

A buffer In the Virtex I OB inp ut path routes the i nput sig nal

either directly to internal logic or through an optional input

flip-flop.

An optional delay element at the D-input of this flip-flop elim-

inates pad-to-pad hold time. The delay is matched to the

internal clock-distribution delay of the FPGA, and when

used, assures that the pad-to-pad hold time is zero.

Each input buffer can be configured to conform to any of the

low-voltage signalling standards supported. In some of

these standards the input buffer utilizes a user-supplied

thresho ld voltage, VREF. The need to sup ply VREF impos es

constraints on which s tandards can use d in clo se proximity

to each other. See I/O Banking, page 3.

There are optional pull-up and pull-down resistors at each

input for use after configuratio n. Their value is in the range

50 k

– 100 k

Output Path

The output pa th include s a 3-state o utput buffer that dr ives

the output signal onto the pad. The output signal can be

routed to the buffer directly from the internal logic or through

an optional IOB output flip-flop.

The 3-state control of the output can also be routed directly

from the internal logic or through a flip-flip that provides syn-

chronous enable and disable.

Each output driver can be individually programmed for a

wide range of low-voltage signalling standards. Each output

buffer can source up to 24 mA and sink up to 48mA. Dri ve

strength and slew rate controls minimize bus transients.

In most signalling standards, the output High voltage

depends on an externally supplied VCCO voltage. The need

to supply VCCO imposes constraints on which standards

can be used in close proximity to each other. See I/O Bank-

ing, page 3.

An optional weak-keeper circuit is connected to each out-

put. Wh en selected, the c ircuit monitors the voltage on th e

pad and weakly drives the pin High or Low to match the

input signal. If the pin is connected to a multiple-source sig-

nal, the weak keeper holds the signal in its last state if all

drivers are disabled. Maintaining a valid logic level in this

way eliminates bus chatter.

Becaus e the weak-keeper circu it uses the IO B input buffer

to monitor the input le vel, an appropriate VREF voltage must

be provided if the signalling standard requires one. The pro-

vision of this voltage must comply with the I/O banking

rules.

I/O Banking

Some of the I/O standards described above require VCCO

and/or VREF voltages. These voltages externally and con-

nected to device pins that serve groups of IOBs, called

banks. Consequently, restrictions exist about which I/O

standards can be combined within a given bank.

Eight I/O banks result from separating each edge of the

FPGA into two banks, as shown in Figure 3. Each bank has

multiple VCCO pins, all of which must be connected to the

same voltage. This voltage is determined by the output

standards in use.

Within a bank, output standards can be mixed only if they

use the same VCCO. Compatible standards are shown in

Table 2. GTL and GTL+ app ear unde r all voltages beca use

their open-drain outputs do not depend on VCCO.

Some input standards require a user-supplied threshold

voltage, VREF. In this case, certain user-I/O pins are auto-

matically configured as inputs for the VREF voltage. Approx-

imately one in six of the I/O pins in the bank assume this

role.

The VREF pins within a bank are interconnected internally

and consequently only one VREF voltage can be used within

each bank. All VREF pins in the bank, howe ver , must be con-

nected to the external voltage source f o r correct operation.

Within a bank, inputs that require VREF can be mixed with

those that do not. However, only one VREF voltage can be

used within a ba nk. Inpu t buffers that use VREF are not 5 V

tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V

tolerant.

The VCCO and VREF pins f or each bank appear in the device

Pinout tables and diagrams. The diagrams also show the

bank affiliation of each I/O.

Within a given package, the number of VREF and VCCO pins

can vary depending on the size of device. In larger devices,

Figure 3: Virtex I/O Banks

Table 2: Compatible Output Standards

VCCO Compatible Standards

3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,

GTL+

2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+

1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+

X8778_b

Bank 0

GCLK3 GCLK2

GCLK1 GCLK0

Bank 1

Bank 5 Bank 4

Virtex

Device

Bank 7Bank 6

Bank 2Bank 3

Virtex™ 2.5 V Field Programmable Gate Arrays R

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4 1-800-255-7778 Product Specification

more I/O pins convert to VREF pins. Since these are always

a superset of the VREF pins used for smaller devices, it is

possible to desi gn a PCB that pe r mit s migration to a la rger

device if necessa r y. A ll the VREF pins for the lar gest device

anticipated must be connected to the VREF voltage, and not

used for I/O.

In sm aller d evi ces, som e VCCO pin s used in larger devices

do not connect within the package. These unconnected pins

can be left unco nnected exter nally, or c an be conn ected to

the VCCO voltage to permit migration to a larger device if

necessary.

In TQ144 and PQ/HQ240 packages, all VCCO pins are

bonded together internally, and consequently the same

VCCO voltage must be connected to all of them. In the

CS144 p ackage, bank pa irs that s hare a si de are inter con-

nected internally, per mitting four choices for VCCO. In both

cases, the VREF pins remain internally connected as eight

banks, and can be used as described previously.

Configurable Logic Block

The basic building block of the Vir tex CLB is the logic cell

(LC). An LC includes a 4-input function generator, carry

logic, and a storage element. The outp ut from the function

generator in eac h LC dr i ves both the CLB outp ut and the D

input of the flip-flop. Each Virtex CLB contains four LCs,

organized in two similar slices, as shown in Figure 4.

Figure 5 shows a more detailed view of a single slice.

In addition to the four basic LCs, the Virtex CLB contains

logic that combines function generators to provide functions

of five or six inputs. Consequently, when estimating the

number of system gates provided by a given device, each

CLB counts as 4.5 LCs.

Look-Up Tables

Virtex function generators are implemented as 4-input

look-up tables (LUTs). In addition to operating as a function

generator, each LUT c an provide a 16 x 1-bit sy nchronous

RAM. Furthermore, the two LUTs within a slice can be com-

bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,

or a 16x1-bit dual-port synchronous RAM.

The Virtex LUT can also provide a 16-bit shift register that is

ideal for capturing high-speed or burst-mode data. This

mode can also be used to store data in applications such as

Digital Signal Processing.

Storage Elements

The storage ele ments in the Vir tex slice ca n be configured

either as edge-triggered D-type flip-flops or as level-sensi-

tive latches. The D inpu ts can be driven eithe r by the fun c-

tion generat ors within the slice o r directly from slice in puts,

bypassing the function generators.

In addition to Clock and Clock Enable signals, each Slice

has synchronous set and reset signals (SR and BY). SR

forces a storage element into the initialization state speci-

fied for it in th e config uration. BY forces it into the op posite

state. Alternatively, these signals can be configured to oper-

ate asynchronously. All of the control signals are indepen-

dently inver tible, and are shared by the two flip -flops withi n

the slice.

Figure 4: 2-Slice Virtex CLB

Carry &

Control Carry &

Control

Carry &

Control Carry &

Control

LUT

CINCIN

COUT COUT

YBYB

slice_b.eps

Slice 1 Slice 0

LUT

LUT D

EC Q

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 5

Additional Logic

The F5 multiple x er in each slice combines the function gen-

erator outputs. This combination provides either a functio n

generator that can implement any 5-input function, a 4:1

multiplexer, or selected functions of up to nine inputs.

Similarly, the F6 multiplex er combines the outputs of all four

function generators in the CLB by selecting one of the

F5-multiplexer outputs. This per mits the implementation of

any 6-input function, an 8:1 multiplexer, or selected func-

tions of up to 19 inputs.

Each CLB has four direct feedthrough paths, one per LC.

These paths provide extra data input lines or additional local

routing that does not consume logic resources.

Arithmetic Logic

Dedi ca te d c ar ry logi c p rovi des fast arit hm e tic c arry capabil -

ity for high-s pe ed ar ithmetic func tio ns. The Virtex CLB sup-

por ts two separate carr y chains, one per Slice. The height

of the carry chains is two bits per CLB.

The arithmetic logic includes an XOR gate that allows a

1-bit full add er to be i mplem ented within an LC. In addit ion,

a dedicated AND gate improves the efficiency of multiplier

implementation.

The dedicated carry path can also be used to cascade func-

tion generators for implementing wide logic functions.

BUFTs

Each Vir tex CLB contains two 3-state drivers (BUFTs) that

can drive on-chip busses. See Dedicated Routing, page 7.

Each Virtex BUFT has an independent 3-state control pin

and an independent input pin.

Block SelectRAM

Virtex FPGAs incorporate several large Block SelectRAM

memories. These complement the distributed LUT Selec-

tRAMs that provide shallow RAM structures implemented in

CLBs.

Block SelectRAM memory blocks are organized in columns.

All Virtex devices contain two such columns, one along

each ver ti c al ed ge. The se col um ns extend the full hei ght of

the chip. Each memory block is four CLBs high, and conse-

quently, a V ir tex dev ice 64 CLBs high contains 16 memor y

blocks per column, and a total of 32 blocks.

Table 3 shows the amount of Block SelectRAM memory that

is available in each Virtex device.

Figure 5: Detailed View of VIrtex Slice

F5IN

CLK

CIN

F5 F5

viewslc4.eps

COUT

EC Q

CK WSO

WSH

BY DG

BX DI

I0 LUT

LUT

INIT

REV

Table 3: Virtex Block SelectRAM Amounts

Device # of Blocks Total Block SelectRAM Bits

XCV50 8 32,768

XCV100 10 40,960

XCV150 12 49,152

XCV200 14 57,344

XCV300 16 65,536

XCV400 20 81,920

XCV600 24 98,304

XCV800 28 114,688

XCV1000 32 131,072

Virtex™ 2.5 V Field Programmable Gate Arrays R

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6 1-800-255-7778 Product Specification

Each Block SelectRAM cell, as illustrated in Figure 6, is a

fully synchronous dual-por ted 4096-bit RAM with indepen-

dent control signals for each port. The data widths of the

two ports can be configured independently, providing

built-in bus-width conversion.

Table 4 shows the depth and width aspect ratios for the

Block SelectRAM.

The Virtex Block SelectRAM also includes dedicated rout-

ing to provide an efficient interface with both CLBs and

other Block SelectRAMs.

Programmable Routing Matrix

It is the longest delay path that limits the speed of any

worst-case design. Consequently, the Virtex routing archi-

tecture and its place-and-route software were defined in a

single optimization process. This joint optimization mini-

mizes long-path delays, and consequently, yields the best

system performance.

The joint optimization also reduces design compilation

times b ecause the ar chitecture is software-fr iendly. Design

cycles are correspondingly reduced due to shorter design

iteration times.

Local Routing

The VersaBlock provides local r outi ng res our ces, as shown

in Figure 7, providing the following three types of connec-

tions.

•Interconnections among the LUTs, flip-flops, and GRM

•Internal CLB feedback paths that provide high-speed

connections to LUTs within the same CLB, chaining

them together with minimal routing delay

•Direct paths that provide high-speed connections

between horizontally adjacent CLBs, eliminating the

delay of the GRM.

Figure 6: Dual-Port Block SelectRAM

WEB

ENB

RSTB

CLKB

ADDRB[#:0]

DIB[#:0]

WEA

ENA

RSTA

CLKA

ADDRA[#:0]

DIA[#:0]

DOA[#:0]

DOB[#:0]

RAMB4_S#_S#

xcv_ds_006

Table 4: Block SelectRAM Port Aspect Ratios

Width Depth ADDR Bus Data Bus

1 4096 ADDR<11:0> DATA<0>

2 2048 ADDR<10:0> DATA<1:0>

4 1024 ADDR<9:0> DATA<3:0>

8 512 ADDR<8:0> DATA<7:0>

16 256 ADDR<7:0> DATA<15:0>

Figure 7: Virtex Local Routing

X8794b

CLB

GRM

To Adjacent

GRM To Adjacent

GRM

Direct Connection

To Adjacent

CLB

To Adjacent

GRM

To Adjacent

GRM

Direct Connection

To Adjacent

CLB

Virtex™ 2.5 V Field Programmable Gate Arrays

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Product Specification 1-800-255-7778 7

General Purpose Routing

Most Virtex signals are routed on the general purpose rout-

ing, and consequently, the majority of interconnect

resour ces are assoc iated with this level of the routi ng hier-

archy. The general routing resources are located in horizon-

tal and vertical routing channels associated with the rows

and columns CLBs. The general-purpose routing resources

are listed below.

•Adjacent to each CLB is a General Routing Matrix

(GRM). The GRM is the switch matrix through which

horizontal and vertical routing resources connect, and

is also the means by which the CLB gains access to

the general purpose routing.

•24 single-length lines route GRM signals to adjacent

GRMs in each of the four directions.

•72 buffered Hex lines route GRM signals to another

GRMs six-blocks away in each one of the four

directions. Organized in a staggered pattern, Hex lines

can be driven only at their endpoints. Hex-line signals

can be accessed either at the endpoints or at the

midpoint (three blocks from the source). One third of

the Hex lines are bidirectional, while the remaining

ones are uni-directional.

•12 Longlines are buffered, bidirectional wires that

distribute signals across the device quickly and

efficiently. Vertical Longlines span the full height of the

device, and horizontal ones span the full width of the

device.

I/O Routing

Virtex devices have additional routing resources around

their periphery that form an interface between the CLB arra y

and the IOBs. This additional routing, called the VersaRing,

facilitates pin-swapping and pin-locking, such that logic

redesi gns can adapt to existing PCB l ayouts. Time- to-mar-

ket is reduced, since PCBs and other system components

can be manufactured while the logic design is still in

progress.

Dedicated Routing

Some classes of signal require dedicated routing resources

to maximize performance. In the Virtex architecture, dedi-

cated routing resources are provided for two classes of sig-

nal.

•Horizontal routing resources are provided for on-chip

3-state busses. Four partitionable bus lines are

provided per CLB row, permitting multiple busses

within a row, as shown in Figure 8.

•Two dedicated nets per CLB propagate carry signals

vertically to the adjacent CLB.

Global Routing

Global Routing resources distribute clocks and other sig-

nals with very high fanout throughout the device. Virtex

devices include two tiers of global routing resources

ref erred to as primary global and secondary local clock rout-

ing resources.

•The primary global routing resources are four

dedicated global nets with dedicated input pins that are

designed to distribute high-fanout clock signals with

minimal skew. Each global clock net can drive all CLB,

IOB, and block RAM clock pins. The primary global

nets can only be driven by global buffers. There are

four global buffers, one for each global net.

•The secondary local clock routing resources consist of

24 backbone lines, 12 across the top of the chip and 12

across bottom. From these lines, up to 12 unique

signals per column can be distributed via the 12

longlines in the column. These secondary resources

are more fle xible than the primary resources since they

are not restricted to routing only to clock pins.

Clock Distribution

Virtex provides high-speed, low-skew clock distribution

through the primary global routing resources described

above. A typical clock distribution net is shown in Figure 9.

F our global buffers are provided, two at the top center of the

device and two at the bottom center. These drive the four

primary global nets that in turn drive any clock pin.

Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines

CLB CLB CLB CLB

buft_c.eps

Tri-State

Lines

Virtex™ 2.5 V Field Programmable Gate Arrays R

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8 1-800-255-7778 Product Specification

Four dedicated clock pads are provided, one adjacent to

each of the global buffers. The input to the global buffer is selecte d either from these pads or from sign als in the gen-

eral purpose routing.

Delay-Locked Loop (DLL)

Associated with each global clock input buffer is a fully digi-

tal Delay-Locked Loop (DLL) that can eliminate skew

between the clock input pad and internal clock-input pins

throughout the device. Each DLL can drive two global clock

network s.The DLL mo nitors the input clock and the distr ib-

uted clock, and automatically adjusts a clock dela y element.

Clock edges r each inter nal flip- flops one to four clock per i-

ods after they arrive at the input. This closed-loop system

effectively eliminates clock-distribution delay by ensuring

that clock edges arrive at internal flip-flops in synchronism

with clock edges arriving at the input.

In addition to eliminating clock-distribution delay, the DLL

provides advanced control of multiple clock domains. The

DLL provides four quadrature phases of the source clock,

can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,

5, 8, or 16.

The DLL also operates as a clock mirror. By driving the out-

put from a DLL off-chip and then back on again, the DLL can

be used to de-s kew a board l evel clock amon g multiple V ir-

tex devices.

In order to guarantee that the system clock is operating cor-

rectly prior to the FPGA st arti ng up after configuration, th e

DLL can delay the c ompletion o f the co nfiguration p roce ss

until after it has achieved lock.

See DLL Timing Parameters , page 20 of Module 3, f or fre-

quency range information.

Boundary Scan

Virtex devices support all the mandatory boundary-scan

instructions specified in the IEEE standard 1149.1. A Test

Access Port (TAP) and registers are provided that imple-

ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions. The TAP

also supports two internal scan chains and configura-

tion/readback of the device.The TAP uses dedicated pack-

age pins that always operate using LVTTL. For TDO to

operate usin g LVTTL, the VCCO for Bank 2 should be 3.3 V.

Otherwise, TDO switches rail-to-rail between ground and

VCCO.

Boundary-scan operation is independent of individual IOB

configurations, and unaffected by package type. All IOBs,

including un-bonded ones, are treated as independent

3-state bidirectional pins in a single scan chain. Retention of

the bidi re ctional tes t c ap abi li ty afte r c onfi guratio n facilit ates

the testing of external interconnections.

Table 5 lists the boundary-scan instructions supported in

Virtex FPGAs. Internal signals can be captured during

EXTEST by connecting them to un-bonded or unused IOBs.

They can als o be c onne ct ed to the unus ed outp uts of IO Bs

defined as unidirectional input pins.

Before the device is configured, all instructions except

USER1 and USER2 are available. After configuration, all

instr uction s are available. Dur ing config uration, it is recom-

mended that those operations using the boundary-scan

performed.

Figure 9: Global Clock Distribution Network

Global Clock Spine

Global Clock Column

GCLKPAD2

GCLKBUF2

GCLKPAD3

GCLKBUF3

GCLKBUF1

GCLKPAD1

GCLKBUF0

GCLKPAD0

Global Clock Rows

gclkbu_2.eps

Virtex™ 2.5 V Field Programmable Gate Arrays

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Product Specification 1-800-255-7778 9

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

Figure 10 is a diagram of the Vi rtex Series bou ndary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access P ort controller , and the Instruction

Instruction Set

The Virtex Series boundary scan instruction set also

include s ins tr ucti ons to confi gure the d evice and r ead back

configuration data (CFG_IN, CFG_OUT, and JSTAR T). The

complete instruction set is coded as shown in Table 5.

Data Registers

The primary data register is the boundary scan register. For

each IOB pi n in the FPGA, bo nded or not, it incl udes thre e

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

The FPGA supports up to two additional internal scan

chains that can be sp ecified using t he BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (TDO1

and TDO2) allow user scan data to be shifted out of TDO.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) f or each user register . There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register , while the output-only pins contributes

all three bits.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 11.

BSDL (Boundar y Scan Description Language) files for Vir-

tex Series devices are available on the Xilinx web site in the

File Download area .

Figure 10: Virtex Series Boundary Scan Logic

D Q

IOB

BYPASS

IOB IOB

TDO

TDI

IOB IOB IOB

D Q

IOB

D Q

0DQ

IOB.T

DATA IN

IOB.I

IOB.Q

IOB.T

IOB.I

SHIFT/

CAPTURE CLOCK DATA

DATAOUT UPDATE EXTEST

X9016

INSTRUCTION REGISTER

Virtex™ 2.5 V Field Programmable Gate Arrays R

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10 1-800-255-7778 Product Specification

Identification Registers

The IDCODE re gister is suppor ted. By using the IDCODE,

the device connected to the JTAG port can be determined.

The IDCODE register has the following binary format:

vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1

where

v = the die version number

f = the family code (03h for Virtex family)

a = the number of CLB rows (ranges from 0 10h for XCV5 0

to 040h for XCV1000)

c = the company code (49h for Xilinx)

The USERCODE register is supported. By using the USER-

CODE, a user-programmable identification code can be

loaded and shifted out for examination. The identification

code is embed ded in the bi tstre am dur ing bitstrea m g ener-

ation and is valid only after configuration.

Including Boundary Scan in a Design

Since the boundary scan pins are dedicated, no special ele-

ment needs to be added to the design unless an internal

data register (USER1 or USER2) is desired.

If an internal data register is used, insert the boundary scan

symbol and connect the necessary pins as appropriate.

Development System

Virtex FPGAs are suppor ted by the Xilinx Foundation and

Alliance CAE tools. The basic methodology for Virtex design

consists of three interrelated steps: design entry, imple-

mentation, and verification. Industry-standard tools are

used for design entry and simulation (for example, Synop-

sys FPGA Express), while Xilinx provides proprietary archi-

tecture-specific tools for implementation.

The Xilinx development system is integrated under the Xil-

inx Design Manager (XDM™) software, providing designers

Figure 11: Boundary Scan Bit Sequence

Table 5: Boundary Scan Instructions

Boundary-Scan

Command Binary

Code(4:0) Description

EXTEST 00000 Enab l es bou nda ry-scan

EXTEST operation

SAMPLE/PRELOAD 00001 Enab l es bou nda ry-scan

SAMPLE/PRELOAD

operation

USE R 1 00010 Acces s use r-def ine d

USE R 2 00011 Acces s use r-def ine d

CFG_OU T 00100 Acces s the con figur ati on

bus for read operations.

CFG_IN 0010 1 Access the con figur ati on

bus for write operations.

INTEST 00111 Enabl es bou nda ry-scan

INTEST operation

USERCOD E 01000 Enab l es sh ifti ng out

USE R co d e

IDCODE 01001 Enables sh ifting out of ID

Code

HIGHZ 01010 3-states output pins while

enabling the Bypass

JSTART 01100 Clock the start-up

se quence wh en

StartupClk is TCK

BYPASS 11111 Enables BYPASS

RESERVED All other

codes Xilinx reserved

instructions

Bit 0 ( TDO end)

Bit 1

Bit 2

Right half of Top-edge IOBs (Right-to-Left)

GCLK2

GCLK3

Left half of Top-edge IOBs (Right-to-Left)

Left-edge IOBs (Top-to-Bottom)

Left half of Bottom-edge IOBs (Left-to-Right)

GCLK1

GCLK0

Right half of Bottom-edge IOBs (Left-to-Right)

DONE

PROG

Right-edge IOBs (Bottom -to-Top)

CCLK

(TDI end)

990602001

Table 6: IDCODEs Assigned to Virtex FPGAs

FPGA IDCODE

XCV50 v0610093h

XCV100 v0614093h

XCV150 v0618093h

XCV200 v061C093h

XCV300 v0620093h

XCV400 v0628093h

XCV600 v0630093h

XCV800 v0638093h

XCV1000 v0640093h

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 11

with a comm on user interface regardless of their choice of

entry and verification tools. The XDM software simplifies the

selection of implementation options with pull-down menus

and on-line help.

Application programs ranging from schematic capture to

Placement and Routing (PAR) can be accessed through the

XDM so ftware. The program com mand se que nce is ge ner-

ated prior to execution, and stored for documentation.

Several advanced software f eatures facilitate Virtex design.

RPMs, for example, are schematic-based macros with rela-

tive location constraints to guide their placement. They help

ensure optimal implementation of common functions.

F or HDL design entry, the Xilinx FPGA Foundation develop-

ment system provides interfaces to the following synthesis

design environments.

•Synopsys (FPGA Compiler, FPGA Express)

•Exemplar (Spectrum)

•Synplicity (Synplify)

For schematic design entry, the Xilinx FPGA Foundation

and alliance development system provides interfaces to the

following schematic-capture design environments.

•Mentor Graphics V8 (Design Architect, QuickSim II)

•Viewlogic Systems (Viewdraw)

Third-party vendors support many other environments.

A standard interface-file specification, Electronic Design

Interchange Format (EDIF), simplifies file transfers into and

out of the development system.

Virtex FPGAs supported by a unified library of standard

functions. This library contains ov er 400 primitives and mac-

ros, ranging from 2-input AND gates to 16-bit accumulators,

and includes arithmetic functions, comparators, counters,

data registers, decoders, encoders, I/O functions, latches,

Boolean functions, multiplexers, shift registers, and barrel

shifters.

The “soft macro” portion of the library contains detailed

descriptions of common logic functions, but does not con-

tain any partitioning or placement information. The perfor-

mance of these macros depends, therefore, on the

partitioning and placement obtained during implementation.

RPMs, on the other hand, do contain predetermined par ti-

tioning and placement information that permits optimal

implementation of these functions. Users can create their

own library of soft macros or RPMs based on the macros

and primitives in the standard library.

The design environment supports hierarchical design entry,

with high-level schematics that comprise major functional

blocks, while lower-level schematics define the logic in

these blocks. These hierarchi ca l desi gn el em ents ar e au to-

matically combined by the implementation tools. Different

design entry tools can be combined within a hierarchical

design, thus allowing the most convenient entr y method to

be used for each portion of the design.

Design Implementation

The place-and-route tools (PAR) automatically provide the

implementation flow described in this section. The parti-

tioner takes the EDIF net list for the design and maps the

logic into the architectural resources of the FPGA (CLBs

and IOBs, for example). The placer then determines the

best loc ations for these blocks bas ed on their int erconnec-

tions and the de sired perfor mance. Finally, the router inter-

connects the blocks.

The PAR algorithms support fully automatic implementation

of most desig ns. For demanding app licatio ns, however, the

user can exercise various degrees of control over the pro-

cess. User partitioning, placement, and routing information

is optio nal ly s pecifi ed during the desi gn- e ntry proc es s. The

implementation of highly structured designs can benefit

greatly from basic floor planning.

The imp lementation so ftware in cor porates Timing Wizard®

timing-driv en placement and routing. Designers specify tim-

ing requirements along entire paths during design entry.

The timing path analysis routines in PAR then recognize

these user-specified requirements and accommodate them.

Timing r equirements a re entered on a schematic in a for m

directly relating to the system requirements, such as the tar-

geted clock frequency, or the maximum allowable delay

between two registers. In this way, the overall perfor mance

of the s yst em al ong e ntire sig nal p aths is auto mat ically tai-

lored to user-generated specifications. Specific timing inf or-

mation for individual nets is unnecessary.

Design Verification

In addition to conv entional software simulation, FPGA users

can use in-circuit debugging techniques. Because Xilinx

devices are infi nitel y re programma ble, designs can be veri-

fied in rea l time wi thout the n eed for extensive sets of soft-

ware simulation vectors.

The dev elopment system supports both software simulation

and in-circuit debugging techniques. For simulation, the

system extracts the post -layout timing i nfor matio n from the

design database, and back-annotates this information into

the net list for use by the simulator. Alternatively, the user

can verify timing-critical portions of the design using the

TRACE® static timing analyzer.

For in-circuit debugging, the development system includes

a download and readback cable. This cable connects the

FPGA in the target system to a PC or workstation. After

downloading the design into the FPGA, the designer can

single-step the logic, readback the contents of the flip-flops,

and so observe the internal logic state. Simple modifica-

tions can be downloaded into the system in a matter of min-

utes.

Virtex™ 2.5 V Field Programmable Gate Arrays R

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12 1-800-255-7778 Product Specification

Configuration

Vir tex devices ar e configur ed by loading configu ration data

into the internal configuration memory. Some of the pins

used for this are d edicated co nfiguration pins, whil e others

can be re-used as general purpose inputs and outputs once

configuration is complete.

The following are dedicated pins:

•Mode pins (M2, M1, M0)

•Configuration clock pin (CCLK)

•PROGRAM pin

•DONE pin

•Boundary-scan pins (TDI, TDO, TMS, TCK)

Depending on the configuration mode chosen, CCLK can

be an output generated by the FPGA, or it can be generated

externally and provided to the FPGA as an input.

Note that some configuration pins can act as outputs. For

correct operation, these pins can require a VCCO of 3.3 V to

permit LVTTL operation. All the pins aff ected are in banks 2

or 3.

After Virtex devices are configured, unused IOBs function

as 3-state OBUFTs with weak pull downs. For a more

detailed description than that given below, see the

XAPP138, Virtex Configuration and Readback.

Configuration Modes

Virte x supports the following four configuration modes.

•Slave-serial mod e

•Maste r-s er i al mod e

•SelectMAP mode

•Bound ary -sc an mod e

The Configuration mode pins (M2, M1, M0) select among

these configuration modes with the option in each case of

having the IOB pins either pulled up or left floating prior to

configuration. The selection codes are listed in Table 7.

Configuration through the boundary-scan port is always

available, independ ent o f the mode selection . Sel ec ti ng th e

boundary-scan mode simply turns off the other modes. The

three mod e pins have inter nal p ull- up resis tors, and de fault

to a logic High if left unconnected.

Slave-Serial Mode

In slave-serial mo de, the FPG A re ce ives confi gurat ion dat a

in bit-serial form from a serial PROM or other source of

serial configuration data. The serial bitstream must be setup

at the DIN input pin a short time be fore each rising edg e of

an externally generated CCLK.

F or more information on serial PROMs, see the PROM data

sheet at http://www.xilinx.com/partinfo/ds026.pdf.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the ne xt device is routed to the DOUT pin.

The data on the DOUT pin changes on the rising edge of

CCLK.

The change of DOUT on the rising edge of CCLK differs

from previous families, but does not cause a problem for

mixed configuration chains. This change was made to

improve serial configuration rates for Virtex-only chains.

Figure 12 sh o w s a fu ll ma st er /slave s yst e m. A Vi rtex de v ice

in slave-serial mode should be connected as shown in the

third device from the left.

Slave-ser ial mode is selected by applying <111> or <011>

to the mode pins (M2, M1, M0). A weak pull-up on the mode

pins makes slave-serial the default mode if the pins are left

unconnected. Figure 13 shows slave-serial configuration

timing.

Table 8 provides more detail about the characteristics

sho wn i n Figure 13. Configuration must be delayed until the

INIT pins of all daisy-chained FPGAs are High.

Table 7: C onfiguration Codes

Configuration Mode M2 M1 M0 CCLK Direction Data Width Serial Dout Configuration Pull-ups

Master-serial mode 0 0 0 Out 1 Yes No

Boundary-scan mode 1 0 1 N/A 1 No No

Selec tMA P mod e 1 1 0 In 8 No No

Slave-serial mode 1 1 1 In 1 Yes No

Master-serial mode 1 0 0 Out 1 Yes Yes

Boundary-scan mode 0 0 1 N/A 1 No Yes

Selec tMA P mod e 0 1 0 In 8 No Yes

Slave-serial mode 0 1 1 In 1 Yes Yes

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 13

Table 8: Master/Slave Serial Mode Programming Switching

Description Figure

References Symbol Values Units

CCLK

DIN setup/hold, slave mode 1/2 TDCC/TCCD 5.0 / 0 ns, min

DIN setup/hold, master mode 1/2 TDSCK/TCKDS 5.0 / 0 ns, min

DOUT 3 TCCO 12.0 ns, max

High time 4 TCCH 5.0 ns, min

Low time 5 TCCL 5.0 ns, min

Maximum Frequency FCC 66 MHz, max

Frequency Tolerance, master mode with

respect to nominal +45%

–30%

Figure 12: Master/Slave Serial Mode Circuit Diagram

VIRTEX

MASTER

SERIAL VIRTEX,

XC4000XL,

SLAVE

XC1701L

PROGRAM

M2M0 M1

DOUT

CCLK CLK

DATA

CE CEO

RESET/OE DONE

DIN

INIT INIT

DONE

PROGRAM PROGRAM

CCLK

DIN DOUT

M0 M1

(Low Reset Option Used)

4.7 K

xcv_12_091499

3.3V VCC

Optional Pull-up

Resistor on Done

Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to the common DONE line.

Figure 13: Slave-Serial Mode Programming Switching Characteristics

4TCCH

3TCCO

5TCCL

2TCCD

1TDCC

DIN

CCLK

DOUT

(Output)

X5379_a

Virtex™ 2.5 V Field Programmable Gate Arrays R

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14 1-800-255-7778 Product Specification

Master-Serial Mode

In master-serial mode, the CCLK output of the FPGA drives

a Xilinx Serial PROM that feeds bit-serial data to the DIN

input. The FPGA accepts this data on each rising CCLK

edge. After the FPGA has been loaded, the data f or the next

device in a daisy- chain i s prese nted on the DOUT pin af ter

the rising CCLK edge.

The interface is identical to slave-serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a slow default frequency. Con-

figuration bits then switch CCLK to a higher frequency for

the remainder of the configuration. Switching to a lower fre-

quency is prohibited.

The CCLK frequ ency is set using the ConfigRate option in

the bitstream generation software. The maximum CCLK fre-

quency that can be selected is 60 MHz. When selecting a

CCLK frequency, ensure that the serial PROM and any

daisy-c hained FPGA s are fast enough t o support the c lock

rate.

On power-up, the CCLK frequency is 2.5 MHz. This fre-

quency is used until the Confi gRate bits have been loade d

when the frequency changes to the selected ConfigRate.

Unless a different frequency is specified in the design, the

default ConfigRate is 4 MHz.

Figure 12 shows a full master/slave system. In this system,

the left-most device operates in master-serial mode. The

remaining devices operate in slave-serial mode. The

SPROM RESET pin is driven by INIT, and the CE input is

driv en by DONE. There is the potential f or contention on the

DONE pin, depending on the start-up sequence options

chosen.

Figure 14 shows the timing of master-serial configuration.

Master-serial mode is selected by a <000> or <100> on the

mode pins (M2, M1, M0). Table 8 show s t h e ti mi ng i nforma-

tion for Figure 14.

At power-up, VCC must rise from 1.0V to VCC min in less

than 50 ms, otherwise delay configuration by pulling

PROGRAM Low until VCC is valid.

The sequence of operations necessary to configure a Virtex

FPGA serially appears in Figure 15.

SelectMAP Mode

The SelectMAP mode is the fastest configuration option.

Byte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data.

An external data source provides a byte stream, CCLK, a

Chip Select (CS) signal and a Write signal (WRITE). If

BUSY is asserted (High) by the FPGA, the data must be

held until BUSY goes Low.

Data can also be read using the SelectMAP mode. If

WRITE is not asserted, configuration data is read out of the

FPGA as part of a readback operation.

In the SelectMAP mode, multiple Virtex devices can be

chained in parallel. DATA pins (D7:D0), CCLK, WRITE,

BUSY, PROGRAM, DONE, and INIT can be connected in

parallel betwe en all the FPGAs. Note tha t the data is orga-

nized with the MS B of e ac h byte o n p in DO a nd the LS B o f

each byte on D7. The CS pins are kept separate, insuring

that each FPGA can be selected individually. WRITE should

be Low before loading the firs t bi tstre am an d re turne d Hig h

after the last device has been programmed. Use CS to

select the appropriate FPGA for loading the bitstream and

sending the configuration data. at the end of the bitstream,

deselect the loaded de vice and select the next target FPGA

by setting its CS pi n Hi gh. A free -r u nni ng o scil la tor or ot her

externally generated signal can be used for CCLK. The

BUSY signal can be ignored for frequencies below 50 MHz.

For details about frequencies above 50 MHz, see

XAPP138, Virtex Configuration and Readback. Once all the

devices have been programmed, the DONE pin goes High.

Figure 14: Master-Serial Mode Programming Switching Characteristics

Serial Data In

CCLK

(Output)

Serial DOUT

(Output)

1TDSCK

TCKDS

DS022_44_071201

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 15

After configuration, the pins of the SelectMAP por t can be

used as additional user I/O. Alternatively, the port can be

retained to permit high-speed 8-bit readback.

Retention of the SelectMAP port is selectable on a

design-by-de sign basis when the bitstr eam is generated. If

retentio n is s el ec ted, PROHIBIT co n straint s a re r equir ed t o

prevent the SelectMAP-port pins from being used as user

I/O.

Multiple Vir tex FPGAs can be confi gured using the Select-

MAP mode, and be made to start-up simultaneously. To

configure multiple devices in this way, wire the individual

CCLK, Data, WRITE, and BUSY pins of all the devices in

parallel. The individual devices are loaded separately by

asser tin g the CS pin o f each device in tur n and w riting the

appropriate data. See Table 9 for SelectMAP Write Timing

Characteristics.

Write

Write operations send packets of configuration data into the

FPGA. The sequence of operations for a multi-cycle write

operation is s hown below. Not e that a configuratio n packet

can be split into many such sequences. The packet does

not have to comp lete with in one as s ertion of CS, illustrated

in Figure 16.

1. Assert WRITE and CS Low. Note that when CS is

asserted on successive CCLKs, WRITE must remain

either asserted or de-asserted. Otherwise an abort will

be initiated, as described below.

2. Drive data onto D[7:0]. Note that to avoid contention,

the data source should not be enabled while CS is Lo w

and WRITE is High. Similarly, while WRITE is High, no

more that one CS should be asserted.

Figure 15: Serial Configuration Flowchart

Apply Power

Set PROGRAM = High

Release INIT If used to dela y

configuration

Load a Configuration Bit

High

Low

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

ds003_154_111799

Configuration Completed

End of

Bitstream?

Yes

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on err or.

If no CRC error s f ound,

FPGA enters start-up phase

causing DONE to go High.

INIT?

Table 9: SelectMAP Write Timing Characteristics

Description Symbol Units

CCLK

D0-7 Setup/Hold 1/2 TSMDCC/TSMCCD 5.0 / 1.7 ns, min

CS Setup/H o ld 3/4 TSMCSCC/TSMCCCS 7.0 / 1.7 ns, min

WRITE Setup/Hold 5/6 TSMCCW/TSMWCC 7.0 / 1.7 ns, min

BUSY Propagation Delay 7 TSMCKBY 12.0 ns, max

Maximum Frequency FCC 66 MHz, max

Maximum Frequency with no handshake FCCNH 50 MHz, max

Virtex™ 2.5 V Field Programmable Gate Arrays R

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16 1-800-255-7778 Product Specification

3. At the rising edge of CCLK: If BUSY is Low, the data is

accepted on this clock. If BUSY is High (from a previous

write), the data is not accepted. Acceptance will instead

occur on the first clock after BUSY goes Low, and the

data must be held until this has happened.

4. Repeat steps 2 and 3 until all the data has been sent.

5. De-assert CS and WRITE.

A flowchart for the write operation appears in Figure 17.

Note that if CCLK is slower than fCCNH, the FPGA never

asserts BUSY. In this case, the above handshake is unnec-

essary, and data can simply be entered into the FPGA e very

CCLK cycle.

Figure 16: Write Operations

ds003_16_102199

CCLK

Write Write No Write Write

DATA[7:0]

WRITE

BUSY

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 17

Abort

During a given assertion of CS, the user cannot switch from

a wr ite to a re ad, or vi ce -versa. Th is a ction c aus es th e c ur -

rent packet command to be aborted. The device will remain

BUSY until the aborted operation has completed. Following

an abor t, data is assumed to be unaligned to word bound-

aries, and the FPGA requires a new synchronization word

prior to accepting any new packets.

To initiate an abort during a write operation, de-assert

WRITE. At the rising edge of CCLK, an abort is initiated, as

shown in Figure 18.

Figure 17: SelectMAP Flowchart for Write Operation

Apply Power

Set PROGRAM = High

Release INIT If used to dela y

configuration

On first FPGA

Set WRITE = Low

Enter Data Source

Set CS = Low

On first FPGA

Set CS = High

Apply Configuration Byte

INIT?

High

Low

Busy?

Low

High

Disable Data Source

Set WRITE = High

When all DONE pins

are released, DONE goes High

and start-up sequences complete.

If no error s,

later FPGAs enter start-up phase

releasing DONE.

If no error s,

first FPGAs enter start-up phase

releasing DONE.

Once per bitstream,

FPGA checks data using CRC

and pulls INIT Low on err or.

FPGA makes a final

clearing pass and releases

INIT when finished.

FPGA starts to clear

configuration memory.

For any other FPGAs

ds003_17_111799

Repeat Sequence A

Configuration Completed

Sequence A

End of Data?

Yes

Virtex™ 2.5 V Field Programmable Gate Arrays R

Module 2 of 4 www.xilinx.com DS003-2 (v2.6) July 19, 2001

18 1-800-255-7778 Product Specification

Boundary-Scan Mode

In the boundary-scan mode, no non-dedicated pins are

required, configuration being done entirely through the

IEEE 1149.1 Test Access Port.

Configuration through the TAP uses the CFG_IN instruc-

tion. This instruction allows data input on TDI to be con-

verted into data packets for the internal configuration bus.

The following steps are required to configure the FPGA

through the boundary-scan port (when using TCK as a

start-up clock).

1. Load the CFG_IN instruction into the boundary-scan

instruction register (IR)

2. Enter the Shift-DR (SDR) state

3. Shift a configuration bitstream into TDI

4. Return to Run-Test-Idle (RTI)

5. Load the JSTART instruction into IR

6. Enter the SDR state

7. Clock TCK through the startup sequence

8. Return to RTI

Configuration and readback via the TAP is always availab le.

The boundary-scan mode is selected by a <101> or 001>

on the mode pins (M2, M1, M0).

Configuration Sequence

The configuration of Virtex devices is a three-phase pro-

cess. Firs t, the configurati on mem ory is cl ea re d. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process.

Configuration is aut omatically initiated on power-up unless

it is delay ed by the user, as described below. The configura-

tion process can also be initiated by asserting PROGRAM.

The end of t he memory-cle ar ing pha se is signa lled by INIT

going High , an d the compl eti on o f the enti r e proc es s is si g-

nalled by DONE going High.

The power-up timing of configuration signals is shown in

Figure 19. The corresponding timing characteristics are

listed in Table 10. .

Delaying Configuration

INIT can be held Low using an open-drain driver. An

open-drain is required since INIT is a bidirectional

open-drain pi n tha t is held Low by the FPGA whi le the c on-

figuration memory is being cleared. Extending the time that

the pin is Low causes the con figuration sequencer to wait.

Thus, configuration is delayed by preventing entry into the

phase where data is loaded.

Start-Up Sequence

The default Start-up sequence is that one CCLK cycle after

DONE goes High, the global 3-state signal (GTS ) is released.

This permits device outputs to turn on as necessary.

One CCLK cycle later , the Global Set/Reset (GSR) and Glo-

bal Wr ite Enable (GW E) si gnals ar e re lease d. This per mits

the internal storage elements to begin changing state in

response to the logi c and the us er clock.

The relative timing of these ev ents can be changed. In addi-

tion, the GTS, GSR, and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start in synchronism. The sequence

can also be paused at any stage until lock has been

achieved on any or all DLLs.

Figure 18: SelectMAP Write Abort Waveforms

X8797_c

CCLK

WRITE

Abort

DATA[7:0]

BUSY

Figure 19: Power-Up Timing Configuration Signals

Table 10: Power-up Timing Ch aracteristics

Description Symbol Value Units

Power-on Reset TPOR 2.0 ms, max

Program Latency TPL 100.0

s, max

CCLK (output) Delay TICCK 0.5

s, min

4.0

s, max

Program Pulse Width TPROGRAM 300 ns, min

VALID

PROGRAM

Vcc

CCLK OUTPUT or INPUT

ICCK

98122302

POR

INIT

M0, M1, M2

(Required)

Virtex™ 2.5 V Field Programmable Gate Arrays

DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4

Product Specification 1-800-255-7778 19

Data Stream Format

Virtex devices are configured by sequentially loading

frames of data. Table 11 lists the total number of bits

required t o configure each device. For more detailed infor-

mation, see application note XAPP151 “Virtex Configura-

tion Architecture Advanced Users Guide”.

Readback

The configuration data stored in the Virtex configuration

memory can be readback for verification. Along with the

configuration data it is possible to readback the contents all

flip-flops/latches, LUTRAMs, and block RAMs. This capabil-

ity is used for real-time debugging.

For more detailed information, see application note

XAPP138, Vir tex FPGA Series Configuration and Read-

back.

Table 11: Virtex Bit-Stream Lengths

Device # of Configuration Bits

XCV50 559,200

XCV100 781,216

XCV150 1,040,096

XCV200 1,335,840

XCV300 1,751,808

XCV400 2,546,048

XCV600 3,607,968

XCV800 4,715,616

XCV1000 6,127,744

Virtex™ 2.5 V Field Programmable Gate Arrays R

Module 2 of 4 www.xilinx.com DS003-2 (v2.6) July 19, 2001

20 1-800-255-7778 Product Specification

Revision History

Virtex Data Sheet

The Virtex Data Sheet contains the f ollowing modules:

•DS003-1, Virtex 2.5V FPGAs:

Introduction and Ordering Information (Module 1)

•DS003-2, Virtex 2.5V FPGAs:

Functional Description (Module 2)

•DS003-3, Virtex 2.5V FPGAs:

DC and Switching Characteristics (Module 3)

•DS003-4, Virtex 2.5V FPGAs:

Pinout Tables (Module 4)

Date Version Revision

11/98 1.0 Initial Xilinx release.

01/99 1.2 Updated package drawings and specs.

02/99 1.3 Update of package drawings, updated specifications.

05/99 1.4 Addition of package drawings and specifications.

05/99 1.5 Replaced FG 676 & FG680 package drawings.

07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit

Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O

Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and

new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and

Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.

Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated

IOB Input and Output Dela ys based on def ault standard of LVTTL, 12 mA, F ast Sle w Rate.

Added IOB Input Switching Characteristics Standard Adjustments.

09/99 1.7 Speed grade update to preliminary status, Po wer-on specification and Clock-to-Out

Minimums additions, “0” ho ld tim e li sti ng explanatio n, qu ies cen t cur re nt listi ng u pd at e , a nd

Figure 6 ADD RA input label co rrection. Added TIJITCC parameter, changed TOJIT to TOPHASE.

01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,

117153, 117154, and 117612. Modified notes f or Recommended Operating Conditions

(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.

01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement

Methodology table for different I/O standards, changed buffered Hex line info and

Input/Output Timing measurement notes.

03/00 2.0 New TBCK O v alues; corrected FG680 package connection drawing; new note about status

of CCLK pin after configuration.

05/00 2.1 Modified “Pins not listed ...” statement. Speed grade update to Final status.

05/00 2.2 Modified Table 18.

09/00 2.3 •Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices.

•Corrected Units column in table under IOB Input Switching Characteristics.

•Added values to table under CLB SelectRAM Switching Characteristics.

10/00 2.4 •Corrected Pinout information for de vices in the BG256, BG432, and BG560 packages in

Table 18.

•Corrected BG256 Pin Function Diagram.

04/01 2.5 •Re vised minimums f or Global Cloc k S et-Up and Hold f o r LVTTL Standard, with DLL.

•Updated SelectMAP Write Timing Characteristics values in Table 9.

•Converted file to modularized format. See the Virtex Data Sheet section.

07/01 2.6 •Made minor edits to text under Configuration.