October 2007 Rev 1 1/247
1
ST72321Bxxx-Auto
8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM,
ADC, 5 timers, SPI, SCI, I2C interface
Features
Memories
■32 to 60 Kbyte dual voltage High Density Flash
(HDFlash) ROM with readout protection
capability. In-application programming and in-
circuit programming for HDFlash devices
■1 to 2 Kbyte RAM
■HDFlash endurance: 100 cycles, data retention
20 years
Clock, reset and supply management
■Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
■Clock sources: crystal/ceramic resonator
oscillators, internal RC oscillator and bypass
for external clock
■PLL for 2x frequency multiplication
■4 power saving modes: Halt, Active Halt, Wait
and Slow
Interrupt management
■Nested interrupt controller
■14 interrupt vectors plus TRAP and RESET
■Top Level Interrupt (TLI) pin on 64-pin devices
■15/9 external interrupt lines (on 4 vectors)
1 analog peripheral (low current coupling)
■10-bit ADC with up to 16 input ports
Up to 48 I/O ports
■48/32/24 multifunctional bidirectional I/O lines
■34/22/17 alternate function lines
■16/12/10 high sink outputs
5 timers
■Main clock controller with Real-time base,
Beep and Clock-out capabilities
■Configurable watchdog timer
■Two 16-bit timers with 2 input captures, 2
output compares, external clock input on 1
timer, PWM and pulse generator modes
■8-bit PWM auto-reload timer with 2 input
captures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector
3 communications interfaces
■SPI synchronous serial interface
■SCI asynchronous serial interface
■I2C multimaster interface
Development tools
■Full HW/SW development pkg, ICT capability
LQFP64
10 x 10
LQFP64
14 x 14 LQFP44
10 x 10
Table 1. Device summary
Device Prog. memory RAM (stack) Oper. voltage Temp. range Package
ST72321BR9-Auto Flash/ROM
60 Kbytes
2048 (256)
bytes
3.8 to 5.5V Up to
-40 to 125°C
LQFP64 14x14
ST72321BAR9-Auto 10x10
ST72321BJ9-Auto LQFP44 10x10
ST72321BR7-Auto Flash/ROM
48 Kbytes
1536 (256)
bytes
LQFP64 14x14
ST72321BAR7-Auto 10x10
ST72321BJ7-Auto LQFP44 10x10
ST72321BR6-Auto Flash/ROM
32 Kbytes
1024 (256)
bytes
LQFP64 14x14
ST72321BAR6-Auto 10x10
ST72321BJ6-Auto LQFP44 10x10
www.st.com
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
Contents ST72321Bxxx-Auto
2/247
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Differences between ST72321B-Auto and ST72321B datasheets . . . . . . 20
1.2.1 Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2.2 Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.3 Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2 Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1 Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5 ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6 IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.7 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8 Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.4 Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3.5 Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Contents
3/247
6 Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.4 Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.5 Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.5.3 External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5.4 Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 48
6.5.5 Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.6.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.6.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.6.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6.5 System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 53
7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.5 Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.5.2 Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 60
7.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.6.2 External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 64
8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.3 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.4 Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Obsolete Product(s) - Obsolete Product(s)
Contents ST72321Bxxx-Auto
4/247
8.4.1 Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.4.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10 Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.6 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.7 Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 85
10.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.9.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11 Main clock controller with real-time clock and beeper (MCC/RTC) . . 87
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2 Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.4 Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.8 Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.8.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Contents
5/247
11.8.2 MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 90
12 PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.3 Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.5 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.2.6 Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 95
12.2.7 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 95
12.2.8 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.2.9 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.3 ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.1 Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3.2 Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.3 Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12.3.4 PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.3.5 Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.3.6 Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . 101
12.3.7 Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
13.3.3 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.3.4 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
13.3.5 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
13.3.6 One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
13.3.7 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
13.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Obsolete Product(s) - Obsolete Product(s)
Contents ST72321Bxxx-Auto
6/247
13.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
13.7 16-bit timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7.3 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 121
13.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 122
13.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 122
13.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 122
13.7.9 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 123
13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 124
14 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14.5.4 Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.6.1 Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 135
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Contents
7/247
14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
14.8 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15 Serial communications interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 140
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.4.1 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.7 SCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15.7.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15.7.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.7.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.7.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.7.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.7.6 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 157
15.7.7 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 158
16 I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2.1 I2C master features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.2.2 I2C slave features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
16.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.3.2 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.3.3 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
16.4.1 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Obsolete Product(s) - Obsolete Product(s)
Contents ST72321Bxxx-Auto
8/247
16.4.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
16.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.7.1 I2C control register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16.7.2 I2C status register 1 (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
16.7.3 I2C status register 2 (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
16.7.4 I2C clock control register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
16.7.5 I2C data register (DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.7.6 I2C own address register (OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
16.7.7 I2C own address register (OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
17 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
17.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.3.1 A/D converter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.3.2 Starting the conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
17.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.6 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
17.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
17.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.6.4 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
18 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
18.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
18.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
18.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
18.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
18.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
18.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
18.1.7 Relative (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Contents
9/247
18.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
18.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
19 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
19.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
19.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
19.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
19.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
19.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
19.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 194
19.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 194
19.3.4 External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . 195
19.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
19.4.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
19.4.2 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
19.4.3 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
19.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.5.2 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
19.5.3 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 200
19.5.4 RC oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
19.5.5 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.6.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
19.6.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
19.7 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 204
19.7.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 204
19.7.2 EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
19.7.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 206
Obsolete Product(s) - Obsolete Product(s)
Contents ST72321Bxxx-Auto
10/247
19.8 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
19.8.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
19.8.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
19.9 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.9.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
19.9.2 ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
19.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 215
19.11.1 SPI (serial peripheral interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
19.11.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
19.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.12.1 Analog power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . 221
19.12.2 General PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
19.12.3 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
20 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
20.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
20.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
20.3 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
20.3.1 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
21 Device configuration and ordering information . . . . . . . . . . . . . . . . . 228
21.1 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
21.1.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
21.1.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
21.2 ROM device ordering information and transfer of customer code . . . . . 232
21.3 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.2 Evaluation tools and starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.3 Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.4 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
21.3.5 Socket and emulator adapter information . . . . . . . . . . . . . . . . . . . . . . 238
21.4 ST7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
22 Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
22.1 All Flash and ROM devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Contents
11/247
22.1.1 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
22.1.2 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
22.1.3 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 242
22.1.4 SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1.5 16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
22.1.6 TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . 244
22.1.7 I2C multimaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
22.1.8 Pull-up always active on PE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
22.2 Limitations specific to 44-pin 32 Kbyte ROM devices . . . . . . . . . . . . . . . 244
22.2.1 Halt/Active Halt mode power consumption with external clock
enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
22.2.2 Active Halt power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
22.2.3 I²C exit from Halt/Active Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Obsolete Product(s) - Obsolete Product(s)
List of tables ST72321Bxxx-Auto
12/247
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 3. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 4. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6. Arithmetic management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7. Interrupt management bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. Interrupt software priority selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. AVD interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. SICSR description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 15. CPU CC register interrupt bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 16. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 18. Interrupt dedicated instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 19. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. EICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 21. Interrupt sensitivity - ei2 (port B3..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 22. Interrupt sensitivity - ei3 (port B7..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 23. Interrupt sensitivity - ei0 (port A3..0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 24. Interrupt sensitivity - ei1 (port F2..0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 25. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 26. MCC/RTC low power mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 27. I/O output mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 28. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 29. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 30. I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 31. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 32. I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 33. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 34. Effect of low power modes on WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 35. WDGCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 36. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 37. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 38. MCC/RTC interrupt control/wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 39. MCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 40. Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 41. MCCBCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 42. Beep frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 43. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 44. ARTCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 45. Prescaler selection for ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 46. ARTCAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 47. ARTAAR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 48. PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto List of tables
13/247
Table 49. PWMCR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 50. PWM output signal polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 51. PWMDCRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 52. ARTICCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 53. ARTICRx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 54. PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 55. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 56. 16-bit timer interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 57. Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 58. CR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 59. CR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 60. Timer clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 61. CSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 62. 16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 63. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 64. SPI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 65. SPICR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 66. SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 67. SPICSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 68. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 69. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 70. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 71. SCI interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 72. SCISR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. SCICR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 74. SCICR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 75. SCIBRR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 76. SCIERPR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 77. SCIETPR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 78. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 79. SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 80. Effect of low power modes on I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 81. I2C interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 82. CR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 83. SR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 84. SR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 85. CCR register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 86. DR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 87. OAR1 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 88. OAR2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 89. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 90. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 91. ADCCSR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 92. ADCDRH register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 93. ADCDRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 94. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 95. Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 96. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 97. Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 98. Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 99. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes 185
Table 100. Available relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Obsolete Product(s) - Obsolete Product(s)
List of tables ST72321Bxxx-Auto
14/247
Table 101. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 103. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 104. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 106. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 107. Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 108. Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 109. External voltage detector (EVD) thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 110. Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 111. Oscillators, PLL and LVD current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 112. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 113. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 114. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 115. Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 116. OSCRANGE selection for typical resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 117. RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 118. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 119. RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 120. Dual voltage HDFlash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 121. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 122. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 123. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 124. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 125. I/O port pin general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 126. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 127. Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 128. ICCSEL/VPP pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 129. 8-bit PWM-ART auto-reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 130. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 131. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 132. I2C control interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 133. SCL frequency table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 134. 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 135. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 136. 64-pin (14x14) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 224
Table 137. 64-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 225
Table 138. 44-pin (10x10) low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 226
Table 139. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 140. Soldering compatibility (wave and reflow soldering process) . . . . . . . . . . . . . . . . . . . . . . 227
Table 141. Flash option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 142. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 143. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 144. Package selection (OPT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 145. Flash user programmable device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 146. FASTROM factory coded device types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 147. ROM factory coded device types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 148. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 149. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 150. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto List of figures
15/247
List of figures
Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3. 44-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 8. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 12. RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Low voltage detector versus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 15. Using the AVD to monitor VDD (AVDS bit = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1). . . . . . . . . . . . . . . . . . . 52
Figure 17. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. Priority decision process flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 21. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 23. Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 24. Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 25. Active Halt timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 26. Active Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 27. Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 28. Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 29. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 31. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 32. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 33. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 34. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 35. PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 37. PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 38. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 39. External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 40. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 41. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 42. 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 43. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 44. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 45. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 46. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 47. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 48. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Obsolete Product(s) - Obsolete Product(s)
List of figures ST72321Bxxx-Auto
16/247
Figure 49. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 50. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 51. One pulse mode cycle flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 52. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 53. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 115
Figure 54. Pulse width modulation cycle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 55. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 56. Single master/single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 57. Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 58. Hardware/Software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 59. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence . . . . . . . . . . . . . . . . . . 134
Figure 61. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 62. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 63. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 64. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 65. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 66. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 67. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 68. Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 69. Interrupt control logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 70. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 71. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 72. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 73. fCPU max versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 74. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 75. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 76. Application with a crystal or ceramic resonator for ROM (LQFP64 or any 48/60K ROM) 201
Figure 77. Typical fOSC(RCINT) versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 78. Integrated PLL jitter versus signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 79. Unused I/O pins configured as input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 80. Typical IPU vs VDD with VIN = VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 81. Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 82. Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 83. Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 84. Typical VOL versus VDD (standard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 85. Typical VOL versus VDD (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 86. Typical VDD-VOH versus VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 87. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 88. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 89. Two typical applications with ICCSEL/VPP pin(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 90. SPI slave timing diagram with CPHA = 0(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 91. SPI slave timing diagram with CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 92. SPI master timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 93. Typical application with I2C BUS and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 94. RAIN maximum versus fADC with CAIN = 0pF(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 95. Recommended CAIN and RAIN values(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 96. Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 97. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 98. ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 99. 64-pin (14x14) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 100. 64-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto List of figures
17/247
Figure 101. 44-pin (10x10) low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 102. Flash commercial product code structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 103. FASTROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 104. ROM commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Obsolete Product(s) - Obsolete Product(s)
Introduction ST72321Bxxx-Auto
18/247
1 Introduction
1.1 Description
The ST72F321B-Auto Flash and ST72321B-Auto ROM devices are members of the ST7
microcontroller family designed for mid-range automotive applications. Different package
options offer up to 48 I/O pins.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced
instruction set and are available with Flash or ROM program memory. The ST7 family
architecture offers both power and flexibility to software developers, enabling the design of
highly efficient and compact application code.
The on-chip peripherals include an A/D converter, a PWM autoreload timer, two general
purpose timers, a watchdog timer, a real-time base main clock controller, I2C, SPI and SCI
interfaces.
For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt
or Halt mode when the application is in idle or standby state.
Typical applications include
●all types of car body applications such as window lift, DC motor control, rain sensors
●safety microcontroller in airbag and engine management applications
●auxiliary functions in car radios
Related documentation
Migrating applications from ST72511/311/314 to ST72521/321/324 (AN1131)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Introduction
19/247
Figure 1. Device block diagram
8-BIT CORE
ALU
ADDRESS AND DATA BUS
OSC1
VPP
CONTROL
PROGRAM
(32 - 60 Kbytes)
VDD
RESET
PORT F
PF7:0
(8-bits) TIMER A
BEEP
PORT A
RAM
(1024 - 2048 bytes)
PORT C
10-BIT ADC
VAREF
VSSA
PORT B
PB7:0
(8-bits)
PWM ART
PORT E
PE7:0
(8-bits)
SCI
TIMER B
PA7:0
(8-bits)
PORT D
PD7:0
(8-bits)
SPI
PC7:0
(8-bits)
VSS
WATCHDOG
TLI
OSC
LVD
OSC2
MEMORY
MCC/RTC/BEEP
EVD AVD
I2C
Obsolete Product(s) - Obsolete Product(s)
Introduction ST72321Bxxx-Auto
20/247
1.2 Differences between ST72321B-Auto and ST72321B
datasheets
The following sections list the differences between the ST72321B-Auto datasheet
(version 1) and the ST72321B datasheet (version 4 dated 10 April 2007).
1.2.1 Principal differences
1. Table 2: Device pin description on page 28:
– removed LQFP32
– added caution text for PC6
– replaced VREF with VAREF in Note 3
– added Note 4 to LQFP44 pin No. 22
2. Table 30: I/O port configuration on page 79:
– modified Input and Output table headers
– changed configuration of pin PE2 and modified Note 1
3. Table 104: Current characteristics on page 192:
– changed maximum value for output current sunk by any standard I/O and control
pin
– changed maximum value for output current sunk by any high sink I/O pin
– added “Injected current on PC6 pin (Flash devices only)” to IINJ(PIN) ratings
– reorganized footnotes
– modified Note 3
4. Table 110: Current consumption on page 196: Changed Flash device typical and
maximum values in Active Halt mode
5. Table 120: Dual voltage HDFlash memory on page 203:
– changed data retention conditions and minimum value
– replaced TA=25°C with TA=85°C in conditions for NRW
6. Table 134: 10-bit ADC characteristics on page 220:
– modified parameter for input leakage current
– removed negative input leakage current parameter
– added Note 2
7. Table 135: ADC accuracy on page 223
– added maximum values specific to 32 Kbyte Flash devices only
– added conditions to total unadjusted error, to offset error and to gain error
– redistributed footnotes
– modified Note 1
8. Table 141: Flash option bytes on page 228:
– Option byte 0: Changed OPT1 to reserved
– Option byte 1: Replaced OPT7 default value with Note 1
– Option byte 1: Changed OPT3 default value of from 1 to 0
9. Table 142: Option byte 0 bit description on page 228: Changed OPT1 to reserved
10. Table 143: Option byte 1 bit description on page 229: Modified function description for
OPT3:1
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Introduction
21/247
11. Table 144: Package selection (OPT7) on page 230: Removed K version
12. ST72321B-Auto MIcrocontroller FASTROM/ROM Option List on page 236:
– updated to include only automotive devices
– added notes 1 and 2 to PLL option
– added caution about readout protection binary value being inverted between ROM
and Flash products
1.2.2 Minor content differences
1. ST72321Bxxx-Auto on page 1:
– changed document title and description
– removed LQFP32 package outline
2. Features on page 1:
– modified data retention in Memories
– replaced ‘up to 16 robust input ports’ with ‘up to 16 input ports’ in 1 analog
peripheral (low current coupling)
–removed Instruction set from list
– modified Development tools list
3. Section 1.1: Description on page 18: Edited content
4. Figure 3: 44-pin LQFP package pinout on page 27:
– added Note 1 for pin 22
– aligned names of pins 2, 3, 4, 5 and 6 to those in Tabl e 2
5. Section 2.1: Package pinout: Removed figure 32-pin LQFP package pinout
6. Table 8: Interrupt software priority selection on page 42
– - removed footnote link from PA6 and PA7 alternate functions cells
– - linked Note 1 to unbonded I/O pins in LQFP44 column
– - defined pin EVD as type ‘I’ and as input level ‘A’
7. Table 8: Interrupt software priority selection on page 42: Added ‘level’ column
8. Section 9.3: I/O port implementation on page 79: Removed following five tables:
– Standard ports PA5:4, PC7:0, PD7:0, PE7:3, PE1:0, PF7:3
– Interrupt ports PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up)
– Interrupt ports PA3, PB7, PB3, PF2 (without pull-up)
– True open drain ports PA7:6
–Pull-up input port PE2 (configurations already exist in Table 30: I/O port
configuration on page 79)
9. Master mode operation on page 129: Modified text concerning SPI operation
10. Section 17.3.2: Starting the conversion on page 178: Replaced ‘A read to the ADCDRH
resets the EOC bit’ with ‘A read to the ADCDRH or a write to any bit of the ADCCSR
register resets the EOC bit’
11. Table 106: General operating conditions on page 193:
– modified TA conditions to include only automotive temperature versions
– added Note 1
12. Table 115: Crystal and ceramic resonator oscillators on page 200:
– modified Note 2
Obsolete Product(s) - Obsolete Product(s)
Introduction ST72321Bxxx-Auto
22/247
– added Note 3
13. Table 116: OSCRANGE selection for typical resonators on page 201:
– added title
– removed footnote detailing SMD- and LEAD-devices
14. Table 121: EMS test results on page 205:
– removed LQFP32 from conditions
– added Note 1
15. Table 122: EMI emissions on page 205:
– removed footnote 2
– added 32/48/60 Kbyte Flash/LQFP64 configuration
– added 48/60 Kbyte ROM/LQFP44 configuration
– added 32/48 Kbyte ROM/LQFP64 configuration
– changed values for 60 Kbyte ROM devices
16. Section 19.7.3: Absolute maximum ratings (electrical sensitivity) on page 206:
Removed text concerning dynamic latch-up (DLU)
17. Electrostatic discharge (ESD) on page 206: Replaced “JESD22-A114A/A115A
standard” with “AEC-Q100-002/-003/-011 standard” in last sentence
18. Table 123: ESD absolute maximum ratings on page 206:
– added AEC-Q100 standards to conditions
– added ‘Class’ column
– added CDM
19. Static latch-up (LU) on page 206:
– updated LU content
– deleted DLU content
20. Table 124: Electrical sensitivities on page 206:
– updated LU conditions and class
– removed DLU row
21. Table 125: I/O port pin general characteristics on page 207:
– replaced symbol for input leakage current IL with Ilkg
– modified Note 4
– Added Note 5
22. Table 136: 64-pin (14x14) low profile quad flat package mechanical data on page 224:
Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in
inches from 3 to 4 decimal digits
23. Table 137: 64-pin (10x10) low profile quad flat package mechanical data on page 225:
Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in
inches from 3 to 4 decimal digits
24. Table 138: 44-pin (10x10) low profile quad flat package mechanical data on page 226:
Changed dimensions in mm from 2 to 3 decimal digits and changed dimensions in
inches from 3 to 4 decimal digits
25. Added Section 20.3.1: Compatibility on page 227
26. Chapter 21: Device configuration and ordering information on page 228: Reorganized
subsections and made minor text editing changes
27. Table 139: Thermal characteristics on page 227:
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Introduction
23/247
– removed LQFP32 package
– reorganized order of Note 1 and Note 2
28. Table 145: Flash user programmable device types on page 231:
– updated to include only automotive device order codes
– added Note 1
29. Added Figure 102: Flash commercial product code structure on page 231
30. Section 21.2: ROM device ordering information and transfer of customer code on
page 232: Edited and updated content
31. Added Table 146: FASTROM factory coded device types on page 232
32. Added Figure 103: FASTROM commercial product code structure on page 233
33. Added Table 147: ROM factory coded device types on page 234
34. Figure 104: ROM commercial product code structure on page 235: Updated to include
only automotive devices
35. Section 21.3: Development tools on page 237: Edited and updated content
36. Table 148: STMicroelectronics development tools on page 238: Removed K devices
from supported products
37. Table 149: Suggested list of socket types on page 238: Removed LQFP32 device
38. Section 21.4: ST7 application notes on page 238: Removed table ST7 application
notes
39. Chapter 22: Known limitations on page 239:
– removed section ADC accuracy 32 Kbyte Flash devices
– updated workaround in Section 22.1.6: TIMD set simultaneously with OC interrupt
on page 244
– added Section 22.2: Limitations specific to 44-pin 32 Kbyte ROM devices on
page 244
1.2.3 Editing and formatting differences
1. Reformatted document
2. Table 1: Device summary on page 1: Updated to include only automotive specific
devices
3. Section 1.1: Description on page 18: Edited content
4. Section 4.6: IAP (in-application programming) on page 39: Removed text concerning
possibility to download code from USB and CAN interfaces
5. Section 5.3.4: Condition code (CC) register on page 41: Replaced IxSPR with ISPRx
6. Table 7: Interrupt management bits on page 42: Modified bit names
7. Monitoring the VDD main supply on page 50: Edited bullet text at end of section
8. Table 10: Effect of low power modes on SI on page 52: Added title
9. Table 11: AVD interrupt control/wake-up capability on page 52: Added title
10. Table 13: Reset source flags on page 53: Added title
11. Figure 18: Priority decision process flowchart on page 56: Changed title
12. Table 15: CPU CC register interrupt bits description on page 59: Modified bit names
13. Table 17: Interrupt priority bits on page 60: Added title
14. Table 26: MCC/RTC low power mode selection on page 70: Added title
Obsolete Product(s) - Obsolete Product(s)
Introduction ST72321Bxxx-Auto
24/247
15. Table 27: I/O output mode selection on page 76: Added title
16. Table 31: Effect of low power modes on I/O ports on page 80: Added title
17. Table 32: I/O port interrupt control/wake-up capability on page 80: Added title
18. Table 34: Effect of low power modes on WDG on page 85: Added title
19. Table 37: Effect of low power modes on MCC/RTC on page 88: Added title
20. Table 38: MCC/RTC interrupt control/wake-up capability on page 88: Added title
21. Table 40: Time base selection on page 90: Added title
22. Table 42: Beep frequency selection on page 90: Added title
23. Table 45: Prescaler selection for ART on page 98: Added title
24. Table 50: PWM output signal polarity selection on page 100: Added title
25. 16-bit read sequence on page 106: Minor text editing changes
26. Section 13.3.6: One Pulse mode on page 113: Edited step 1 of procedure
27. Section 13.3.7: Pulse width modulation mode on page 115: Edited steps 1 and 2 of
procedure
28. Table 55: Effect of low power modes on 16-bit timer on page 117: Added title
29. Table 56: 16-bit timer interrupt control/wake-up capability on page 117: Added title
30. Table 63: Effect of low power modes on SPI on page 135: Added title
31. Table 64: SPI interrupt control/wake-up capability on page 135: Added title
32. Table 70: Effect of low power modes on SCI on page 151: Added title
33. Table 71: SCI interrupt control/wake-up capability on page 151: Added title
34. Table 80: Effect of low power modes on I2C on page 168: Added title
35. Figure 69: Interrupt control logic diagram on page 168: Changed title
36. Table 81: I2C interrupt control/wake-up capability on page 168: Added title
37. Table 90: Effect of low power modes on ADC on page 179: Changed title
38. Table 103: Voltage characteristics on page 191: Removed note 2
39. Removed note below Figure 73: fCPU max versus VDD on page 193
40. Table 111: Oscillators, PLL and LVD current consumption on page 197: Added title
41. Table 114: External clock source on page 199: Replaced symbol for input leakage
current IL with Ilkg
42. Figure 74: Typical application with an external clock source on page 199: Replaced
symbol IL with Ilkg
43. Section 19.7: EMC (electromagnetic compatibility) characteristics on page 204:
Modified title
44. Table 128: ICCSEL/VPP pin characteristics on page 213: Replaced symbol for input
leakage current IL with Ilkg
45. Table 131: SPI characteristics on page 215: Added Note 1
46. Figure 90: SPI slave timing diagram with CPHA = 0(1) on page 216: Reorganized
footnotes
47. Figure 91: SPI slave timing diagram with CPHA = 1(1) on page 216: Reorganized
footnotes
48. Figure 92: SPI master timing diagram(1) on page 217: Reorganized footnotes
49. Table 132: I2C control interface characteristics on page 218: Reorganized footnotes
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Introduction
25/247
50. Figure 93: Typical application with I2C BUS and timing diagram(1) on page 219:
Reorganized footnotes
51. Figure 96: Typical A/D converter application on page 221:
– replaced symbol IL with Ilkg
–removed I
lkg value ‘±1µA’
52. Figure 98: ADC error classification on page 223: Changed title
53. Table 136: 64-pin (14x14) low profile quad flat package mechanical data on page 224:
Added Note 1
54. Table 137: 64-pin (10x10) low profile quad flat package mechanical data on page 225:
Added Note 1
Obsolete Product(s) - Obsolete Product(s)
Package pinout and pin description ST72321Bxxx-Auto
26/247
2 Package pinout and pin description
2.1 Package pinout
Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout
VAREF
VSSA
VDD_3
VSS_3
MCO / AIN8 / PF0
BEEP / (HS) PF1
(HS) PF2
OCMP2_A / AIN9 / PF3
OCMP1_A / AIN10 / PF4
ICAP2_A / AIN11 / PF5
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ei2
ei3
ei0
ei1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_0
VDD_0
VSS_1
VDD_1
PA3 ( H S )
PA2
VDD_2
OSC1
OSC2
VSS_2
TLI
EVD
RESET
VPP / ICCSEL
PA7 (HS) / SCLI
PA6 ( H S ) / SDAI
PA5 ( H S )
PA4 ( H S )
PE3
PE2
PE1 / RDI
PE0 / TDO
(HS) 20mA high sink capability
eix associated external interrupt vector
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Package pinout and pin description
27/247
Figure 3. 44-pin LQFP package pinout
1. Pin 22 is not connected on 48 Kbyte and 64 Kbyte ROM devices
For external pin connection guidelines, refer to Chapter 19: Electrical characteristics.
MCO / AIN8 / PF0
BEEP / (HS) PF1
(HS) PF2
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0
VSS_0(1)
AIN5 / PD5
VAREF
VSSA
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
ei2
ei3
ei0
ei1
PWM0 / PB3
ARTCLK / (HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
RDI / PE1
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_1
VDD_1
PA3 (H S )
PC7 / SS / AIN15
VSS_2
RESET
VPP / ICCSEL
PA7 (HS) / SCLI
PA6 (HS) / SDAI
PA5 ( H S )
PA4 ( H S )
PE0 / TDO
VDD_2
OSC1
OSC2
(HS) 20mA high sink capability
eix associated external interrupt vector
Obsolete Product(s) - Obsolete Product(s)
Package pinout and pin description ST72321Bxxx-Auto
28/247
2.2 Pin description
In the device pin description table, the RESET configuration of each pin is shown in bold.
This configuration is valid as long as the device is in reset state.
Refer to Chapter 9: I/O ports on page 75 for more details on the software configuration of
the I/O ports.
Table 2. Device pin description
Pin No.
Pin name
Type
Level Port Main
function
(after
reset)
Alternate function
LQFP64
LQFP44
Input
Output
Input Output
float
wpu
int
ana
OD
PP
1-
(1)(2) PE4(HS) I/O CTHS XXXXPort E4
2-
(1)(2) PE5(HS) I/O CTHS XXXXPort E5
3-
(1)(2) PE6(HS) I/O CTHS XXXXPort E6
4-
(1)(2) PE7(HS) I/O CTHS XXXXPort E7
5 2 PB0/PWM3 I/O CTXei2 X X Port B0 PWM Output 3
6 3 PB1/PWM2 I/O CTXei2 X X Port B1 PWM Output 2
7 4 PB2/PWM1 I/O CTXei2 X X Port B2 PWM Output 1
8 5 PB3/PWM0 I/O CTXei2 X X Port B3 PWM Output 0
9 6 PB4(HS)/ARTCLK I/O CTHS Xei3 X X Port B4 PWM-ART External
Clock
10 -
(1)(2) PB5 / ARTIC1 I/O CTXei3 X X Port B5 PWM-ART Input
Capture 1
11 -
(1)(2) PB6 / ARTIC2 I/O CTXei3 X X Port B6 PWM-ART Input
Capture 2
12 -
(1)(2) PB7 I/O CTXei3 X X Port B7
13 7 PD0/AIN0 I/O CTXX X X X Port D0 ADC Analog Input 0
14 8 PD1/AIN1 I/O CTXX X X X Port D1 ADC Analog Input 1
15 9 PD2/AIN2 I/O CTXX X X X Port D2 ADC Analog Input 2
16 10 PD3/AIN3 I/O CTXX X X X Port D3 ADC Analog Input 3
17 11 PD4/AIN4 I/O CTXX X X X Port D4 ADC Analog Input 4
18 12 PD5/AIN5 I/O CTXX X X X Port D5 ADC Analog Input 5
19 -
(1)(2) PD6/AIN6 I/O CTXX X X X Port D6 ADC Analog Input 6
20 -
(2)(1) PD7/AIN7 I/O CTXX X X X Port D7 ADC Analog Input 7
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Package pinout and pin description
29/247
21 13 VAREF(3) I Analog Reference Voltage for ADC
22 14 VSSA(3) S Analog Ground Voltage
23 - VDD_3(3) S Digital Main Supply Voltage
24 - VSS_3(3) S Digital Ground Voltage
25 15 PF0/MCO/AIN8 I/O CTXei1 X X X Port F0 Main clock
out (fOSC/2)
ADC
Analog
Input 8
26 16 PF1 (HS)/BEEP I/O CTHS Xei1 X X Port F1 Beep signal output
27 17 PF2 (HS) I/O CTHS Xei1 X X Port F2
28 -
(1)(2) PF3/OCMP2_A/
AIN9 I/O CTXXXXXPort F3
Timer A
Output
Compare 2
ADC
Analog
Input 9
29 18 PF4/OCMP1_A/
AIN10 I/O CTXXXXXPort F4
Timer A
Output
Compare 1
ADC
Analog
Input 10
30 -
(1)(2) PF5/ICAP2_A/
AIN11 I/O CTXXXXXPort F5
Timer A
Input
Capture 2
ADC
Analog
Input 11
31 19 PF6(HS)/ICAP1_A I/O CTHS XX X X Port F6 Timer A Input Capture 1
32 20 PF7(HS)/
EXTCLK_A I/O CTHS XXXXPort F7
Timer A External Clock
Source
33 21 VDD_0(3) S Digital Main Supply Voltage
34 22(4) VSS_0(3) S Digital Ground Voltage
35 23 PC0/OCMP2_B/
AIN12 I/O CTXXXXXPort C0
Timer B
Output
Compare 2
ADC
Analog
Input 12
36 24 PC1/OCMP1_B/
AIN13 I/O CTXXXXXPort C1
Timer B
Output
Compare 1
ADC
Analog
Input 13
37 25 PC2(HS)/
ICAP2_B I/O CTHS XX X X Port C2 Timer B Input Capture 2
38 26 PC3(HS)/
ICAP1_B I/O CTHS XX X X Port C3 Timer B Input Capture 1
39 27 PC4/MISO/
ICCDATA I/O CTXXXXPort C4
SPI Master
In / Slave
Out Data
ICC Data
Input
40 28 PC5/MOSI/AIN14 I/O CTXXXXXPort C5
SPI Master
Out / Slave
In Data
ADC
Analog
Input 14
Table 2. Device pin description (continued)
Pin No.
Pin name
Type
Level Port Main
function
(after
reset)
Alternate function
LQFP64
LQFP44
Input
Output
Input Output
float
wpu
int
ana
OD
PP
Obsolete Product(s) - Obsolete Product(s)
Package pinout and pin description ST72321Bxxx-Auto
30/247
41 29 PC6/SCK/ICCCLK I/O CTXXXXPort C6
SPI Serial
Clock
ICC Clock
Output
Caution: Negative
current injection not
allowed on this pin
(Flash devices only)
42 30 PC7/SS/AIN15 I/O CTXXXXXPort C7
SPI Slave
Select
(active low)
ADC
Analog
Input 15
43 -
(1)(2) PA0 I/O CTXei0 X X Port A0
44 -
(2)(1) PA1 I/O CTXei0 X X Port A1
45 -
(1)(2) PA2 I/O CTXei0 X X Port A2
46 31 PA3(HS) I/O CTHS Xei0 X X Port A3
47 32 VDD_1(3) S Digital Main Supply Voltage
48 33 VSS_1(3) S Digital Ground Voltage
49 34 PA4(HS) I/O CTHS XXXXPort A4
50 35 PA5(HS) I/O CTHS XXXXPort A5
51 36 PA6(HS)/SDAI I/O CTHS XT Port A6 I2C Data
52 37 PA7(HS)/SCLI I/O CTHS XT Port A7 I2C Clock
53 38 VPP/ ICCSEL I
Must be tied low. In Flash
programming mode, this pin acts
as the programming voltage input
VPP
. See Section 19.9.2:
ICCSEL/VPP pin for more details.
High voltage must not be applied
to ROM devices.
54 39 RESET I/O CTTop priority non-maskable interrupt
55 - EVD I A External voltage detector
56 - TLI I CTX Top level interrupt input pin
57 40 VSS_2(3) S Digital Ground Voltage
58 41 OSC2(5) I/O Resonator oscillator inverter output
59 42 OSC1(5) IExternal clock input or Resonator
oscillator inverter input
60 43 VDD_2(3) S Digital Main Supply Voltage
61 44 PE0/TDO I/O CTXX X X Port E0 SCI Transmit Data Out
Table 2. Device pin description (continued)
Pin No.
Pin name
Type
Level Port Main
function
(after
reset)
Alternate function
LQFP64
LQFP44
Input
Output
Input Output
float
wpu
int
ana
OD
PP
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Package pinout and pin description
31/247
Legend / Abbreviations for Tabl e 2 :
Type: I = input
O = output
S = supply
Input level: A = dedicated analog input
In/Output level: C = CMOS 0.3VDD/0.7VDD
CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
●Input: float = floating
wpu = weak pull-up
int = interrupt(a)
ana = analog
●Output: OD = open-drain(b)
PP = push-pull
62 1 PE1/RDI I/O CTXX X X Port E1 SCI Receive Data In
63 -(1) PE2 I/O CTXX(6) X(6) Port E2
64 -
(2)(1) PE3 I/O CTXXXXPort E3
1. On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
2. On the chip, each I/O port may have up to eight pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
3. It is mandatory to connect all available VDD and VAREF pins to the supply voltage and all VSS and VSSA pins to ground.
4. Not connected in 48 Kbyte and 64 Kbyte ROM devices
5. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator; see Chapter 1:
Introduction on page 18 and Section 19.5: Clock and timing characteristics on page 199 for more details.
6. Pull-up always activated on PE2; see limitation Section 22.1.8: Pull-up always active on PE2 on page 244.
Table 2. Device pin description (continued)
Pin No.
Pin name
Type
Level Port Main
function
(after
reset)
Alternate function
LQFP64
LQFP44
Input
Output
Input Output
float
wpu
int
ana
OD
PP
a. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column
(wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, otherwise
the configuration is floating interrupt input.
b. In the open-drain output column, “T” defines a true open-drain I/O (P-Buffer and protection diode to VDD are not
implemented). See Chapter 9: I/O ports on page 75 and Section 19.8: I/O port pin characteristics on page 207
for more details.
Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST72321Bxxx-Auto
32/247
3 Register and memory map
As shown in Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of
RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256
bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Related documentation
Executing Code in ST7 RAM (AN 985)
Figure 4. Memory map
0000h
RAM
Program Memory
(60, 48 or 32 Kbytes)
Interrupt and Reset Vectors
HW Registers
0080h
007Fh
0FFFh
(see Ta b l e 3 )
1000h
FFDFh
FFE0h
FFFFh (see Ta b l e 1 9 )
0880h Reserved
087Fh
Short Addressing
RAM (zero page)
256 bytes Stack
16-bit Addressing
RAM
0100h
01FFh
0080h
0200h
00FFh
or 087Fh 32 Kbytes
8000h
60 Kbytes
48 Kbytes
FFFFh
1000h
4000h
(2048, 1536 or 1024 bytes)
or 067Fh
or 047Fh
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Register and memory map
33/247
Table 3. Hardware register map
Address Block Register label Register name Reset status Remarks
0000h
0001h
0002h
Port A(2) PA D R
PA D D R
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0003h
0004h
0005h
Port B(2) PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0006h
0007h
0008h
Port C
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0009h
000Ah
000Bh
Port D(2) PDDR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h(1)
00h
00h
R/W
R/W
R/W
000Ch
000Dh
000Eh
Port E(2) PEDR
PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h(1)
00h
00h
R/W
R/W(2)
R/W(2)
000Fh
0010h
0011h
Port F(2) PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h(1)
00h
00h
R/W
R/W
R/W
0012h
to
0017h
Reserved area (6 bytes)
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
I2C
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Control Register
I2C Status Register 1
I2C Status Register 2
I2C Clock Control Register
I2C Own Address Register 1
I2C Own Address Register2
I2C Data Register
00h
00h
00h
00h
00h
00h
00h
R/W
Read only
Read only
R/W
R/W
R/W
R/W
001Fh
0020h Reserved area (2 bytes)
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
xxh
0xh
00h
R/W
R/W
R/W
0024h
0025h
0026h
0027h ITC
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
0028h EICR External Interrupt Control Register 00h R/W
0029h FLASH FCSR Flash Control/Status Register 00h R/W
002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W
002Bh SICSR System Integrity Control/Status Register 000x 000xb R/W
002Ch
002Dh MCC MCCSR
MCCBCR
Main Clock Control/Status Register
Main Clock Controller/Beep Control Register
00h
00h
R/W
R/W
Obsolete Product(s) - Obsolete Product(s)
Register and memory map ST72321Bxxx-Auto
34/247
002Eh
to
0030h
Reserved area (3 bytes)
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
TIMER A
TACR2
TACR1
TAC S R
TA I C 1 H R
TAIC1LR
TAO C 1 H R
TAO C 1 L R
TACHR
TAC L R
TA AC H R
TA AC L R
TA I C 2 H R
TAIC2LR
TAO C 2 H R
TAO C 2 L R
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
0040h Reserved area (1 byte)
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
TIMER B
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxxx x0xxb
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
x000 0000b
00h
00h
---
00h
Read only
R/W
R/W
R/W
R/W
R/W
R/W
0058h
to
006Fh
Reserved Area (24 bytes)
0070h
0071h
0072h
ADC
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h
00h
00h
R/W
Read only
Read only
Table 3. Hardware register map (continued)
Address Block Register label Register name Reset status Remarks
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Register and memory map
35/247
Legend: x = undefined, R/W = read/write
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
PWM ART
PWMDCR3
PWMDCR2
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
PWM AR Timer Duty Cycle Register 3
PWM AR Timer Duty Cycle Register 2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
AR Timer Input Capture Control/Status Reg.
AR Timer Input Capture Register 1
AR Timer Input Capture Register 1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
007Eh
007Fh Reserved area (2 bytes)
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
Table 3. Hardware register map (continued)
Address Block Register label Register name Reset status Remarks
Obsolete Product(s) - Obsolete Product(s)
Flash program memory ST72321Bxxx-Auto
36/247
4 Flash program memory
4.1 Introduction
The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-
byte basis using an external VPP supply.
The HDFlash devices can be programmed and erased off-board (plugged in a programming
tool) or on-board using ICP (in-circuit programming) or IAP (in-application programming).
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2 Main features
●3 Flash programming modes:
– Insertion in a programming tool. In this mode, all sectors including option bytes
can be programmed or erased.
– ICP (in-circuit programming). In this mode, all sectors including option bytes can
be programmed or erased without removing the device from the application board.
– IAP (in-application programming). In this mode, all sectors except Sector 0 can be
programmed or erased without removing the device from the application board
and while the application is running.
●ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●Readout protection
●Register Access Security System (RASS) to prevent accidental programming or
erasing
4.3 Structure
The Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall Flash memory size in the microcontroller device, there are up to
three user sectors (see Ta b l e 4 ). Each of these sectors can be erased independently to
avoid unnecessary erasing of the whole Flash memory when only a partial erasing is
required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 5). They are mapped in the
upper part of the ST7 addressing space so the reset and interrupt vectors are located in
Sector 0 (F000h-FFFFh).
Table 4. Sectors available in Flash devices
Flash size (bytes) Available sectors
4K Sector 0
8K Sectors 0, 1
> 8K Sectors 0, 1, 2
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Flash program memory
37/247
Figure 5. Memory map and sector address
4.3.1 Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the
entire program memory is first automatically erased and the device can be reprogrammed.
Readout protection selection depends on the device type:
●In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
●In ROM devices it is enabled by mask option specified in the Option List.
Note:
4.4 ICC interface
ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see
Figure 6). These pins are:
RESET: device reset
VSS: device power supply ground
ICCCLK: ICC output serial clock pin
ICCDATA: ICC input/output serial data pin
ICCSEL/VPP: programming voltage
OSC1 (or OSCIN): main clock input for external source (optional)
VDD: application board power supply (optional, see Figure 6, Note 3)
4 Kbytes
4 Kbytes
2Kbytes
SECTOR 1
SECTOR 0
16 Kbytes
SECTOR 2
8K 16K 32K 60K FLASH
FFFFh
EFFFh
DFFFh
3FFFh
7FFFh
1000h
24 Kbytes
MEMORY SIZE
8Kbytes 40 Kbytes 52 Kbytes
9FFFh
BFFFh
D7FFh
4K 10K 24K 48K
Obsolete Product(s) - Obsolete Product(s)
Flash program memory ST72321Bxxx-Auto
38/247
Figure 6. Typical ICC interface
1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the
programming tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to
implemented in case another device forces the signal. Refer to the programming tool documentation for recommended
resistor values.
2. During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the
programming tool and the application reset circuit if it drives more than 5mA at high level (push-pull output or pull-up
resistor < 1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical
RC network with R > 1K or a reset management IC with open-drain output and pull-up resistor > 1K, no additional
components are needed. In all cases the user must ensure that no external reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends on the programming tool architecture. This pin must be connected when
using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool
manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the
selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2
grounded in this case.
4.5 ICP (in-circuit programming)
To perform ICP the microcontroller must be switched to ICC (in-circuit communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations, or selection serial
communication interface for downloading).
When using an STMicroelectronics or third-party programming tool that supports ICP and
the specific microcontroller device, the user needs only to implement the ICP hardware
interface on the application board (see Figure 6). For more details on the pin locations, refer
to the device pinout description.
ICC CONNECTOR
ICCDATA
ICCCLK
RESET
VDD
HE10 CONNECTOR TYPE
APPLICATION
POWER SUPPLY
1
246810
975 3
PROGRAMMING TOOL
ICC CONNECTOR
APPLICATION BOARD
ICC Cable
(See Note 3)
10kΩ
VSS
ICCSEL/VPP
ST7
CL2 CL1
OSC1
OSC2
OPTIONAL
See Note 1
See Note 2
APPLICATION
RESET SOURCE
APPLICATION
I/O
(See Note 4)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Flash program memory
39/247
4.6 IAP (in-application programming)
This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP
mode or by plugging the device in a programming tool).
This mode is fully controlled by user software. This allows it to be adapted to the user
application, (such as user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored). For example, it is possible to
download code from the serial peripheral or serial communication interface and program it in
the Flash. IAP mode can be used to program any of the Flash sectors except Sector 0,
which is write/erase protected to allow recovery in case errors occur during the
programming operation.
4.7 Related documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming
Reference Manual and to the ST7 ICC Protocol Reference Manual.
4.8 Flash control/status register (FCSR)
This register is reserved for use by programming tool software. It controls the Flash
programming and erasing operations.
FSCR Reset value: 0000 0000 (00h)
76543210
00000000
RW RW RW RW RW RW RW RW
Table 5. Flash control/status register address and reset value
Address (Hex.) Register label 7 6 5 4 3 2 1 0
0029h FCSR
Reset value 00000000
Obsolete Product(s) - Obsolete Product(s)
Central processing unit (CPU) ST72321Bxxx-Auto
40/247
5 Central processing unit (CPU)
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-
bit data manipulation.
5.2 Main features
●Enable executing 63 basic instructions
●Fast 8-bit by 8-bit multiply
●17 main addressing modes (with indirect addressing mode)
●Two 8-bit index registers
●16-bit stack pointer
●Low power Halt and Wait modes
●Priority maskable hardware interrupts
●Non-maskable software/hardware interrupts
5.3 CPU registers
The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
Figure 7. CPU registers
Accumulator
X index register
Y index register
Stack pointer
Condition code register
Program counter
70
1C1I1HI0NZ
Reset value = reset vector @ FFFEh-FFFFh
70
70
70
0715 8PCH PCL
15 8 7 0
Reset value = stack higher address
Reset value = 1 X11X1XX
Reset value = XXh
Reset value = XXh
Reset value = XXh
X = undefined value
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Central processing unit (CPU)
41/247
5.3.1 Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.
5.3.2 Index registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation (the Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
5.3.3 Program counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
5.3.4 Condition code (CC) register
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
CC Reset value: 111x1xxx
76543210
11I1HI0NZC
RW RW RW RW RW RW
Table 6. Arithmetic management bits
Bit Name Function
4 H
Half carry
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instructions. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
2N
Negative
This bit is set and cleared by hardware. It is representative of the result sign of the
last arithmetic, logical or data manipulation. It is a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative (that is, the most significant bit is a logic
1).
This bit is accessed by the JRMI and JRPL instructions.
Obsolete Product(s) - Obsolete Product(s)
Central processing unit (CPU) ST72321Bxxx-Auto
42/247
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See Chapter 7: Interrupts on page 55 for more details.
5.3.5 Stack pointer (SP) register
7
1Z
Zero
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
0C
Carry/borrow
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate
instructions.
Table 7. Interrupt management bits
Bit Name Function
5 I1 Interrupt Software Priority 1
The combination of the I1 and I0 bits gives the current interrupt software priority.
3I0 Interrupt Software Priority 0
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 8. Interrupt software priority selection
Interrupt software priority Level I1 I0
Level 0 (main) Low
High
10
Level 1 01
Level 2 00
Level 3 (= interrupt disable) 1 1
Table 6. Arithmetic management bits (continued)
Bit Name Function
SP Reset value: 01 FFh
1514131211109876543210
00000001SP7SP6SP5SP4SP3SP2SP1SP0
RW RW RW RW RW RW RW RW
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Central processing unit (CPU)
43/247
The stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 8).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a reset stack pointer instruction (RSP), the stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the stack pointer (called S) can be directly accessed by an LD
instruction.
Note: When the lower limit is exceeded, the stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. The other registers are then stored in the next locations as shown in
Figure 8.
●When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Figure 8. Stack manipulation example
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
Subroutine Interrupt
Event
PUSH Y POP Y IRET RET
or RSP
@ 01FFh
@ 0100h
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
44/247
6 Supply, reset and clock management
6.1 Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in Figure 9.
For more details, refer to the dedicated parametric section.
6.2 Main features
●Optional PLL for multiplying the frequency by 2 (not to be used with internal RC
oscillator)
●Reset Sequence Manager (RSM)
●Multi-oscillator Clock Management (MO)
– 5 crystal/ceramic resonator oscillators
– 1 internal RC oscillator
●System Integrity Management (SI)
– Main supply low voltage detection (LVD)
– Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply or the EVD pin
Figure 9. Clock, reset and supply block diagram
LOW VOLTAGE
DETECTOR
(LVD)
fOSC2
AUXILIARY VOLTAGE
DETECTOR
(AVD)
MULTI-
OSCILLATOR
(MO)
OSC1
RESET
VSS
EVD
VDD
RESET SEQUENCE
MANAGER
(RSM)
OSC2 MAIN CLOCK
AVD Interrupt Request
CONTROLLER
PLL
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR TIMER (WDG)
WITH REAL-TIME
CLOCK (MCC/RTC)
AVD AVD AVD LVD
RF
IE
WDG
RF
0
1
fOSC
(option)
0
SF
fCPU
00
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Supply, reset and clock management
45/247
6.3 Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option
byte. If the PLL is disabled, then fOSC2 =f
OSC/2.
Caution: The PLL is not recommended for applications where timing accuracy is required (see
Section 19.5.5: PLL characteristics on page 202).
Figure 10. PLL block diagram
6.4 Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:
●an external source
●4 crystal or ceramic resonator oscillators
●an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Tabl e 9 . Refer to Chapter 19: Electrical characteristics for more details.
Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of four oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 21.1.1: Flash
configuration on page 228 for more details on the frequency ranges). In this mode of the
0
1
PLL OPTION BIT
PLL x 2
fOSC2
/ 2
fOSC
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
46/247
multi-oscillator, the resonator and the load capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output distortion and start-up stabilization time.
The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
Internal RC oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an internal
resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency
accuracy and should not be used in applications that require accurate timing.
In this mode, the two oscillator pins have to be tied to ground.
Table 9. ST7 clock sources
6.5 Reset sequence manager (RSM)
6.5.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 11:
●External RESET source pulse
●Internal LVD RESET (low voltage detection)
●Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
Hardware configuration
External clockCrystal/Ceramic resonatorsInternal RC oscillator
OSC1 OSC2
EXTERNAL
ST7
SOURCE
OSC1 OSC2
LOAD
CAPACITORS
ST7
CL2
CL1
OSC1 OSC2
ST7
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Supply, reset and clock management
47/247
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of three phases as shown in Figure 12:
●Active phase depending on the RESET source
●256 or 4096 CPU clock cycle delay (selected by option byte)
●RESET vector fetch
Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 21.1.1: Flash configuration on page 228).
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset block diagram
Figure 12. RESET sequence phases
6.5.2 Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 19.9: Control pin
characteristics on page 211 for more details.
A RESET signal originating from an external source must have a duration of at least
th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and
therefore the MCU can enter reset state even in Halt mode.
RESET
RON
VDD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
Filter
RESET
ACTIVE PHASE INTERNAL RESET
256 or 4096 CLOCK CYCLES
FETCH
VECTOR
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
48/247
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Chapter 19:
Electrical characteristics.
If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 13),
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 13). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
6.5.3 External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency (see Section 19.3: Operating
conditions on page 193).
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
6.5.4 Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
●Power-on RESET
●Voltage drop RESET
The device RESET pin acts as an output that is pulled low when VDD <V
IT+ (rising edge) or
VDD <V
IT- (falling edge) as shown in Figure 13.
The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.
6.5.5 Internal watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in
Figure 13.
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least tw(RSTL)out.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Supply, reset and clock management
49/247
Figure 13. RESET sequences
6.6 System integrity management (SI)
The System Integrity Management block contains the Low Voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
6.6.1 Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the VDD supply
voltage is below a VIT- reference value. This means that it secures the power-up as well as
the power-down keeping the ST7 in reset.
The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-
on in order to avoid a parasitic reset when the MCU starts running and sinks current on the
supply (hysteresis).
The LVD reset circuitry generates a reset when VDD is below:
–V
IT+ when VDD is rising
–V
IT- when VDD is falling
The LVD function is illustrated in Figure 14.
The voltage threshold can be configured by option byte to be low, medium or high.
VDD
RUN
RESET PIN
EXTERNAL
WATCHDOG
Active Phase
VIT+(LVD)
VIT-(LVD)
th(RSTL)in
tw(RSTL)out
RUN
th(RSTL)in
Active
WATCHDOG UNDERFLOW
tw(RSTL)out
RUN RUN RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 TCPU)
VECTOR FETCH
tw(RSTL)out
Phase
Active
Phase
Active
Phase
DELAY
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
50/247
Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the
MCU can only be in two modes:
– under full software control
– in static safe reset
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to
reset other devices.
Note: The LVD allows the device to be used without any external RESET circuitry.
If the medium or low thresholds are selected, the detection may occur outside the specified
operating voltage range. Below 3.8V, device operation is not guaranteed.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the VDD supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Figure 14. Low voltage detector versus reset
6.6.2 Auxiliary voltage detector (AVD)
The auxiliary voltage detector function (AVD) is based on an analog comparison between a
VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin
voltage level (VEVD). The VIT- reference value for falling voltage is lower than the VIT+
reference value for rising voltage in order to avoid parasitic detection (hysteresis).
The output of the AVD comparator can be read directly by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.
Caution: The AVD function is active only if the LVD is enabled through the option byte.
Monitoring the VDD main supply
This mode is selected by clearing the AVDS bit in the SICSR register.
The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see Section 21.1.1: Flash configuration on page 228).
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).
VDD
VIT+
RESET
VIT-
Vhys
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Supply, reset and clock management
51/247
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See Figure 15.
The interrupt on the rising edge is used to inform the application that the VDD warning state
is over.
If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay
selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.
If trv is greater than 256 or 4096 cycles
●two AVD interrupts will be received if the AVD interrupt is enabled before the VIT+(AVD)
threshold is reached: the first when the AVDIE bit is set, and the second when the
threshold is reached.
●only one AVD interrupt will occur if the AVD interrupt is enabled after the VIT+(AVD)
threshold is reached.
Figure 15. Using the AVD to monitor VDD (AVDS bit = 0)
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:
●VEVD rises up to VIT+(EVD)
●VEVD falls down to VIT-(EVD)
The EVD function is illustrated in Figure 16.
For more details, refer to Chapter 19: Electrical characteristics.
VDD
VIT+(AVD)
VIT-(AVD)
AVDF bit 0 0RESET VALUE
IF AVDIE bit = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS INTERRUPT PROCESS
VIT+(LVD)
VIT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
trv VOLTAGE RISE TIME
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
52/247
Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1)
6.6.3 Low power modes
6.6.4 Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
VEVD
VIT+(EVD)
VIT-(EVD)
AVDF 0 01
IF AVDIE = 1
Vhyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS INTERRUPT PROCESS
Table 10. Effect of low power modes on SI
Mode Effect
Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode.
Halt The SICSR register is frozen.
Table 11. AVD interrupt control/wake-up capability
Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt
AVD event AVDF AVDIE Yes No
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Supply, reset and clock management
53/247
6.6.5 System Integrity (SI) Control/Status register (SICSR)
SICSR Reset value: 000x 000x (00h)
76543210
AVDS AVDIE AVDF LVDRF Reserved WDGRF
RW RW RW RW - RW
Table 12. SICSR description
Bit Name Function
7AVDS
Voltage Detection selection
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
0: Voltage detection on VDD supply
1: Voltage detection on EVD pin
6AVDIE
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
5AVDF
Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 15 and to Monitoring the VDD main supply on page 50 for additional
details.
0: VDD or VEVD over VIT+(AVD) threshold
1: VDD or VEVD under VIT-(AVD) threshold
4 LVDRF
LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See Table 13: Reset
source flags for more details. When the LVD is disabled by OPTION BYTE, the
LVDRF bit value is undefined.
3:1 - Reserved, must be kept cleared.
0 WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It
is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in
Ta b l e 1 3 .
Table 13. Reset source flags
Reset sources LVDRF WDGRF
External RESET pin 0 0
Watchdog 0 1
LVD 1 X
Obsolete Product(s) - Obsolete Product(s)
Supply, reset and clock management ST72321Bxxx-Auto
54/247
Application notes
The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the
LVDRF flag remains set to keep trace of the original failure.
In this case, software can detect a watchdog reset but cannot detect an external reset.
Caution: When the LVD is not activated with the associated option byte, the WDGRF flag cannot be
used in the application.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
55/247
7 Interrupts
7.1 Introduction
The ST7 enhanced interrupt management provides the following features:
●Hardware interrupts
●Software interrupt (TRAP)
●Nested or concurrent interrupt management with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non-maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
This interrupt management is based on:
●Bit 5 and bit 3 of the CPU CC register (I1:0)
●Interrupt software priority registers (ISPRx)
●Fixed interrupt vector addresses located at the high addresses of the memory map
(FFE0h to FFFFh) sorted by hardware priority order
This enhanced interrupt controller guarantees full upward compatibility with the standard
(not nested) ST7 interrupt controller.
7.2 Masking and processing flow
The interrupt masking is managed by the I1 and I0 bits of the CC register and the ISPRx
registers which give the interrupt software priority level of each interrupt vector (see Tabl e
14). The processing flow is shown in Figure 17.
When an interrupt request has to be serviced:
●Normal processing is suspended at the end of the current instruction execution.
●The PC, X, A and CC registers are saved onto the stack.
●I1 and I0 bits of CC register are set according to the corresponding values in the ISPRx
registers of the serviced interrupt vector.
●The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to Table 19: Interrupt
mapping for vector addresses).
The interrupt service routine should end with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
56/247
Figure 17. Interrupt processing flowchart
Servicing pending interrupts
As several interrupts can be pending at the same time, the interrupt to be taken into account
is determined by the following two-step process:
●the highest software priority interrupt is serviced,
●if several interrupts have the same software priority then the interrupt with the highest
hardware priority is serviced first.
Figure 18 describes this decision process.
Figure 18. Priority decision process flowchart
Table 14. Interrupt software priority levels
Interrupt software priority Level I1 I0
Level 0 (main) Low
High
10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1
“IRET”
RESTORE PC, X, A, CC
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
FETCH NEXT
RESET TRAP
PENDING
INSTRUCTION
I1:0
FROM STACK
LOAD PC FROM INTERRUPT VECTOR
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software priority
THE INTERRUPT
STAYS PENDING
than current one
Interrupt has a higher
software priority
than current one
EXECUTE
INSTRUCTION
INTERRUPT
PENDING
SOFTWARE Different
INTERRUPTS
Same
HIGHEST HARDWARE
PRIORITY SERVICED
PRIORITY
HIGHEST SOFTWARE
PRIORITY SERVICED
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
57/247
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
2 TLI, RESET and TRAP can be considered as having the highest software priority in the
decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (RESET, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see Figure 17). After stacking the PC, X, A and CC registers (except for RESET), the
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
●TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be
serviced according to the flowchart in Figure 17.
Caution: TRAP can be interrupted by a TLI.
●RESET
The RESET source has the highest priority in the ST7. This means that the first current
routine has the highest software priority (level 3) and the highest hardware priority.
See Section 6.5: Reset sequence manager (RSM) for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●TLI (top level hardware interrupt)
Caution: This hardware interrupt occurs when a specific edge is detected on the dedicated TLI pin. It
will be serviced according to the flowchart in Figure 17 as a trap.
A TRAP instruction must not be used in a TLI service routine.
●External Interrupts
External interrupts allow the processor to exit from HALT low power mode. External
interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
●Peripheral Interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in Table 19: Interrupt mapping. A peripheral interrupt occurs when a specific
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
58/247
flag is set in the peripheral status registers and if the corresponding enable bit is set in
the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting to be
serviced) will therefore be lost if the clear sequence is executed.
7.3 Interrupts and low power modes
All interrupts allow the processor to exit the Wait low power mode. On the contrary, only
external and other specified interrupts allow the processor to exit from the Halt modes (see
column “Exit from Halt/Active Halt” in Table 19: Interrupt mapping). When several pending
interrupts are present while exiting Halt mode, the first one serviced can only be an interrupt
with “exit from Halt mode” capability and it is selected through the same decision process
shown in Figure 18.
Note: If an interrupt that is not able to exit from Halt mode is pending with the highest priority when
exiting Halt mode, this interrupt is serviced after the first one serviced.
7.4 Concurrent and nested management
The following Figure 19 and Figure 20 show two different interrupt management modes. The
first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the
nested mode in Figure 20. The interrupt hardware priority is given in this order from the
lowest to the highest: MAIN, IT4, IT3, IT2, IT1, IT0, TLI. The software priority is given for
each interrupt.
Warning: A stack overflow may occur without notifying the software of
the failure.
Figure 19. Concurrent interrupt management
MAIN
IT4
IT2
IT1
TRAP
IT1
MAIN
IT0
I1
HARDWARE PRIORITY
SOFTWARE
3
3
3
3
3
3/0
3
11
11
11
11
11
11 / 10
11
RIM
IT2
IT1
IT4
TRAP
IT3
IT0
IT3
I0
10
PRIORITY
LEVEL
USED STACK = 10 BYTES
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
59/247
Figure 20. Nested interrupt management
7.5 Interrupt register description
7.5.1 CPU CC register interrupt bits
These two bits indicate the current interrupt software priority (see Ta b le 1 6 ) and are
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see Table 18: Interrupt dedicated instruction set).
MAIN
IT2
TRAP
MAIN
IT0
IT2
IT1
IT4
TRAP
IT3
IT0
HARDWARE PRIORITY
3
2
1
3
3
3/0
3
11
00
01
11
11
11
RIM
IT1
IT4 IT4
IT1
IT2
IT3
I1 I0
11 / 10 10
SOFTWARE
PRIORITY
LEVEL
USED STACK = 20 BYTES
CPU CC Reset value: 111x 1010 (xAh)
76543210
11I1 HI0 NZC
RW RW RW RW RW RW
Table 15. CPU CC register interrupt bits description
Bit Name Function
5I1
Interrupt Software Priority 1
3I0 Interrupt Software Priority 0
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
60/247
7.5.2 Interrupt software priority registers (ISPRx)
These four registers are read/write, with the exception of bits 7:4 of ISPR3, which are read
only.
These four registers contain the interrupt software priority of each interrupt vector.
●Each interrupt vector (except RESET and TRAP) has corresponding bits in these
registers where its own software priority is stored. This correspondence is shown in the
following Tab l e 1 7 .
●Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1
and I0 bits in the CC register.
●Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value
is kept (Example: previous = CFh, write = 64h, result = 44h).
The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the
I1 and I0 bits of the CC register are both set.
Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior
has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previous one, the interrupt x is re-entered.
Table 16. Interrupt software priority levels
Interrupt software priority Level I1 I0
Level 0 (main) Low
High
10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable(1))
1. TLI, TRAP and RESET events can interrupt a level 3 program.
11
ISPRx Reset value: 1111 1111 (FFh)
76543210
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
ISPR3 1111I1_13 I0_13 I1_12 I0_12
Table 17. Interrupt priority bits
Vector address ISPRx bits
FFFBh-FFFAh I1_0 and I0_0 bits(1)
1. Bits in the ISPRx registers which correspond to the TLI can be read and written but they are not significant
in the interrupt process management.
FFF9h-FFF8h I1_1 and I0_1 bits
... ...
FFE1h-FFE0h I1_13 and I0_13 bits
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
61/247
Otherwise, the software priority stays unchanged up to the next interrupt request (after the
IRET of the interrupt x).
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI
instructions change the current software priority up to the next IRET instruction or one of the
previously mentioned instructions.
Table 18. Interrupt dedicated instruction set
Instruction New description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0 = 11 (level 3) I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
62/247
7.6 External interrupts
7.6.1 I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 21). This control allows to have up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●Falling edge
●Rising edge
●Falling and rising edge
●Falling edge and low level
●Rising edge and high level (only for ei0 and ei2)
Table 19. Interrupt mapping
No. Source
block Description Register
label
Priority
order
Exit
from
Halt /
Active
Halt
Address
vector
RESET Reset N/A yes FFFEh-FFFFh
TRAP Software interrupt no FFFCh-FFFDh
0 TLI External top level interrupt EICR yes FFFAh-FFFBh
1 MCC/RTC Main clock controller time base interrupt MCCSR Higher
priority
yes FFF8h-FFF9h
2 ei0 External interrupt port A3..0
N/A
yes FFF6h-FFF7h
3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h
4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h
5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR yes(1) FFECh-FFEDh
8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh
9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h
10 SCI SCI peripheral interrupts SCISR Lower
priority
no FFE6h-FFE7h
11 AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h
12 I2C I2C peripheral interrupts (see
peripheral) no FFE2h-FFE3h
13 PWM ART PWM ART interrupt ARTCSR yes(2) FFE0h-FFE1h
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
63/247
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.
Figure 21. External interrupt control bits
IS10 IS11
EICR
SENSITIVITY
CONTROL
PBOR.3
PBDDR.3
IPB BIT
PB3 ei2 INTERRUPT SOURCE
PORT B [3:0] INTERRUPTS
PB3
PB2
PB1
PB0
IS10 IS11
EICR
SENSITIVITY
CONTROL
PBOR.7
PBDDR.7
PB7 ei3 INTERRUPT SOURCE
PORT B [7:4] INTERRUPTS
PB7
PB6
PB5
PB4
IS20 IS21
EICR
SENSITIVITY
CONTROL
PAOR.3
PADDR.3
IPA BIT
PA3 ei0 INTERRUPT SOURCE
PORT A [3:0] INTERRUPTS
PA3
PA2
PA1
PA0
IS20 IS21
EICR
SENSITIVITY
CONTROL
PFOR.2
PFDDR.2
PF2 ei1 INTERRUPT SOURCE
PORT F [2:0] INTERRUPTS
PF2
PF1
PF0
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
64/247
7.6.2 External interrupt control register (EICR)
EICR Reset value: 0000 0000 (00h)
76543210
IS1[1:0] IPB IS2[1:0] IPA TLIS TLIE
RW RW RW RW RW RW
Table 20. EICR register description
Bit Name Function
7:6 IS1[1:0]
ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 (port B3..0) (see Ta bl e 2 1 )
- ei3 (port B7..4) (see Ta bl e 2 2 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
5IPB
Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
4:3 IS2[1:0]
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
- ei0 (port A3..0) (see Ta b le 2 3 )
- ei1 (port F2..0) (see Ta b l e 2 4 )
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
2IPA
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
1TLIS
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by
software only when TLIE bit is cleared.
0: Falling edge
1: Rising edge
0TLIE
TLI enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set
and cleared by software.
0: TLI disabled
1: TLI enabled
Note: A parasitic interrupt can be generated when clearing the TLIE bit.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Interrupts
65/247
Table 21. Interrupt sensitivity - ei2 (port B3..0)
IS11 IS10
External interrupt sensitivity
IPB bit = 0 IPB bit = 1
0 0 Falling edge and low level Rising edge and high level
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
Table 22. Interrupt sensitivity - ei3 (port B7..4)
IS11 IS10 External interrupt sensitivity
0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge
Table 23. Interrupt sensitivity - ei0 (port A3..0)
IS21 IS20
External interrupt sensitivity
IPA bit = 0 IPA bit = 1
0 0 Falling edge and low level Rising edge and high level
0 1 Rising edge only Falling edge only
1 0 Falling edge only Rising edge only
1 1 Rising and falling edge
Table 24. Interrupt sensitivity - ei1 (port F2..0)
IS21 IS20 External interrupt sensitivity
0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge
Obsolete Product(s) - Obsolete Product(s)
Interrupts ST72321Bxxx-Auto
66/247
Table 25. Nested interrupts register map and reset values
Address (Hex.)Register label76543210
0024h ISPR0
Reset value
ei1 ei0 MCC TLI
I1_3
1
I0_3
1
I1_2
1
I0_2
1
I1_1
1
I0_1
111
0025h ISPR1
Reset value
SPI ei3 ei2
I1_7
1
I0_7
1
I1_6
1
I0_6
1
I1_5
1
I0_5
1
I1_4
1
I0_4
1
0026h ISPR2
Reset value
AVD SCI TIMER B TIMER A
I1_11
1
I0_11
1
I1_10
1
I0_10
1
I1_9
1
I0_9
1
I1_8
1
I0_8
1
0027h ISPR3
Reset value 1 1 1 1
PWMART I2C
I1_13
1
I0_13
1
I1_12
1
I0_12
1
0028h EICR
Reset value
IS11
0
IS10
0
IPB
0
IS21
0
IS20
0
IPA
0
TLIS
0
TLIE
0
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Power saving modes
67/247
8 Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a RESET the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (fOSC2).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 22. Power saving mode transitions
8.2 Slow mode
This mode has two targets:
●To reduce power consumption by decreasing the internal clock in the device,
●To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (fCPU).
In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU
and peripherals are clocked at this lower frequency (fCPU).
Note: Slow Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
POWER CONSUMPTION
WAIT
SLOW
RUN
ACTIVE HALT
High
Low
SLOW WAIT
HALT
Obsolete Product(s) - Obsolete Product(s)
Power saving modes ST72321Bxxx-Auto
68/247
Figure 23. Slow mode clock transitions
8.3 Wait mode
Wait mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the ‘WFI’ instruction.
All peripherals remain active. During Wait mode, the I[1:0] bits of the CC register are forced
to ‘10’, to enable all interrupts. All other registers and memory remain unchanged. The MCU
remains in Wait mode until an interrupt or RESET occurs, whereupon the Program Counter
branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake
up.
Refer to the following Figure 24.
00 01
SMS
CP1:0
fCPU
NEW SLOW
NORMAL RUN MODE
MCCSR
FREQUENCY
REQUEST
REQUEST
fOSC2
fOSC2/2 fOSC2/4 fOSC2
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Power saving modes
69/247
Figure 24. Wait mode flowchart
1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
8.4 Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register) as shown in Ta b l e 2 6 .
WFI INSTRUCTION
RESET
INTERRUPT
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
OFF
10
ON
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
XX(1)
ON
256 OR 4096 CPU CLOCK
CYCLE DELAY
Obsolete Product(s) - Obsolete Product(s)
Power saving modes ST72321Bxxx-Auto
70/247
8.4.1 Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see Section 12.3: ART registers for more details
on the MCCSR register).
The MCU can exit Active Halt mode on reception of an external interrupt, MCC/RTC
interrupt or a RESET. When exiting Active Halt mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see Figure 26).
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Caution: When exiting Active Halt mode following an MCC/RTC interrupt, OIE bit of MCCSR register
must not be cleared before tDELAY after the interrupt occurs (tDELAY = 256 or 4096 tCPU
delay depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining
tDELAY period.
Figure 25. Active Halt timing overview
1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET.
Table 26. MCC/RTC low power mode selection
MCCSR OIE bit Power saving mode entered when HALT instruction is executed
0Halt
1 Active Halt
HALTRUN RUN
256 OR 4096 CPU
CYCLE DELAY(1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION FETCH
VECTOR
ACTIVE
[MCCSR.OIE = 1]
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Power saving modes
71/247
Figure 26. Active Halt mode flowchart
1. Peripheral clocked with an external clock source can still be active.
2. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
8.4.2 Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Chapter 11: Main clock controller with real-time clock and
beeper (MCC/RTC) for more details on the MCCSR register).
The MCU can exit Halt mode on reception of either a specific interrupt (see Ta bl e 1 9:
Interrupt mapping on page 62) or a RESET. When exiting Halt mode by means of a RESET
or an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay
is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see Figure 28).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
HALT INSTRUCTION
RESET
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS(1)
I[1:0] BITS
ON
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
OFF
XX(2)
ON
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
XX(2)
ON
256 OR 4096 CPU CLOCK
CYCLE DELAY
(MCCSR.OIE = 1)
INTERRUPT
Obsolete Product(s) - Obsolete Product(s)
Power saving modes ST72321Bxxx-Auto
72/247
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’
option bit of the option byte. The HALT instruction when executed while the Watchdog
system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash
configuration on page 228 for more details).
Figure 27. Halt timing overview
HALTRUN RUN
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION FETCH
VECTOR
[MCCSR.OIE = 0]
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Power saving modes
73/247
Figure 28. Halt mode flowchart
1. WDGHALT is an option bit. See Section 21.1.1: Flash configuration for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
Table 19: Interrupt mapping for more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
HALT INSTRUCTION
RESET
INTERRUPT (3)
Y
N
N
Y
CPU
OSCILLATOR
PERIPHERALS (2)
I[1:0] BITS
OFF
OFF
10
OFF
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
OFF
XX (4)
ON
CPU
OSCILLATOR
PERIPHERALS
I[1:0] BITS
ON
ON
XX (4)
ON
256 OR 4096 CPU CLOCK
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT (1) 0
WATCHDOG
RESET
1
(MCCSR.OIE = 0)
CYCLE
Obsolete Product(s) - Obsolete Product(s)
Power saving modes ST72321Bxxx-Auto
74/247
Halt mode recommendations
●Make sure that an external event is available to wake up the microcontroller from Halt
mode.
●When using an external interrupt to wake up the microcontroller, re-initialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
●For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
●The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in ROM with the value
0x8E.
●As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
Related documentation
ST7 Keypad Decoding Techniques, Implementing Wake-Up on Keystroke (AN 980)
How to Minimize the ST7 Power Consumption (AN1014)
Using an active RC to wake up the ST7LITE0 from power saving mode (AN1605)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I/O ports
75/247
9 I/O ports
9.1 Introduction
The I/O ports offer different functional modes:
●transfer of data through digital inputs and outputs
and for specific pins:
●external interrupt generation
●alternate signal input/output for the on-chip peripherals.
An I/O port contains up to eight pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
9.2 Functional description
Each port has two main registers:
●Data Register (DR)
●Data Direction Register (DDR)
and one optional register:
●Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers (bit X corresponding to pin X of the port). The same correspondence is used for
the DR register.
The following description takes into account the OR register (for specific ports which do not
provide this register refer to Section 9.3: I/O port implementation on page 79). The generic
I/O block diagram is shown in Figure 29.
9.2.1 Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note: 1 Writing the DR register modifies the latch value but does not affect the pin status.
2 When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
3 Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
Obsolete Product(s) - Obsolete Product(s)
I/O ports ST72321Bxxx-Auto
76/247
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt sources, these are first detected according to the sensitivity bits in the EICR
register and then logically ORed.
The external interrupts are hardware interrupts, which means that the request latch (not
accessible directly by the application) is automatically cleared when the corresponding
interrupt vector is fetched. To clear an unwanted pending interrupt by software, the
sensitivity bits in the EICR register must be modified.
9.2.2 Output modes
The output configuration is selected by setting the corresponding DDR register bit. In this
case, writing the DR register applies this digital value to the I/O pin through the latch. Then
reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output
push-pull and open-drain. The DR register value and output pin status are shown in the
following Ta bl e 2 7 .
9.2.3 Alternate functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically
selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically
configured in output mode (push-pull or open-drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input
mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate
peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to
be configured in input floating mode.
Table 27. I/O output mode selection
DR Push-pull Open-drain
0V
SS VSS
1V
DD Floating
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I/O ports
77/247
Figure 29. I/O port general block diagram
Table 28. I/O port mode options
Configuration mode Pull-up P-buffer
Diodes
to VDD to VSS
Input Floating with/without Interrupt Off Off
On On
Pull-up with/without Interrupt On
Output
Push-pull Off On
Open-drain (logic level) Off
True open-drain NI NI NI(1)
1. The diode to VDD is not implemented in the true open-drain pads. A local protection between the pad and
VSS is implemented to protect the device against positive stress.
Legend:
Off - Implemented not activated
On - Implemented and activated
NI - Not implemented
DR
DDR
OR
DATA BUS
PAD
VDD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT 1
0
OR SEL
DDR SEL
DR SEL
PULL-UP
CONDITION
P-BUFFER
(see table below)
N-BUFFER
PULL-UP
(see table below)
1
0
ANALOG
INPUT
If implemented
ALTERNATE
INPUT
VDD
DIODES
(see table below)
EXTERNAL
SOURCE (eix)
INTERRUPT
CMOS
SCHMITT
TRIGGER
REGISTER
ACCESS
Obsolete Product(s) - Obsolete Product(s)
I/O ports ST72321Bxxx-Auto
78/247
Table 29. I/O port configurations
Hardware configuration
Input(1)
Open-drain output(2)
Push-pull output(2)
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR
register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate
function reads the pin status given by the DR register content.
CONDITION
PAD
VDD
RPU
EXTERNAL INTERRUPT
DATA BUS
PULL-UP
INTERRUPT
DR REGISTER ACCESS
W
R
SOURCE (eix)
DR
REGISTER
CONDITION
ALTERNATE INPUT
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
ANALOG INPUT
PA D
RPU
DATA BUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
PA D
RPU
DATA BUS
DR
DR REGISTER ACCESS
R/W
VDD
ALTERNATEALTERNATE
ENABLE OUTPUT
REGISTER
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I/O ports
79/247
Caution: The alternate function must not be activated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The
analog multiplexer (controlled by the ADC registers) switches the analog voltage present on
the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while
conversion is in progress. Furthermore it is recommended not to have clocking pins located
close to a selected analog pin.
Warning: The analog input voltage level must be within the limits
stated in the absolute maximum ratings.
9.3 I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open-drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 30.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 30. Interrupt I/O port state transitions
The I/O port register configurations are summarized in the following table.
Table 30. I/O port configuration
Port Pin name
Input (DDR = 0) Output (DDR = 1)
OR = 0 OR = 1 OR = 0 OR = 1
Port A
PA7:6 floating true open-drain
PA5:4 floating pull-up open-drain push-pull
PA3 floating floating interrupt open-drain push-pull
PA2:0 floating pull-up interrupt open-drain push-pull
01
floating/pull-up
interrupt
INPUT
00
floating
(reset state)
INPUT
10
open-drain
OUTPUT
11
push-pull
OUTPUT
XX = DDR, OR
Obsolete Product(s) - Obsolete Product(s)
I/O ports ST72321Bxxx-Auto
80/247
9.4 Low power modes
9.5 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Port B PB7, PB3 floating floating interrupt open-drain push-pull
PB6:5, PB4, PB2:0 floating pull-up interrupt open-drain push-pull
Port C PC7:0 floating pull-up open-drain push-pull
Port D PD7:0 floating pull-up open-drain push-pull
Port E PE7:3, PE1:0 floating pull-up open-drain push-pull
PE2 pull-up open-drain(1) push-pull(1)
Port F
PF7:3 floating pull-up open-drain push-pull
PF2 floating floating interrupt open-drain push-pull
PF1:0 floating pull-up interrupt open-drain push-pull
1. Pull-up is always enabled leading to unwanted power consumption if output is tied to low level
Table 30. I/O port configuration (continued)
Port Pin name
Input (DDR = 0) Output (DDR = 1)
OR = 0 OR = 1 OR = 0 OR = 1
Table 31. Effect of low power modes on I/O ports
Mode Effect
Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
Table 32. I/O port interrupt control/wake-up capability
Interrupt event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event - DDRx, ORx Yes Yes
Table 33. I/O port register map and reset values
Address (Hex.)Register label76543210
Reset value of all I/O port registers00000000
0000h PADR
MSB LSB0001h PADDR
0002h PAOR
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I/O ports
81/247
Related documentation
SPI Communication between ST7 and EEPROM (AN 970)
S/W implementation of I2C bus master (AN1045)
Software LCD driver (AN1048)
0003h PBDR
MSB LSB0004h PBDDR
0005h PBOR
0006h PCDR
MSB LSB0007h PCDDR
0008h PCOR
0009h PDDR
MSB LSB000Ah PDDDR
000Bh PDOR
000Ch PEDR
MSB LSB000Dh PEDDR
000Eh PEOR
000Fh PFDR
MSB LSB0010h PFDDR
0011h PFOR
Table 33. I/O port register map and reset values (continued)
Address (Hex.)Register label76543210
Reset value of all I/O port registers00000000
Obsolete Product(s) - Obsolete Product(s)
Watchdog timer (WDG) ST72321Bxxx-Auto
82/247
10 Watchdog timer (WDG)
10.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated
by external interference or by unforeseen logical conditions, which causes the application
program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before the T6 bit becomes cleared.
10.2 Main features
●Programmable free-running downcounter
●Programmable reset
●Reset (if watchdog activated) when the T6 bit reaches zero
●Optional reset on HALT instruction (configurable by option byte)
●Hardware Watchdog selectable by option byte
10.3 Functional description
The counter value stored in the Watchdog Control register (WDGCR bits T[6:0]), is
decremented every 16384 fOSC2 cycles (approx.), and the length of the timeout period can
be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling the RESET pin
low for typically 30µs.
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This downcounter is free-running: It counts down
even if the watchdog is disabled. The value to be stored in the WDGCR register must be
between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 32: Approximate timeout
duration). The timing varies between a minimum and a maximum value due to the
unknown status of the prescaler when writing to the WDGCR register (see
Figure 33).
Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by
a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Watchdog timer (WDG)
83/247
Figure 31. Watchdog block diagram
10.4 How to program the watchdog timeout
Figure 32 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 33.
Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 32. Approximate timeout duration
RESET
WDGA
6-BIT DOWNCOUNTER (CNT)
fOSC2
T6 T0
WDG PRESCALER
WATCHDOG CONTROL REGISTER (WDGCR)
DIV 4
T1T2T3T4T5
12-BIT MCC
RTC COUNTER
MSB LSB
DIV 64
0611
MCC/RTC
TB[1:0] bits
(MCCSR
Register)
5
CNT Value (hex.)
Watchdog timeout (ms) @ 8 MHz fOSC2
3F
00
38
128
1.5 65
30
28
20
18
10
08
503418 82 98 114
Obsolete Product(s) - Obsolete Product(s)
Watchdog timer (WDG) ST72321Bxxx-Auto
84/247
Figure 33. Exact timeout duration (tmin and tmax)
WHERE:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125ns if fOSC2=8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
To calculate the minimum Watchdog Timeout (tmin):
IF THEN
ELSE
To calculate the maximum Watchdog Timeout (tmax):
IF THEN
ELSE
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
TB1 bit
(MCCSR reg.)
TB0 bit
(MCCSR reg.)
Selected MCCSR
timebase MSB LSB
0 0 2ms 4 59
0 1 4ms 8 53
1 0 10ms 20 35
1 1 25ms 49 54
Value of T[5:0] bits in
WDGCR register (Hex.)
Min. Watchdog
Timeout (ms)
tmin
Max. Watchdog
Timeout (ms)
tmax
00 1.496 2.048
3F 128 128.552
CNT MSB
4
-------------
<tmin tmin0 16384 CNT tosc2
××+=
tmin tmin0 16384 CNT 4CNT
MSB
-----------------
–
⎝⎠
⎛⎞
×192 LSB+()64 4CNT
MSB
-----------------
××
+tosc2
×+=
CNT MSB
4
-------------
≤tmax tmax0 16384 CNT tosc2
××+=
tmax tmax0 16384 CNT 4CNT
MSB
-----------------
–
⎝⎠
⎛⎞
×192 LSB+()64 4CNT
MSB
-----------------
××
+tosc2
×+=
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Watchdog timer (WDG)
85/247
10.5 Low power modes
10.6 Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 21.1.1:
Flash configuration on page 228.
10.7 Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled:
Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected
WDG reset immediately after waking up the microcontroller.
10.8 Interrupts
None.
Table 34. Effect of low power modes on WDG
Mode Effect
Slow No effect on Watchdog
Wait No effect on Watchdog
Halt
OIE bit in
MCCSR
register
WDGHALT
bit in
Option
Byte
00
No Watchdog reset is generated. The MCU enters Halt mode.
The Watchdog counter is decremented once and then stops
counting and is no longer able to generate a watchdog reset
until the MCU receives an external interrupt or a reset.
If an external interrupt is received, the Watchdog restarts
counting after 256 or 4096 CPU clocks. If a reset is generated,
the Watchdog is disabled (reset state) unless Hardware
Watchdog is selected by option byte. For application
recommendations see Section 10.7 below.
0 1 A reset is generated.
1x
No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When
the MCU receives an oscillator interrupt or external interrupt,
the Watchdog restarts counting immediately. When the MCU
receives a reset the Watchdog restarts counting after 256 or
4096 CPU clocks.
Obsolete Product(s) - Obsolete Product(s)
Watchdog timer (WDG) ST72321Bxxx-Auto
86/247
10.9 Register description
10.9.1 Control register (WDGCR)
WDGCR Reset value: 0111 1111 (7Fh)
76543210
WDGA T[6:0]
RW RW
Table 35. WDGCR register description
Bit Name Function
7WDGA
Activation bit
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
6:0 T[6:0]
7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter. It is decremented every 16384
fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
Table 36. Watchdog timer register map and reset values
Address
(Hex.)
Register
label 76543210
002Ah WDGCR
Reset Value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)
87/247
11 Main clock controller with real-time clock and beeper
(MCC/RTC)
11.1 Introduction
The Main Clock Controller consists of three different functions:
●a programmable CPU clock prescaler
●a clock-out signal to supply external devices
●a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2 Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see Section 8.2: Slow mode on page 67
for more details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the
MCCSR register: CP[1:0] and SMS.
11.3 Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a fCPU clock to
drive external devices. It is controlled by the MCO bit in the MCCSR register.
Caution: When selected, the clock out pin suspends the clock during Active Halt mode.
11.4 Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on fOSC2 are available.
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active Halt mode when the
HALT instruction is executed. See Section 8.4: Active Halt and Halt modes on page 69 for
more details.
11.5 Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
Obsolete Product(s) - Obsolete Product(s)
Main clock controller with real-time clock and beeper (MCC/RTC) ST72321Bxxx-Auto
88/247
Figure 34. Main clock controller (MCC/RTC) block diagram
11.6 Low power modes
11.7 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
DIV 2, 4, 8, 16
MCC/RTC INTERRUPT
SMSCP1 CP0 TB1 TB0 OIE OIF
CPU CLOCK
MCCSR
12-BIT MCC RTC
COUNTER
TO CPU AND
PERIPHERALS
fOSC2
fCPU
MCO
MCO
BC1 BC0
MCCBCR
BEEP
SELECTION
BEEP SIGNAL
1
0
TO
WATCHDOG
TIMER
DIV 64
Table 37. Effect of low power modes on MCC/RTC
Mode Effect
Wait No effect on MCC/RTC peripheral.
MCC/RTC interrupt causes the device to exit from Wait mode.
Active Halt No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt causes the device to exit from Active Halt mode.
Halt
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the MCU is woken up by an interrupt with
“exit from HALT” capability.
Table 38. MCC/RTC interrupt control/wake-up capability
Interrupt event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
Time base overflow event OIF OIE Yes No(1)
1. The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)
89/247
11.8 Main clock controller registers
11.8.1 MCC control/status register (MCCSR)
MCCSR Reset value: 0000 0000 (00h)
76543210
MCO CP[1:0] SMS TB[1:0] OIE OIF
RW RW RW RW RW RW
Table 39. MCCSR register description
Bit Name Function
7MCO
Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and
cleared by software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O port)
Note: To reduce power consumption, the MCO function is not active in Active Halt
mode.
6:5 CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow
modes. Their action is conditioned by the setting of the SMS bit. These two bits are
set and cleared by software.
00: fCPU in Slow mode = fOSC2/2
01: fCPU in Slow mode = fOSC2/4
10: fCPU in Slow mode = fOSC2/8
11: fCPU in Slow mode = fOSC2/16
4SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2
1: Slow mode. fCPU is given by CP1, CP0
See Section 8.2: Slow mode on page 67 and Chapter 11: Main clock controller with
real-time clock and beeper (MCC/RTC) for more details.
3:2 TB[1:0]
Time base control
These bits select the programmable divider time base. They are set and cleared by
software (see Ta b l e 4 0 ).
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base
as a real-time clock.
1OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active Halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active Halt
power saving mode.
Obsolete Product(s) - Obsolete Product(s)
Main clock controller with real-time clock and beeper (MCC/RTC) ST72321Bxxx-Auto
90/247
11.8.2 MCC beep control register (MCCBCR)
The beep output signal is available in Active Halt mode but has to be disabled to reduce
consumption.
0OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.
Table 40. Time base selection
Counter prescaler
Time base
TB1 TB0
fOSC2 =4MHz f
OSC2 =8MHz
16000 4ms 2ms 0 0
32000 8ms 4ms 0 1
80000 20ms 10ms 1 0
200000 50ms 25ms 1 1
Table 39. MCCSR register description (continued)
Bit Name Function
MCCBCR Reset value: 0000 0000 (00h)
76543210
Reserved BC[1:0]
-RW
Table 41. MCCBCR register description
Bit Name Function
7:2 - Reserved, must be kept cleared.
1:0 BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability (see Ta bl e 4 2 ).
Table 42. Beep frequency selection
BC1 BC0 Beep mode with fOSC2 =8MHz
00 Off
0 1 ~2 kHz Output
Beep signal
~50% duty cycle
1 0 ~1 kHz
11 ~500Hz
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Main clock controller with real-time clock and beeper (MCC/RTC)
91/247
Table 43. Main clock controller register map and reset values
Address (Hex.) Register label 76543210
002Bh SICSR
Reset value
AVDS
0
AVDIE
0
AVDF
0
LVD R F
x000
WDGRF
x
002Ch MCCSR
Reset value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh MCCBCR
Reset value000000
BC1
0
BC0
0
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
92/247
12 PWM auto-reload timer (ART)
12.1 Introduction
The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto-
reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
These resources allow five possible operating modes:
●Generation of up to 4 independent PWM signals
●Output compare and Time base interrupt
●Up to 2 input capture functions
●External event detector
●Up to 2 external interrupt sources
The three first modes can be used together with a single counter frequency.
The timer can be used to wake up the MCU from Wait and Halt modes.
Figure 35. PWM auto-reload timer block diagram
OVF INTERRUPT
EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR
fINPUT
PWMx
PORT
FUNCTION
ALTERNATE
OCRx
COMPARE
REGISTER
PROGRAMMABLE
PRESCALER
ARR
REGISTER
ICRx
REGISTER
LOAD
OPx
POLARITY
CONTROL
OEx
PWMCR
MUX
fCPU
DCRx
REGISTER
LOAD
fCOUNTER
ARTCLK fEXT
ARTICx
ICFxICSx ICCSR
LOAD
ICx INTERRUPT
ICIEx
INPUT CAPTURE
CONTROL
8-BIT COUNTER
(CAR REGISTER)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto PWM auto-reload timer (ART)
93/247
12.2 Functional description
12.2.1 Counter
The free running 8-bit counter is fed by the output of the prescaler, and is incremented on
every rising edge of the clock signal.
It is possible to read or write the contents of the counter on the fly by reading or writing the
Counter Access register (ARTCAR).
When a counter overflow occurs, the counter is automatically reloaded with the contents of
the ARTARR register (the prescaler is not affected).
12.2.2 Counter clock and prescaler
The counter clock frequency is given by:
fCOUNTER = fINPUT / 2CC[2:0]
The timer counter’s input clock (fINPUT) feeds the 7-bit programmable prescaler, which
selects one of the 8 available taps of the prescaler, as defined by CC[2:0] bits in the
Control/Status Register (ARTCSR). Thus the division factor of the prescaler can be set to 2n
(where n = 0, 1,..7).
This fINPUT frequency source is selected through the EXCL bit of the ARTCSR register and
can be either the fCPU or an external input frequency fEXT
.
The clock input to the counter is enabled by the TCE (Timer Counter Enable) bit in the
ARTCSR register. When TCE is reset, the counter is stopped and the prescaler and counter
contents are frozen. When TCE is set, the counter runs at the rate of the selected clock
source.
12.2.3 Counter and prescaler initialization
After RESET, the counter and the prescaler are cleared and fINPUT = fCPU.
The counter can be initialized by:
●writing to the ARTARR register and then setting the FCRL (Force Counter Re-Load)
and the TCE (Timer Counter Enable) bits in the ARTCSR register
●writing to the ARTCAR counter access register
In both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known
value.
Direct access to the prescaler is not possible.
12.2.4 Output compare control
The timer compare function is based on four different comparisons with the counter (one for
each PWMx output). Each comparison is made between the counter value and an output
compare register (OCRx) value. This OCRx register can not be accessed directly, it is
loaded from the duty cycle register (PWMDCRx) at each overflow of the counter.
This double buffering method avoids glitch generation when changing the duty cycle on the
fly.
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
94/247
Figure 36. Output compare control
12.2.5 Independent PWM signal generation
This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx
output pins with minimum core processing overhead. This function is stopped during Halt
mode.
Each PWMx output signal can be selected independently using the corresponding OEx bit
in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is
configured as output push-pull alternate function.
The PWM signals all have the same frequency which is controlled by the counter period and
the ARTARR register value.
fPWM = fCOUNTER / (256 - ARTARR)
When a counter overflow occurs, the PWMx pin level is changed depending on the
corresponding OPx (output polarity) bit in the PWMCR register. When the counter reaches
the value contained in one of the output compare register (OCRx) the corresponding PWMx
pin level is restored.
It should be noted that the reload values will also affect the value and the resolution of the
duty cycle of the PWM output signal. To obtain a signal on a PWMx pin, the contents of the
OCRx register must be greater than the contents of the ARTARR register.
The maximum available resolution for the PWMx duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by changing the polarity.
COUNTER FDh FEh FFh FDh FEh FFh FDh FEh
ARTARR = FDh
fCOUNTER
OCRx
PWMDCRx FDh FEh
FDh FEh
FFh
PWMx
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto PWM auto-reload timer (ART)
95/247
Figure 37. PWM auto-reload timer function
Figure 38. PWM signal from 0% to 100% duty cycle
12.2.6 Output compare and time base interrupt
On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is
generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF
flag must be reset by the user software. This interrupt can be used as a time base in the
application.
12.2.7 External clock and event detector mode
Using the fEXT external prescaler input clock, the auto-reload timer can be used as an
external clock event detector. In this mode, the ARTARR register is used to select the
nEVENT number of events to be counted before setting the OVF flag.
nEVENT = 256 - ARTARR
Caution: The external clock function is not available in Halt mode. If Halt mode is used in the
application, prior to executing the HALT instruction, the counter must be disabled by clearing
the TCE bit in the ARTCSR register to avoid spurious counter increments.
DUTY CYCLE
REGISTER
AUTO-RELOAD
REGISTER
PWMx OUTPUT
t
255
000
WITH OEx=1
AND OPx=0
(ARTARR)
(PWMDCRx)
WITH OEx=1
AND OPx=1
COUNTER
COUNTER
PWMx OUTPUT
t
WITH OEx=1
AND OPx=0
FDh FEh FFh FDh FEh FFh FDh FEh
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
ARTARR = FDh
fCOUNTER
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
96/247
Figure 39. External event detector example (3 counts)
12.2.8 Input capture function
This mode allows the measurement of external signal pulse widths through ARTICRx
registers.
Each input capture can generate an interrupt independently on a selected input signal
transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture
Control/Status register (ARTICCSR).
These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
The active transition (falling or rising edge) is software programmable through the CSx bits
of the ARTICCSR register.
The read only input capture registers (ARTICRx) are used to latch the auto-reload counter
value when a transition is detected on the ARTICx pin (CFx bit set in ARTICCSR register).
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
Note: After a capture detection, data transfer in the ARTICRx register is inhibited until it is read
(clearing the CFx bit).
The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled
(CIEx bit set). This means that the ARTICRx register has to be read at each capture event to
clear the CFx flag.
The timing resolution is given by auto-reload counter cycle time (1/fCOUNTER).
Note: During Halt mode, if both the input capture and the external clock are enabled, the ARTICRx
register value is not guaranteed if the input capture pin and the external clock change
simultaneously.
COUNTER
t
FDh FEh FFh FDh
OVF
ARTCSR READ
INTERRUPT
ARTARR = FDh
fEXT =f
COUNTER
FEh FFh FDh
IF OIE = 1
INTERRUPT
IF OIE = 1
ARTCSR READ
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto PWM auto-reload timer (ART)
97/247
12.2.9 External interrupt capability
This mode allows the input capture capabilities to be used as external interrupt sources. The
interrupts are generated on the edge of the ARTICx signal.
The edge sensitivity of the external interrupts is programmable (CSx bit of ARTICCSR
register) and they are independently enabled through CIEx bits of the ARTICCSR register.
After fetching the interrupt vector, the CFx flags can be read to identify the interrupt source.
During Halt mode, the external interrupts can be used to wake up the micro (if the CIEx bit is
set).
Figure 40. Input capture timing diagram
04h
COUNTER
t
01h
fCOUNTER
xxh
02h 03h 05h 06h 07h
04h
ARTICx PIN
CFx FLAG
ICRx REGISTER
INTERRUPT
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
98/247
12.3 ART registers
12.3.1 Control/status register (ARTCSR)
ARTCSR Reset value: 0000 0000 (00h)
76543210
EXCL CC[2:0] TCE FCRL OIE OVF
RW RW RW RW RW RW
Table 44. ARTCSR register description
Bit Name Function
7 EXCL
External Clock
This bit is set and cleared by software. It selects the input clock for the 7-bit
prescaler.
0: CPU clock
1: External clock
6:4 CC[2:0]
Counter Clock Control
These bits are set and cleared by software. They determine the prescaler division
ratio from fINPUT (see Ta b l e 4 5 ).
3TCE
Timer Counter Enable
This bit is set and cleared by software. It puts the timer in the lowest power
consumption mode.
0: Counter stopped (prescaler and counter frozen)
1: Counter running
2 FCRL
Force Counter Re-Load
This bit is write-only and any attempt to read it will yield a logical zero. When set, it
causes the contents of ARTARR register to be loaded into the counter, and the
content of the prescaler register to be cleared in order to initialize the timer before
starting to count.
1OIE
Overflow Interrupt Enable
This bit is set and cleared by software. It allows to enable/disable the interrupt which
is generated when the OVF bit is set.
0: Overflow Interrupt disable
1: Overflow Interrupt enable
0OVF
Overflow Flag
This bit is set by hardware and cleared by software reading the ARTCSR register. It
indicates the transition of the counter from FFh to the ARTARR value.
0: New transition not yet reached
1: Transition reached
Table 45. Prescaler selection for ART
fCOUNTER With fINPUT = 8 MHz CC2 CC1 CC0
fINPUT 8 MHz 0 0 0
fINPUT / 2 4 MHz 0 0 1
fINPUT / 4 2 MHz 0 1 0
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto PWM auto-reload timer (ART)
99/247
12.3.2 Counter access register (ARTCAR)
12.3.3 Auto-reload register (ARTARR)
This register has two PWM management functions:
– Adjusting the PWM frequency
– Setting the PWM duty cycle resolution
fINPUT / 8 1 MHz 0 1 1
fINPUT / 16 500 kHz 1 0 0
fINPUT / 32 250 kHz 1 0 1
fINPUT / 64 125 kHz 1 1 0
fINPUT / 128 62.5 kHz 1 1 1
Table 45. Prescaler selection for ART (continued)
fCOUNTER With fINPUT = 8 MHz CC2 CC1 CC0
ARTCAR Reset value: 0000 0000 (00h)
76543210
CA[7:0]
RW
Table 46. ARTCAR register description
Bit Name Function
7:0 CA[7:0]
Counter Access Data
These bits can be set and cleared either by hardware or by software. The
ARTCAR register is used to read or write the auto-reload counter “on the fly”
(while it is counting).
ARTARR Reset value: 0000 0000 (00h)
76543210
AR[7:0]
RW
Table 47. ARTAAR register description
Bit Name Function
7:0 AR[7:0]
Counter Auto-Reload Data
These bits are set and cleared by software. They are used to hold the auto-reload
value which is automatically loaded in the counter when an overflow occurs. At the
same time, the PWM output levels are changed according to the corresponding
OPx bit in the PWMCR register.
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
100/247
12.3.4 PWM control register (PWMCR)
Table 48. PWM frequency versus resolution
ARTARR value Resolution
fPWM
Min Max
0 8-bit ~0.244 kHz 31.25 kHz
[ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz
[ 128..191 ] > 6-bit ~0.488 kHz 125 kHz
[ 192..223 ] > 5-bit ~0.977 kHz 250 kHz
[ 224..239 ] > 4-bit ~1.953 kHz 500 kHz
PWMCR Reset value: 0000 0000 (00h)
76543210
OE[3:0] OP[3:0]
RW RW
Table 49. PWMCR register description
Bit Name Function
7:4 OE[3:0]
PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM
output channels independently acting on the corresponding I/O pin.
0: PWM output disabled
1: PWM output enabled
3:0 OP[3:0]
PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity
of the four PWM output signals (see Ta b l e 5 0 ).
Table 50. PWM output signal polarity selection
PWMx output level
OPx(1)
1. When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
Counter <= OCRx Counter > OCRx
100
011
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto PWM auto-reload timer (ART)
101/247
12.3.5 Duty cycle registers (PWMDCRx)
A PWMDCRx register is associated with the OCRx register of each PWM channel to
determine the second edge location of the PWM signal (the first edge location is common to
all channels and given by the ARTARR register). These PWMDCR registers allow the duty
cycle to be set independently for each PWM channel.
12.3.6 Input capture control / status register (ARTICCSR)
PWMDCRx Reset value: 0000 0000 (00h)
76543210
DC[7:0]
RW
Table 51. PWMDCRx register description
Bit Name Function
7:0 DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
ARTICCSR Reset value: 0000 0000 (00h)
76543210
Reserved CS[2:1] CIE[2:1] CF[2:1]
- RWRWRW
Table 52. ARTICCSR register description
Bit Name Function
7:6 - Reserved, always read as 0.
5:4 CS[2:1]
Capture Sensitivity
These bits are set and cleared by software. They determine the trigger event
polarity on the corresponding input capture channel.
0: Falling edge triggers capture on channel x
1: Rising edge triggers capture on channel x
3:2 CIE[2:1]
Capture Interrupt Enable
These bits are set and cleared by software. They enable or disable the Input
capture channel interrupts independently.
0: Input capture channel x interrupt disabled
1: Input capture channel x interrupt enabled
1:0 CF[2:1]
Capture Flag
These bits are set by hardware and cleared by software reading the
corresponding ARTICRx register. Each CFx bit indicates that an input capture x
has occurred.
0: No input capture on channel x
1: An input capture has occurred on channel x.
Obsolete Product(s) - Obsolete Product(s)
PWM auto-reload timer (ART) ST72321Bxxx-Auto
102/247
12.3.7 Input capture registers (ARTICRx)
ARTICRx Reset value: 0000 0000 (00h)
76543210
IC[7:0]
RO
Table 53. ARTICRx register description
Bit Name Function
7:0 IC[7:0]
Input Capture Data
These read only bits are set and cleared by hardware. An ARTICRx register
contains the 8-bit auto-reload counter value transferred by the input capture
channel x event.
Table 54. PWM auto-reload timer register map and reset values
Address (Hex.) Register label 7 6 5 4 3 2 1 0
0073h PWMDCR3
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0074h PWMDCR2
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0075h PWMDCR1
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0076h PWMDCR0
Reset value
DC7
0
DC6
0
DC5
0
DC4
0
DC3
0
DC2
0
DC1
0
DC0
0
0077h PWMCR
Reset value
OE3
0
OE2
0
OE1
0
OE0
0
OP3
0
OP2
0
OP1
0
OP0
0
0078h ARTCSR
Reset value
EXCL
0
CC2
0
CC1
0
CC0
0
TCE
0
FCRL
0
RIE
0
OVF
0
0079h ARTCAR
Reset value
CA7
0
CA6
0
CA5
0
CA4
0
CA3
0
CA2
0
CA1
0
CA0
0
007Ah ARTARR
Reset value
AR7
0
AR6
0
AR5
0
AR4
0
AR3
0
AR2
0
AR1
0
AR0
0
007Bh ARTICCSR
Reset value 0 0
CS2
0
CS1
0
CIE2
0
CIE1
0
CF2
0
CF1
0
007Ch ARTICR1
Reset value
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
007Dh ARTICR2
Reset value
IC7
0
IC6
0
IC5
0
IC4
0
IC3
0
IC2
0
IC1
0
IC0
0
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
103/247
13 16-bit timer
13.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and
do not share any resources. They are synchronized after an MCU reset as long as the timer
clock frequencies are not modified.
This description covers one or two 16-bit timers. In ST7 devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
13.2 Main features
●Programmable prescaler: fCPU divided by 2, 4 or 8
●Overflow status flag and maskable interrupt
●External clock input (must be at least four times slower than the CPU clock speed) with
the choice of active edge
●1 or 2 Output Compare functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
●1 or 2 Input Capture functions each with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
●Pulse Width Modulation mode (PWM)
●One Pulse mode
●Reduced Power mode
●5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)(a)
The block diagram is shown in Figure 41.
Note: When reading an input signal on a non-bonded pin, the value will always be ‘1’.
a. Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pinout
description.
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
104/247
13.3 Functional description
13.3.1 Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
Counter Register (CR)
●Counter High Register (CHR) is the most significant byte (MS Byte)
●Counter Low Register (CLR) is the least significant byte (LS Byte)
Alternate Counter Register (ACR)
●Alternate Counter High Register (ACHR) is the most significant byte (MS Byte)
●Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 60: Timer clock selection. The value in the counter register repeats every 131072,
262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
105/247
Figure 41. Timer block diagram
1. If IC, OC and TO interrupt request have separate vectors, then the last OR is not present (see device interrupt vector table).
MCU-PERIPHERAL INTERFACE
COUNTER
ALTERNATE
OUTPUT
COMPARE
REGISTER
OUTPUT COMPARE EDGE DETECT
OVERFLOW
DETECT
CIRCUIT
1/2
1/4
1/8
8-bit
buffer
ST7 INTERNAL BUS
LATCH1 OCMP1
ICAP1
EXTCLK
fCPU
TIMER INTERRUPT
ICF2ICF1 TIMD 0 0OCF2OCF1 TOF
PWMOC1E EXEDGIEDG2CC0CC1OC2E OPM
FOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIE TOIE
ICAP2
LATCH2 OCMP2
88
8 low
16
8 high
16 16
16 16
(Control Register 1) CR1 (Control Register 2) CR2
6
16
8 8 8
88 8
high
low
high
high
high
low
low
low
EXEDG
TIMER INTERNAL BUS
CIRCUIT1
EDGE DETECT
CIRCUIT2
CIRCUIT
1
OUTPUT
COMPARE
REGISTER
2
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
CC[1:0]
COUNTER
pin
pin
pin
pin
pin
REGISTER
REGISTER
(1)
CSR
(Control/Status Register)
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
106/247
16-bit read sequence
The 16-bit read sequence (from either the Counter Register or the Alternate Counter
Register) is illustrated in Figure 42.
Figure 42. 16-bit read sequence
The user must read the MS Byte first; the LS Byte value is then buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever timer mode is used (input capture, output compare, one pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h, after which
●the TOF bit of the SR register is set
●a timer interrupt is generated if
– the TOIE bit of the CR1 register is set and
– the I bit of the CC register is cleared
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set
2. An access (read or write) to the CLR register
Note: The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
is buffered
Read
At t0
Read Returns the buffered
LS Byte value at t0
At t0 +Dt
Other
instructions
Beginning of the sequence
Sequence completed
LS Byte
LS Byte
MS Byte
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
107/247
13.3.2 External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 43. Counter timing diagram, internal clock divided by 2
Figure 44. Counter timing diagram, internal clock divided by 4
Figure 45. Counter timing diagram, internal clock divided by 8
Note: The MCU is in reset state when the internal reset signal is high; when it is low the MCU is
running.
CPU CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
108/247
13.3.3 Input capture
In this section, the index, i, may be 1 or 2 because there are two input capture functions in
the 16-bit timer.
The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the
free running counter after a transition is detected on the ICAPi pin (see Figure 46).
ICiR register is a read-only register.
The active transition is software programmable through the IEDGi bit of Control Registers
(CRi).
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function select the following in the CR2 register:
●Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection).
●Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input or input with pull-up without interrupt if this
configuration is available).
And select the following in the CR1 register:
●Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
●Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input or input with pull-up without interrupt if
this configuration is available).
When an input capture occurs:
●ICFi bit is set.
●The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 47).
●A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set
2. An access (read or write) to the ICiLR register
Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
2 The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3 The two input capture functions can be used together even if the timer also uses the two
output compare functions.
4 In One pulse Mode and PWM mode only Input Capture 2 can be used.
MS Byte LS Byte
ICiR ICiHR ICiLR
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
109/247
5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any
transitions on these pins activates the input capture function.
6 Moreover if one of the ICAPi pins is configured as an input and the second one as an output,
an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
7 This can be avoided if the input capture function i is disabled by reading the ICiHR (see note
1).
8 The TOF bit can be used with interrupt generation in order to measure events that go
beyond the timer range (FFFFh).
Figure 46. Input capture block diagram
Figure 47. Input capture timing diagram
ICIE
CC0CC1
16-BIT FREE RUNNING
COUNTER
IEDG1
(Control Register 1) CR1
(Control Register 2) CR2
ICF2ICF1 000
(Status Register) SR
IEDG2
ICAP1
ICAP2
EDGE DETECT
CIRCUIT2
16-BIT
IC1R Register
IC2R Register
EDGE DETECT
CIRCUIT1
pin
pin
FF01 FF02 FF03
FF03
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: The rising edge is the active edge.
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
110/247
13.3.4 Output compare
In this section, the index, i, may be 1 or 2 because there are two output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
When a match is found between the Output Compare register and the free running counter,
the output compare function:
●Assigns pins with a programmable value if the OCiE bit is set
●Sets a flag in the status register
●Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2
(OC2R) contain the value to be compared to the counter register each timer clock cycle.
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
Timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure
To use the output compare function, select the following in the CR2 register:
●Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection).
And select the following in the CR1 register:
●Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
●Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
●OCFi bit is set.
●The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
●A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Where:
∆t = Output compare period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Table 6 0 :
Timer clock selection)
MS byte LS byte
OCiROCiHR OCiLR
∆ OCiR = ∆t * fCPU
PRESC
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
111/247
If the timer clock is an external clock, the formula is:
Where:
∆t = Output compare period (in seconds)
fCPU = External timer clock frequency (in hertz)
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1. Reading the SR register while the OCFi bit is set
2. An access (read or write) to the OCiLR register
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
●Write to the OCiHR register (further compares are inhibited).
●Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
●Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
Note: 1 After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2 If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3 In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 49 on page 112 for an example with fCPU/2 and
Figure 50 on page 112 for an example with fCPU/4). This behavior is the same in OPM or
PWM mode.
4 The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5 The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
13.3.5 Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
∆ OCiR = ∆t * fEXT
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
112/247
Figure 48. Output compare block diagram
Figure 49. Output compare timing diagram, fTIMER =f
CPU/2
Figure 50. Output compare timing diagram, fTIMER =f
CPU/4
OUTPUT COMPARE
16-bit
CIRCUIT
OC1R Register
16-BIT FREE RUNNING
COUNTER
OC1E CC0CC1OC2E
OLVL1OLVL2OCIE
(Control Register 1) CR1
(Control Register 2) CR2
000OCF2OCF1
(Status Register) SR
16-bit
16-bit
OCMP1
OCMP2
Latch
1
Latch
2
OC2R Register
pin
pin
FOLV2 FOLV1
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCRi)2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
113/247
13.3.6 One Pulse mode
One Pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure
To use one pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (using
the appropriate formula below according to the timer clock source used).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
– Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 60: Timer clock selection).
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and OLVL2 bit is
loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R
register.
Figure 51. One pulse mode cycle flowchart
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1. Reading the SR register while the ICFi bit is set
2. An access (read or write) to the ICiLR register
OCMP1 = OLVL1
When counter = OC1R
When event occurs OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
ICR1 = Counter
on ICAP1
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
114/247
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Where:
t = Pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits; see Table 60:
Timer clock selection)
If the timer clock is an external clock the formula is:
Where:
t = Pulse period (in seconds)
fEXT = External clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (see Figure 52).
Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
2 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
4 The ICAP1 pin cannot be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 52. One pulse mode timing example
OCiR value = t * fCPU
PRESC
- 5
OCiR = t * fEXT - 5
COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2
2ED3
FFFC FFFD
OLVL2 OLVL2
OLVL1
ICAP1
OCMP1
compare1
Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
01F8
01F8 2ED3
IC1R
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
115/247
Figure 53. Pulse width modulation mode timing example with 2 output compare
functions
Note: On timers with only one Output Compare register, a fixed frequency PWM signal can be
generated using the output compare and the counter overflow to define the pulse length.
13.3.7 Pulse width modulation mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse Width Modulation mode uses the complete Output Compare 1 function plus the
OC2R register, and so this functionality cannot be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are taken into account only at the end of the
PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using
the appropriate formula below according to the timer clock source used.
2. Load the OC1R register with the value corresponding to the period of the pulse if
OLVL1 = 0 and OLVL2 = 1 using the appropriate formula below according to the timer
clock source used.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 60: Timer clock selection).
COUNTER 34E2 34E2 FFFC
OLVL2 OLVL2OLVL1
OCMP1
compare2 compare1 compare2
Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
FFFC FFFD FFFE 2ED0 2ED1 2ED2
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
116/247
Figure 54. Pulse width modulation cycle flowchart
If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Where:
t = Signal or pulse period (in seconds)
fCPU = CPU clock frequency (in hertz)
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits; see Ta ble 6 0:
Timer clock selection)
If the timer clock is an external clock the formula is:
Where:
t = Signal or pulse period (in seconds)
fEXT = External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (see Figure 53).
Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3 The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
4 In PWM mode the ICAP1 pin cannot be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
5 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
OCMP1 = OLVL2
Counter
= OC2R
OCMP1 = OLVL1
When
When
= OC1R
Counter is reset
to FFFCh
ICF1 bit is set
OCiR value = t * fCPU
PRESC
- 5
OCiR = t * fEXT -5
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
117/247
13.4 Low power modes
13.5 Interrupts
Note: The 16-bit timer interrupt events are connected to the same interrupt vector (see Chapter 7:
Interrupts on page 55). These events generate an interrupt if the corresponding Enable
Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
13.6 Summary of timer modes
Table 55. Effect of low power modes on 16-bit timer
Mode Effect
Wait No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
Halt
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the MCU is woken up by an interrupt with “exit from Halt mode”
capability or from the counter reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the MCU is woken up by an interrupt with “exit from Halt
mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
Table 56. 16-bit timer interrupt control/wake-up capability
Interrupt event Event
flag
Enable
control
bit
Exit
from
Wait
Exit
from
Halt
Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE
Ye s N o
Input Capture 2 event ICF2
Output Compare 1 event (not available in PWM mode) OCF1 OCIE
Output Compare 2 event (not available in PWM mode) OCF2
Timer Overflow event TOF TOIE
Table 57. Timer modes
Modes
Timer resources
Input
Capture 1
Input
Capture 2
Output
Compare 1
Output
Compare 2
Input Capture
(1 and/or 2) Yes Yes Yes Yes
Output Compare
(1 and/or 2)
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
118/247
13.7 16-bit timer registers
Each timer is associated with 3 control and status registers, and with 6 pairs of data
registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter
and the alternate counter.
13.7.1 Control register 1 (CR1)
One Pulse mode
No
Not
recommended(1)
No
Partially(2)
PWM mode Not
recommended(3) No
1. See Note 4 in Section 13.3.6 One Pulse mode
2. See Note 5 in Section 13.3.6 One Pulse mode
3. See Note 4 in Section 13.3.7 Pulse width modulation mode
Table 57. Timer modes
Modes
Timer resources
Input
Capture 1
Input
Capture 2
Output
Compare 1
Output
Compare 2
CR1 Reset value: 0000 0000 (00h)
76543210
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
RW RW RW RW RW RW RW RW
Table 58. CR1 register description
Bit Name Function
7ICIE
Input Capture Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
6OCIE
Output Compare Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
5 TOIE
Timer Overflow Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
4FOLV2
Forced Output Compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
119/247
13.7.2 Control register 2 (CR2)
3FOLV1
Forced Output Compare 1
This bit is set and cleared by software.
0: No effect on the OCMP1 pin
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison
2OLVL2
Output Level 2
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode.
1IEDG1
Input Edge 1
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0OLVL1
Output Level 1
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.
Table 58. CR1 register description (continued)
Bit Name Function
CR2 Reset value: 0000 0000 (00h)
76543210
OC1E OC2E OPM PWM CC[1:0] IEDG2 EXEDG
RW RW RW RW RW RW RW
Table 59. CR2 register description
Bit Name Function
7OC1E
Output Compare 1 Pin Enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP1 pin alternate function enabled
6OC2E
Output Compare 2 Pin Enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare
2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O)
1: OCMP2 pin alternate function enabled
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
120/247
13.7.3 Control/status register (CSR)
5OPM
One Pulse Mode
0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the
generated pulse depends on the contents of the OC1R register.
4PWM
Pulse Width Modulation
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
length of the pulse depends on the value of OC1R register; the period depends on
the value of OC2R register.
3:2 CC[1:0] Clock Control
The timer clock mode depends on these bits (see Ta b l e 6 0 ).
1IEDG2
Input Edge 2
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
0 EXEDG
External Clock Edge
This bit determines which type of level transition on the external clock pin EXTCLK
will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Table 60. Timer clock selection
Timer clock CC1 CC0
fCPU / 4 0 0
fCPU / 2 0 1
fCPU / 8 1 0
External clock (where available)(1)
1. If the external clock pin is not available, programming the external clock configuration stops the counter.
11
Table 59. CR2 register description (continued)
Bit Name Function
CSR Reset value: xxxx x0xx (xxh)
76543210
ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved
RO RO RO RO RO RW -
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
121/247
13.7.4 Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
Table 61. CSR register description
Bit Name Function
7ICF1
Input Capture Flag 1
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) register.
6OCF1
Output Compare Flag 1
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC1R (OC1LR) register.
5TOF
Timer Overflow Flag
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
4ICF2
Input Capture Flag 2
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the
SR register, then read or write the low byte of the IC2R (IC2LR) register.
3OCF2
Output Compare Flag 2
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC2R (OC2LR) register.
2TIMD
Timer disable
This bit is set and cleared by software. When set, it freezes the timer prescaler
and counter and disabled the output functions (OCMP1 and OCMP2 pins) to
reduce power consumption. Access to the timer registers is still available, allowing
the timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
1:0 - Reserved, must be kept cleared
IC1HR Reset value: Undefined
76543210
MSB LSB
RO RO RO RO RO RO RO RO
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
122/247
13.7.5 Input capture 1 low register (IC1LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
13.7.6 Output compare 1 high register (OC1HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
13.7.7 Output compare 1 low register (OC1LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
13.7.8 Output compare 2 high register (OC2HR)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
IC1LR Reset value: Undefined
76543210
MSB LSB
RO RO RO RO RO RO RO RO
OC1HR Reset value: 1000 0000 (80h)
76543210
MSB LSB
RW RW RW RW RW RW RW RW
OC1LR Reset value: 0000 0000 (00h)
76543210
MSB LSB
RW RW RW RW RW RW RW RW
OC2HR Reset value: 1000 0000 (80h)
76543210
MSB LSB
RW RW RW RW RW RW RW RW
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
123/247
13.7.9 Output compare 2 low register (OC2LR)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
13.7.10 Counter high register (CHR)
This is an 8-bit register that contains the high part of the counter value.
13.7.11 Counter low register (CLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after accessing the CSR register clears the
TOF bit.
13.7.12 Alternate counter high register (ACHR)
This is an 8-bit register that contains the high part of the counter value.
OC2LR Reset value: 0000 0000 (00h)
76543210
MSB LSB
RW RW RW RW RW RW RW RW
CHR Reset value: 1111 1111 (FFh)
76543210
MSB LSB
RO RO RO RO RO RO RO RO
CLR Reset value: 1111 1100 (FCh)
76543210
MSB LSB
RO RO RO RO RO RO RO RO
ACHR Reset value: 1111 1111 (FFh)
76543210
MSB LSB
RO RO RO RO RO RO RO RO
Obsolete Product(s) - Obsolete Product(s)
16-bit timer ST72321Bxxx-Auto
124/247
13.7.13 Alternate counter low register (ACLR)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
13.7.14 Input capture 2 high register (IC2HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the Input Capture 2 event).
13.7.15 Input capture 2 low register (IC2LR)
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the Input Capture 2 event).
ACLR Reset value: 1111 1100 (FCh)
76543210
MSB LSB
RO RO RO RO RO RO RO RO
IC2HR Reset value: Undefined
76543210
MSB LSB
RO RO RO RO RO RO RO RO
IC2LR Reset value: Undefined
76543210
MSB LSB
RO RO RO RO RO RO RO RO
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 16-bit timer
125/247
Related documentation
SCI software communications using 16-bit timer (AN 973)
Real-time Clock with ST7 Timer Output Compare (AN 974)
Driving a buzzer through the ST7 Timer PWM function (AN 976)
Using ST7 PWM signal to generate analog input (sinusoid) (AN1041)
UART emulation software (AN1046)
PWM duty cycle switch implementing true 0 or 100 per cent duty cycle (AN1078)
Starting a PWM signal directly at high level using the ST7 16-bit timer (AN1504)
Table 62. 16-bit timer register map and reset values
Address
(Hex.)
Register
label 76543210
Timer A: 32
Timer B: 42
CR1
Reset value
ICIE
0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
IEDG1
0
OLVL1
0
Timer A: 31
Timer B: 41
CR2
Reset value
OC1E
0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
IEDG2
0
EXEDG
0
Timer A: 33
Timer B: 43
CSR
Reset value
ICF1
x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
-
x
-
x
Timer A: 34
Timer B: 44
IC1HR
Reset value
MSB
xxxxxxx
LSB
x
Timer A: 35
Timer B: 45
IC1LR
Reset value
MSB
xxxxxxx
LSB
x
Timer A: 36
Timer B: 46
OC1HR
Reset value
MSB
1000000
LSB
0
Timer A: 37
Timer B: 47
OC1LR
Reset value
MSB
0000000
LSB
0
Timer A: 3E
Timer B: 4E
OC2HR
Reset value
MSB
1000000
LSB
0
Timer A: 3F
Timer B: 4F
OC2LR
Reset value
MSB
0000000
LSB
0
Timer A: 38
Timer B: 48
CHR
Reset value
MSB
1111111
LSB
1
Timer A: 39
Timer B: 49
CLR
Reset value
MSB
1111110
LSB
0
Timer A: 3A
Timer B: 4A
ACHR
Reset value
MSB
1111111
LSB
1
Timer A: 3B
Timer B: 4B
ACLR
Reset value
MSB
1111110
LSB
0
Timer A: 3C
Timer B: 4C
IC2HR
Reset value
MSB
xxxxxxx
LSB
x
Timer A: 3D
Timer B: 4D
IC2LR
Reset value
MSB
xxxxxxx
LSB
x
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
126/247
14 Serial peripheral interface (SPI)
14.1 Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves
however the SPI interface cannot be a master in a multimaster system.
14.2 Main features
●Full duplex synchronous transfers (on 3 lines)
●Simplex synchronous transfers (on 2 lines)
●Master or slave operation
●6 master mode frequencies (fCPU/4 max.)
●fCPU/2 max. slave mode frequency (see note)
●SS Management by software or hardware
●Programmable clock polarity and phase
●End of transfer interrupt flag
●Write collision, Master Mode Fault and Overrun flags
Note: In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
14.3 General description
Figure 55 shows the serial peripheral interface (SPI) block diagram. There are three
registers:
●SPI Control Register (SPICR)
●SPI Control/Status Register (SPICSR)
●SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
●MISO (Master In / Slave Out data)
●MOSI (Master Out / Slave In data)
●SCK (Serial Clock out by SPI masters and input by SPI slaves)
●SS (Slave select): This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
127/247
Figure 55. Serial peripheral interface block diagram
14.3.1 Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 56.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 59) but master and
slave must be programmed with the same timing mode.
SPIDR
Read Buffer
8-bit Shift Register
Write
Read
Data/Address Bus
SPI
SPIE SPE MSTR CPHA SPR0SPR1CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
07
07
SPIF WCOL MODF 0OVR SSISSMSOD
SOD
bit SS 1
0
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
128/247
Figure 56. Single master/single slave application
14.3.2 Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 58)
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode
●SS internal must be held high continuously
In Slave mode
There are two cases depending on the data/clock timing relationship (see Figure 57):
If CPHA = 1 (data latched on 2nd clock edge):
●SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to VSS, or made free for standard I/O by
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
If CPHA = 0 (data latched on 1st clock edge):
●SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see Write collision
error (WCOL) on page 133).
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI MOSI
MISO
SCK SCK
SLAVE
MASTER
SS SS
+5V
MSBit LSBit MSBit LSBit
Not used if SS is managed
by software
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
129/247
Figure 57. Generic SS timing diagram
Figure 58. Hardware/Software slave select management
14.3.3 Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
a) Select the clock frequency by configuring the SPR[2:0] bits.
b) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 59 shows the four possible configurations.
Note: The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high
for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if SS is high).
IMPORTANT: If the SPICSR register is not written first, the SPICR register setting (MSTR
bit) may not be taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1 Byte 2 Byte 3
1
0
SS internal
SSM bit
SSI bit
SS external pin
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
130/247
14.3.4 Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A read to the SPIDR register.
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
14.3.5 Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1. Write to the SPICSR register to perform the following actions:
a) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 59).
Note: The slave must have the same CPOL and CPHA settings as the master.
b) Manage the SS pin as described in Slave select management on page 128 and
Figure 57. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must
be held low during byte transmission and pulled up between each byte to let the
slave write in the shift register.
2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
14.3.6 Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware.
– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPICSR register while the SPIF bit is set
2. A write or a read to the SPIDR register
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
131/247
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition
(OVR) on page 133).
14.4 Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see Figure 59).
Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 59 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
132/247
Figure 59. Data clock timing diagram
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
CAPTURE STROBE
CPHA = 1
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
CAPTURE STROBE
CPHA = 0
Note: This figure should not be used as a replacement for parametric information.
Refer to Chapter 19: Electrical characteristics.
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
133/247
14.5 Error flags
14.5.1 Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
●The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●The MSTR bit is reset, thus forcing the device into slave mode.
Clearing the MODF bit is done through a software sequence:
1. A read access to the SPICSR register while the MODF bit is set.
2. A write to the SPICR register.
Note: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
14.5.2 Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
●The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
14.5.3 Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted; and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management on page 128.
Note: A “read collision” will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 60).
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
134/247
Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence
14.5.4 Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 61).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 61. Single master / multiple slave configuration
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step Read SPICSR
Read SPIDR
2nd Step SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step WCOL = 0
Read SPICSR
Read SPIDR
Note: Writing to the SPIDR register
instead of reading it does not reset the
WCOL bit.
RESULT
RESULT
MISO
MOSI
MOSI
MOSI MOSI MOSIMISO MISO MISOMISO
SS
SS SS SS SS
SCK SCK
SCK
SCK
SCK
5V
Ports
Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
Master
MCU
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
135/247
14.6 Low power modes
14.6.1 Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wake up the ST7 device from Halt mode through a
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave
selection is configured as external (see Slave select management on page 128), make sure
the master drives a low level on the SS pin when the slave enters Halt mode.
14.7 Interrupts
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Table 63. Effect of low power modes on SPI
Mode Effect
Wait No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
Halt
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently
read from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wake-up event, then an overrun error is generated.
This error can be detected after the fetch of the interrupt routine that woke up the
device.
Table 64. SPI interrupt control/wake-up capability
Interrupt event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
SPI End of Transfer event SPIF
SPIE Yes
Ye s
Master Mode Fault event MODF No
Overrun error OVR
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
136/247
14.8 SPI registers
14.8.1 Control register (SPICR)
SPICR Reset value: 0000 xxxx (0xh)
76543210
SPIE SPE SPR2 MSTR CPOL CPHA SPR[1:0]
RW RW RW RW RW RW RW
Table 65. SPICR register description
Bit Name Function
7SPIE
Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
6 SPE
Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see Master mode fault (MODF) on page 133). The SPE bit
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
5SPR2
Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Ta bl e 6 6 .
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
4MSTR
Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS =0 (see Master mode fault (MODF) on page 133).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
3CPOL
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
2CPHA
Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
137/247
14.8.2 Control/status register (SPICSR)
1:0 SPR[1:0]
Serial Clock Frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select
the baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note: These 2 bits have no effect in slave mode.
Table 66. SPI master mode SCK frequency
Serial clock SPR2 SPR1 SPR0
fCPU/4 1 0 0
fCPU/8 0 0 0
fCPU/16 0 0 1
fCPU/32 1 1 0
fCPU/64 0 1 0
fCPU/128 0 1 1
Table 65. SPICR register description (continued)
Bit Name Function
SPICSR Reset value: 0000 0000 (00h)
76543210
SPIF WCOL OVR MODF Reserved SOD SSM SSI
RO RO RO RO - RW RW RW
Table 67. SPICSR register description
Bit Name Function
7SPIF
Serial Peripheral Data Transfer Flag
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared
1: Data transfer between the device and an external device has been completed.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the
SPICSR register is read.
6WCOL
Write Collision status
This bit is set by hardware when a write to the SPIDR register is done during a
transmit sequence. It is cleared by a software sequence (see Figure 60).
0: No write collision occurred.
1: A write collision has been detected.
5OVR
SPI Overrun error
This bit is set by hardware when the byte currently being received in the shift register
is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun
condition (OVR) on page 133). An interrupt is generated if SPIE = 1 in SPICR
register. The OVR bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Obsolete Product(s) - Obsolete Product(s)
Serial peripheral interface (SPI) ST72321Bxxx-Auto
138/247
14.8.3 Data I/O register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
4MODF
Mode Fault flag
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault (MODF) on page 133). An SPI interrupt can be generated if
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected
3 - Reserved, must be kept cleared
2SOD
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
1 SSM
SS Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave select management on
page 128.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O)
0 SSI
SS Internal Mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
Table 67. SPICSR register description (continued)
Bit Name Function
SPIDR Reset value: Undefined
76543210
D[7:0]
RW
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial peripheral interface (SPI)
139/247
Warning: A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 55).
Table 68. SPI register map and reset values
Address
(Hex.)
Register
label 76543210
0021h SPIDR
Reset value
MSB
xxxxxxx
LSB
x
0022h SPICR
Reset value
SPIE
0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h SPICSR
Reset value
SPIF
0
WCOL
0
OVR
0
MODF
00
SOD
0
SSM
0
SSI
0
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
140/247
15 Serial communications interface (SCI)
15.1 Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
15.2 Main features
●Full duplex, asynchronous communications
●NRZ standard format (Mark/Space)
●Dual baud rate generator systems
●Independently programmable transmit and receive baud rates up to 500K baud
●Programmable data word length (8 or 9 bits)
●Receive buffer full, Transmit buffer empty and End of Transmission flags
●2 receiver wake-up modes:
– Address bit (MSB)
– Idle line
●Muting function for multiprocessor configurations
●Separate enable bits for Transmitter and Receiver
●4 error detection flags:
– Overrun error
– Noise error
–Frame error
– Parity error
●5 interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
●Parity control:
– Transmits parity bit
– Checks parity of received data byte
●Reduced power consumption mode
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
141/247
15.3 General description
The interface is externally connected to another device by two pins (see Figure 63):
●TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the
output pin returns to its I/O port configuration. When the transmitter and/or the receiver
are enabled and nothing is to be transmitted, the TDO pin is at high level.
●RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●An Idle Line prior to transmission or reception
●A start bit
●A data word (8 or 9 bits) least significant bit first
●A Stop bit indicating that the frame is complete
This interface uses two types of baud rate generator:
●A conventional type for commonly-used baud rates
●An extended type with a prescaler offering a very wide range of baud rates even with
non-standard oscillator frequencies
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
142/247
Figure 62. SCI block diagram
WAKE
UP
UNIT
RECEIVER
CONTROL
SR
TRANSMIT
CONTROL
TDRE TC RDRF IDLE OR NF FE PE
SCI
CONTROL
INTERRUPT
CR1
R8 T8 SCID M WAKE PCE PS PIE
Received Data Register (RDR)
Received Shift Register
Read
Transmit Data Register (TDR)
Transmit Shift Register
Write
RDI
TDO
(DATA REGISTER) DR
TRANSMITTER
CLOCK
RECEIVER
CLOCK
RECEIVER RATE
TRANSMITTER RATE
BRR
SCP1
fCPU
CONTROL
CONTROL
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
/PR
/16
CONVENTIONAL BAUD RATE GENERATOR
SBKRWURETEILIERIETCIETIE
CR2
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
143/247
15.4 Functional description
The block diagram of the Serial Control Interface, is shown in Figure 62. It contains six
dedicated registers:
●2 control registers (SCICR1 and SCICR2)
●a status register (SCISR)
●a baud rate register (SCIBRR)
●an extended prescaler receiver register (SCIERPR)
●an extended prescaler transmitter register (SCIETPR)
Refer to the register descriptions in Section 15.7 for the definitions of each bit.
15.4.1 Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 62).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of ‘1’s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving ‘0’s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra ‘1’ bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 63. Word length programming
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8
Start
Bit Stop
Bit
Next
Start
Bit
Idle Frame
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Start
Bit Stop
Bit
Next
Start
Bit
Start
Bit
Idle Frame Start
Bit
9-bit Word length (M bit is set)
8-bit Word length (M bit is reset)
Possible
Parity
Bit
Possible
Parity
Bit
Break Frame Start
Bit
Extra
‘1’
Data Frame
Break Frame Start
Bit
Extra
‘1’
Data Frame
Next Data Frame
Next Data Frame
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
144/247
15.4.2 Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this
mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 62).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIETPR registers.
3. Set the TE bit to assign the TDO pin to the alternate function and to send an idle frame
as first transmission.
4. Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
●The TDR register is empty.
●The data transfer is beginning.
●The next data can be written in the SCIDR register without overwriting the previous
data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores the
data in the TDR register and which is copied in the shift register at the end of the current
transmission.
When no transmission is taking place, a write instruction to the SCIDR register places the
data directly in the shift register, the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1. An access to the SCISR register
2. A write to the SCIDR register
Note: The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame length
depends on the M bit (see Figure 63).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
145/247
bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the
recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte
in the SCIDR.
15.4.3 Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this
mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the
received shift register (see Figure 62).
Procedure
1. Select the M bit to define the word length.
2. Select the desired baud rate using the SCIBRR and the SCIERPR registers.
3. Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
●The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
●An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
●The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
cannot be transferred from the shift register to the RDR register as long as the RDRF bit is
not cleared.
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
146/247
When an overrun error occurs:
●The OR bit is set.
●The RDR content is not lost.
●The shift register is overwritten.
●An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise. Normal data bits are considered valid if three consecutive samples
(8th, 9th, 10th) have the same bit value, otherwise the NF flag is set. In the case of start bit
detection, the NF flag is set on the basis of an algorithm combining both valid edge
detection and three samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set
during start bit reception, there should be a valid edge detection as well as three valid
samples.
When noise is detected in a frame:
●The NF flag is set at the rising edge of the RDRF bit.
●Data is transferred from the Shift register to the SCIDR register.
●No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register read
operation.
During reception, if a false start bit is detected (for example, 8th, 9th, 10th samples are 011,
101, 110), the frame is discarded and the receiving sequence is not started for this frame.
There is no RDRF bit set for this frame and the NF flag is set internally (not accessible to the
user). This NF flag is accessible along with the RDRF bit when a next valid frame is
received.
Note: If the application Start Bit is not long enough to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes on page 150.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
147/247
Figure 64. SCI baud rate and extended prescaler block diagram
Framing error
A framing error is detected when:
●The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.
●A break is received.
When the framing error is detected:
●The FE bit is set by hardware.
●Data is transferred from the Shift register to the SCIDR register.
●No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
TRANSMITTER
RECEIVER
SCIETPR
SCIERPR
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
EXTENDED PRESCALER
CLOCK
CLOCK
RECEIVER RATE
TRANSMITTER RATE
SCIBRR
SCP1
fCPU
CONTROL
CONTROL
SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
/PR
/16
CONVENTIONAL BAUD RATE GENERATOR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED TRANSMITTER PRESCALER REGISTER
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
148/247
Conventional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
receive baud rates are 38400 baud.
Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option provides a very fine tuning of the baud rate, using a 255
value prescaler, whereas the conventional baud rate generator retains industry standard
software compatibility.
The extended baud rate generator block diagram is described in the Figure 64.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
Note: The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
with:
ETPR = 1,..,255 (see SCIETPR register)
ERPR = 1,..,255 (see SCIERPR register)
Receiver muting and wake-up feature
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non-addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
●All the reception status bits cannot be set.
●All the receive interrupts are inhibited.
A muted receiver may be awakened by one of the following two ways:
●by Idle Line detection if the WAKE bit is reset
●by Address Mark detection if the WAKE bit is set
Tx = (16*PR)*TR
fCPU Rx = (16*PR)*RR
fCPU
Tx = 16*ETPR*(PR*TR)
fCPU Rx = 16*ERPR*(PR*RR)
fCPU
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
149/247
A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
Receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
Caution: In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the
read operation (RWU = 1) and a address mark wake-up event occurs (RWU is reset) before
the write operation, the RWU bit is set again by this write operation. Consequently the
address byte is lost and the SCI is not woken up from Mute mode.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Ta bl e 6 9 .
Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit
Note: In case of wake-up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity: the parity bit is calculated to obtain an even number of ‘1’s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: the parity bit is calculated to obtain an odd number of ‘1’s inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the interface checks if the received data byte
has an even number of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd
parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register
and an interrupt is generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the Noise Flag bit is set
because the three samples values are not the same.
Table 69. Frame formats
M bit PCE bit SCI frame
0 0 | SB | 8 bit data | STB |
0 1 | SB | 7-bit data | PB | STB |
1 0 | SB | 9-bit data | STB |
1 1 | SB | 8-bit data PB | STB |
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
150/247
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note: The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud
(bit length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs
respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs
for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
–D
TRA: Deviation due to transmitter error (Local oscillator error of the transmitter or
the transmitter is transmitting at a different baud rate).
–D
QUANT: Error due to the baud rate quantization of the receiver.
–D
REC: Deviation of the local oscillator of the receiver: This deviation can occur
during the reception of one complete SCI message assuming that the deviation
has been compensated at the beginning of the message.
–D
TCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
Noise error causes
See also description of noise error in Receiver on page 145.
Start bit
The noise flag (NF) is set during start bit reception if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3
consecutive samples before the falling edge occurs are detected as ‘1’ and, after the
falling edge occurs, during the sampling of the 16 samples, if one of the samples
numbered 3, 5 or 7 is detected as a ‘1’.
2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a ‘1’.
Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag
getting set.
Data bits
The noise flag (NF) is set during normal data bit reception if the following condition occurs:
●During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not
the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag from getting set.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
151/247
Figure 65. Bit sampling in reception mode
15.5 Low power modes
15.6 Interrupts
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
RDI LINE
Sample
clock 1234567891011
12 13 14 15 16
sampled values
One bit time
6/16
7/16 7/16
Table 70. Effect of low power modes on SCI
Mode Effect
Wait No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
Halt SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Table 71. SCI interrupt control/wake-up capability
Interrupt event Event flag Enable control
bit
Exit from
Wait
Exit from
Halt
Transmit Data Register Empty TDRE TIE Yes No
Transmission Complete TC TCIE Yes No
Received Data Ready to be Read RDRF RIE Ye s N o
Overrun Error Detected OR Yes No
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
152/247
15.7 SCI registers
15.7.1 Status register (SCISR)
Idle Line Detected IDLE ILIE Yes No
Parity Error PE PIE Yes No
Table 71. SCI interrupt control/wake-up capability
Interrupt event Event flag Enable control
bit
Exit from
Wait
Exit from
Halt
SCISR Reset value: 1100 0000 (C0h)
76543210
TDRE TC RDRF IDLE OR NF FE PE
RO RO RO RO RO RO RO RO
Table 72. SCISR register description
Bit Name Function
7TDRE
Transmit data register empty
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the
SCICR2 register. It is cleared by a software sequence (an access to the SCISR
register followed by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: Data is not transferred to the shift register unless the TDRE bit is cleared.
6TC
Transmission complete
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared
by a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Preamble or a Break.
5 RDRF
Received data ready flag
This bit is set by hardware when the content of the RDR register has been
transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the SCISR register
followed by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
153/247
4IDLE
Idle line detect
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a
new idle line occurs).
3OR
Overrun error
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RDRF = 1. An interrupt
is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content is not lost but the shift register is
overwritten.
2NF
Noise flag
This bit is set by hardware when noise is detected on a received frame. It is cleared
by a software sequence (an access to the SCISR register followed by a read to the
SCIDR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt.
1FE
Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the
RDRF bit which itself generates an interrupt. If the word currently being transferred
causes both frame error and overrun error, it will be transferred and only the OR bit
will be set.
0PE
Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared
by a software sequence (a read to the status register followed by an access to the
SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
Table 72. SCISR register description (continued)
Bit Name Function
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
154/247
15.7.2 Control register 1 (SCICR1)
SCICR1 Reset value: X000 0000 (x0h)
76543210
R8 T8 SCID M WAKE PCE PS PIE
RW RW RW RW RW RW RW RW
Table 73. SCICR1 register description
Bit Name Function
7R8
Receive data bit 8
This bit is used to store the 9th bit of the received word when M = 1.
6T8
Transmit data bit 8
This bit is used to store the 9th bit of the transmitted word when M = 1.
5SCID
Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and
cleared by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
4M
Word length
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note: The M bit must not be modified during a data transfer (both transmission and
reception).
3 WAKE
Wake-up method
This bit determines the SCI wake-up method. It is set or cleared by software.
0: Idle line
1: Address mark
2PCE
Parity control enable
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M = 1; 8th bit if M = 0) and parity is checked on the received data. This bit is
set and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled
1PS
Parity selection
This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity is selected after
the current byte.
0: Even parity
1: Odd parity
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
155/247
15.7.3 Control register 2 (SCICR2)
0PIE
Parity interrupt enable
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Table 73. SCICR1 register description (continued)
Bit Name Function
SCICR2 Reset value: 0000 0000 (00h)
76543210
TIE TCIE RIE ILIE TE RE RWU SBK
RW RW RW RW RW RW RW RW
Table 74. SCICR2 register description
Bit Name Function
7TIE
Transmitter interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.
6TCIE
Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.
5RIE
Receiver interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR
register.
4ILIE
Idle line interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
3TE
Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Notes:
During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble
(idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits
are both cleared (or if TE is never set).
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
156/247
15.7.4 Data register (SCIDR)
This register contains the Received or Transmitted data character, depending on whether it
is read from or written to.
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 62).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 62).
15.7.5 Baud rate register (SCIBRR)
2RE
Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
1RWU
Receiver wake-up
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in Active mode
1: Receiver in Mute mode
Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some
data first, otherwise it cannot function in Mute mode with wake-up by idle line
detection.
0 SBK
Send break
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word
at the end of the current word.
Table 74. SCICR2 register description (continued)
Bit Name Function
SCIDR Reset value: Undefined
76543210
DR[7:0]
RW
SCIBRR Reset value: 0000 0000 (00h)
76543210
SCP[1:0] SCT[2:0] SCR[2:0]
RW RW RW
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
157/247
15.7.6 Extended receive prescaler division register (SCIERPR)
This register allows setting of the extended prescaler rate division factor for the receive
circuit.
Table 75. SCIBRR register description
Bit Name Function
7:6 SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges.
00: PR prescaling factor = 1
01: PR prescaling factor = 3
10: PR prescaling factor = 4
11: PR prescaling factor = 13
5:3 SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division
applied to the bus clock to yield the transmit rate clock in conventional Baud Rate
Generator mode.
000: TR dividing factor = 1
001: TR dividing factor = 2
010: TR dividing factor = 4
011: TR dividing factor = 8
100: TR dividing factor = 16
101: TR dividing factor = 32
110: TR dividing factor = 64
111: TR dividing factor = 128
2:0 SCR[2:0]
SCI Receiver rate divisor
These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied
to the bus clock to yield the receive rate clock in conventional Baud Rate
Generator mode.
000: RR dividing factor = 1
001: RR dividing factor = 2
010: RR dividing factor = 4
011: RR dividing factor = 8
100: RR dividing factor = 16
101: RR dividing factor = 32
110: RR dividing factor = 64
111: RR dividing factor = 128
SCIERPR Reset value: 0000 0000 (00h)
76543210
ERPR[7:0]
RW
Obsolete Product(s) - Obsolete Product(s)
Serial communications interface (SCI) ST72321Bxxx-Auto
158/247
15.7.7 Extended transmit prescaler division register (SCIETPR)
This register allows setting of the external prescaler rate division factor for the transmit
circuit.
Table 76. SCIERPR register description
Bit Name Function
7:0 ERPR[7:0]
8-bit Extended Receive Prescaler Register
The extended baud rate generator is activated when a value different from 00h is
stored in this register. Therefore the clock frequency issued from the 16 divider
(see Figure 64) is divided by the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended baud rate generator is not used after a reset.
SCIETPR Reset value: 0000 0000 (00h)
76543210
ETPR[7:0]
RW
Table 77. SCIETPR register description
Bit Name Function
7:0 ETPR[7:0]
8-bit Extended Transmit Prescaler Register
The extended baud rate generator is activated when a value different from 00h is
stored in this register. Therefore the clock frequency issued from the 16 divider
(see Figure 64) is divided by the binary factor set in the SCIETPR register (in the
range 1 to 255).
The extended baud rate generator is not used after a reset.
Table 78. Baud rate selection
Symbol Parameter
Conditions
Standard Baud rate Unit
fCPU
Accuracy
versus
standard
Prescaler
fTx
fRx
Communication
frequency 8MHz
~0.16%
Conventional mode
TR (or RR) = 128, PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR = 13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
Hz
~0.79%
Extended mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1 14400 ~14285.71
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Serial communications interface (SCI)
159/247
Table 79. SCI register map and reset values
Address (Hex.)Register label76543210
0050h SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0051h SCIDR
Reset value
MSB
xxxxxxx
LSB
x
0052h SCIBRR
Reset value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
0053h SCICR1
Reset value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
0054h SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
0055h SCIERPR
Reset value
MSB
0000000
LSB
0
0057h SCIPETPR
Reset value
MSB
0000000
LSB
0
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
160/247
16 I2C bus interface (I2C)
16.1 Introduction
The I2C bus interface serves as an interface between the microcontroller and the serial I2C
bus. It provides both multimaster and slave functions, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz).
16.2 Main features
●Parallel-bus/I2C protocol converter
●Multimaster capability
●7-bit/10-bit addressing
●SMBus V1.1 compliant
●Transmitter/Receiver flag
●End-of-byte transmission flag
●Transfer problem detection
16.2.1 I2C master features
●Clock generation
●I2C bus busy flag
●Arbitration Lost flag
●End of byte transmission flag
●Transmitter/Receiver flag
●Start bit detection flag
●Start and Stop generation
16.2.2 I2C slave features
●Stop bit detection
●I2C bus busy flag
●Detection of misplaced start or stop condition
●Programmable I2C address detection
●Transfer problem detection
●End-of-byte transmission flag
●Transmitter/Receiver flag
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
161/247
16.3 General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
enabled or disabled by software. The interface is connected to the I2C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a
fast I2C bus. This selection is made by software.
16.3.1 Mode selection
The interface can operate in the four following modes:
●Slave transmitter/receiver
●Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multimaster capability.
16.3.2 Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7- or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 66.
Figure 66. I2C bus protocol
Acknowledge may be enabled and disabled by software.
The I2C interface address and/or general call address can be selected by software.
The speed of the I2C interface may be selected between standard (up to 100 kHz) and fast
I2C (up to 400 kHz).
SCL
SDA
12 8 9
MSB ACK
STOP
START
CONDITION
CONDITION VR02119B
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
162/247
16.3.3 SDA/SCL line control
Transmitter mode
The interface holds the clock line low before transmission to wait for the microcontroller to
write the byte in the data register.
Receiver mode
The interface holds the clock line low after reception to wait for the microcontroller to read
the byte in the data register.
The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on
the I2C bus mode.
When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 67. I2C interface block diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
CLOCK CONTROL REGISTER (CCR)
STATUS REGISTER 1 (SR1)
CONTROL REGISTER (CR)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL or SCLI
SDA or SDAI
OWN ADDRESS REGISTER 2 (OAR2)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
163/247
16.4 Functional description
Refer to the CR, SR1 and SR2 registers in Section 16.7 for the bit definitions.
By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
16.4.1 Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
Header matched (10-bit mode only): The interface generates an acknowledge pulse if the
ACK bit is set.
Address not matched: The interface ignores it and waits for another Start condition.
Address matched: The interface generates in sequence:
●an acknowledge pulse if the ACK bit is set
●EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 68: Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after the SR1 register has been read, the slave
receives bytes from the SDA line into the DR register via the internal shift register. After
each byte the interface generates in sequence:
●an acknowledge pulse if the ACK bit is set
●EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 68: Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 68: Transfer sequencing EV3).
When the acknowledge pulse is received:
●The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
164/247
Closing slave communication
After the last data byte is transferred, a Stop Condition is generated by the master. The
interface detects this condition and sets:
●EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 68: Transfer sequencing
EV4).
Error cases
●BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
●AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note: In case of errors, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. While AF = 1, the SCL line may be held low due to SB or BTF
flags that are set at the same time. It is then necessary to release both lines by software.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
The ST7 I2C is compatible with the SMBus V1.1 protocol. It supports all SMBus addressing
modes, SMBus bus protocols and CRC-8 packet error checking. Refer to SMBus Slave
Driver For ST7 I2C Peripheral (AN1713).
16.4.2 Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
●The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 68: Transfer sequencing
EV5).
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
165/247
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
●In 7-bit addressing mode, one address byte is sent.
●In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event:
– The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 68: Transfer sequencing EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
●The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 68: Transfer sequencing
EV6).
Next, the master must enter Receiver or Transmitter mode.
Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●Acknowledge pulse if the ACK bit is set
●EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 68: Transfer sequencing EV7).
To close the communication: Before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 68: Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
●EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: After writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
166/247
Error cases
●BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first or second pulse of
each 9-bit transaction:
–Single Master Mode
If a Start or Stop is issued during the first or second pulse of a 9-bit transaction,
the BERR flag will not be set and transfer will continue however the BUSY flag will
be reset. To work around this, slave devices should issue a NACK when they
receive a misplaced Start or Stop. The reception of a NACK or BUSY by the
master in the middle of communication makes it possible to re-initiate
transmission.
–Multimaster Mode
Normally the BERR bit would be set whenever unauthorized transmission takes
place while transfer is already in progress. However, an issue will arise if an
external master generates an unauthorized Start or Stop while the I2C master is
on the first or second pulse of a 9-bit transaction. It is possible to work around this
by polling the BUSY bit during I2C master mode transmission. The resetting of the
BUSY bit can then be handled in a similar manner as the BERR flag being set.
●AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
●ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to
possible ‘0’ bits transmitted last. It is then necessary to release both lines by software.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
167/247
Figure 68. Transfer sequencing
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter:
10-bit Master transmitter:
10-bit Master receiver:
S Address A Data1 A Data2 A ..... DataN A P
EV1 EV2 EV2 EV2 EV4
S Address A Data1 A Data2 A ..... DataN NA P
EV1 EV3 EV3 EV3 EV3-1 EV4
S Address A Data1 A Data2 A ..... DataN NA P
EV5 EV6 EV7 EV7 EV7
S Address A Data1 A Data2 A ..... DataN A P
EV5 EV6 EV8 EV8 EV8 EV8
S Header A Address A Data1 A ..... DataN A P
EV1 EV2 EV2 EV4
SrHeader A Data1 A ....
.
DataN A P
EV1 EV3 EV3 EV3-1 EV4
S Header A Address A Data1 A ..... DataN A P
EV5 EV9 EV6 EV8 EV8 EV8
SrHeader A Data1 A ..... DataN A P
EV5 EV6 EV7 EV7
Legend:
S = Start, Sr = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITE = 1)
EV1: EVF = 1, ADSL = 1, cleared by reading SR1 register.
EV2: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF = 1, AF = 1, BTF = 1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP = 1, STOP = 0) or
by writing DR register (DR = FFh). Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen.
EV4: EVF = 1, STOPF = 1, cleared by reading SR2 register.
EV5: EVF = 1, SB = 1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF = 1, cleared by reading SR1 register followed by writing CR register (for example PE = 1).
EV7: EVF = 1, BTF = 1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF = 1, BTF = 1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF = 1, ADD10 = 1, cleared by reading SR1 register followed by writing DR register.
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
168/247
16.5 Low power modes
16.6 Interrupts
Figure 69. Interrupt control logic diagram
Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control bit is set and the I-bit in the
CC register is reset (RIM instruction).
Table 80. Effect of low power modes on I2C
Mode Effect
Wait No effect on I2C interface.
I2C interrupts cause the device to exit from Wait mode.
Halt
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus. The
I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from
Halt mode” capability.
Table 81. I2C interrupt control/wake-up capability
Interrupt event Event flag Enable
control bit
Exit from
Wait
Exit from
Halt
10-bit Address Sent Event (Master mode) ADD10
ITE Yes No
End of Byte Transfer Event BTF
Address Matched Event (Slave mode) ADSEL
Start Bit Generation Event (Master mode) SB
Acknowledge Failure Event AF
Stop Detection Event (Slave mode) STOPF
Arbitration Lost Event (Multimaster configuration) ARLO
Bus Error Event BERR
BTF
ADSL
SB
AF
STOPF
ARLO
BERR EVF
INTERRUPT
ITE
*
* EVF can also be set by EV6 or an error from the SR2 register.
ADD10
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
169/247
16.7 Register description
16.7.1 I2C control register (CR)
CR Reset value: 0000 0000 (00h)
76543210
Reserved PE ENGC START ACK STOP ITE
- RWRWRWRWRWRW
Table 82. CR register description
Bit Name Function
7:6 - Reserved. Forced to 0 by hardware.
5PE
Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Notes:
- When PE = 0, all the bits of the CR register and the SR register except the Stop
bit are reset. All outputs are released while PE = 0
- When PE = 1, the corresponding I/O pins are selected by hardware as alternate
functions.
To enable the I2C interface, write the CR register TWICE with PE = 1 as the first
write only activates the interface (only PE is set).
4ENGC
Enable General Call
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0). The 00h General Call address is acknowledged (01h
ignored).
0: General Call disabled
1: General Call enabled
Note: In accordance with the I2C standard, when GCAL addressing is enabled, an
I2C slave can only receive data. It will not transmit data to the master.
3START
Generation of a Start condition
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0) or when the Start condition is sent (with interrupt
generation if ITE = 1).
In Master mode
0: No start generation
1: Repeated start generation
In Slave mode
0: No start generation
1: Start generation when the bus is free
2ACK
Acknowledge enable
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE = 0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
170/247
16.7.2 I2C status register 1 (SR1)
1STOP
Generation of a Stop condition
This bit is set and cleared by software. It is also cleared by hardware in master
mode.
Note: This bit is not cleared when the interface is disabled (PE = 0).
In Master mode
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition
is sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In Slave mode
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF = 1). In this
mode the STOP bit has to be cleared by software.
0ITE
Interrupt enable
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE = 0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 69 and Ta b l e 8 1 for the relationship between the events and the
interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see
Figure 68) is detected.
Table 82. CR register description (continued)
Bit Name Function
SR1 Reset value: 0000 0000 (00h)
76543210
EVF ADD10 TRA BUSY BTF ADSL M/SL SB
RO RO RO RO RO RO RO RO
Table 83. SR1 register description
Bit Name Function
7EVF
Event flag
This bit is set by hardware as soon as an event occurs. It is cleared by software
reading SR2 register in case of error event or as described in Figure 68. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No event
1: One of the following events has occurred:
- BTF = 1 (Byte received or transmitted)
- ADSL = 1 (Address matched in Slave mode while ACK = 1)
- SB = 1 (Start condition generated in Master mode)
- AF = 1 (No acknowledge received after byte transmission)
- STOPF = 1 (Stop condition detected in Slave mode)
- ARLO = 1 (Arbitration lost in Master mode)
- BERR = 1 (Bus error, misplaced Start or Stop condition detected)
- ADD10 = 1 (Master has sent header byte)
- Address byte successfully transmitted in Master mode
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
171/247
6 ADD10
10-bit addressing in Master mode
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the
peripheral is disabled (PE = 0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
5TRA
Transmitter/Receiver
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared
automatically when BTF is cleared. It is also cleared by hardware after detection of
Stop condition (STOPF = 1), loss of bus arbitration (ARLO = 1) or when the
interface is disabled (PE = 0).
0: Data byte received (if BTF = 1)
1: Data byte transmitted
4BUSY
Bus busy
This bit is set by hardware on detection of a Start condition and cleared by hardware
on detection of a Stop condition. It indicates a communication in progress on the
bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Note: The BUSY flag is NOT updated when the interface is disabled (PE = 0). This
can have consequences when operating in Multimaster mode; that is, a second
active I2C master commencing a transfer with an unset BUSY bit can cause a
conflict resulting in lost data. A software workaround consists of checking that the
I2C is not busy before enabling the I2C Multimaster cell.
3BTF
Byte transfer finished
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE = 1. It is cleared by software reading SR1 register
followed by a read or write of DR register. It is also cleared by hardware when the
interface is disabled (PE = 0).
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event (see
Figure 68). BTF is cleared by reading SR1 register followed by writing the next byte
in DR register.
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK = 1. BTF is cleared by reading SR1 register followed by reading the
byte from DR register.
The SCL line is held low while BTF = 1.
0: Byte transfer not done
1: Byte transfer succeeded
2ADSL
Address matched (Slave mode)
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if
ITE = 1. It is cleared by software reading SR1 register or by hardware when the
interface is disabled (PE = 0).
The SCL line is held low while ADSL = 1.
0: Address mismatched or not received
1: Received address matched
Table 83. SR1 register description (continued)
Bit Name Function
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
172/247
16.7.3 I2C status register 2 (SR2)
1M/SL
Master/Slave
This bit is set by hardware as soon as the interface is in Master mode (writing
START = 1). It is cleared by hardware after detecting a Stop condition on the bus or
a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled
(PE = 0).
0: Slave mode
1: Master mode
0SB
Start bit (Master mode)
This bit is set by hardware as soon as the Start condition is generated (following a
write START = 1). An interrupt is generated if ITE = 1. It is cleared by software
reading SR1 register followed by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No Start condition
1: Start condition generated
Table 83. SR1 register description (continued)
Bit Name Function
SR2 Reset value: 0000 0000 (00h)
76543210
Reserved AF STOPF ARLO BERR GCAL
- RORORORORO
Table 84. SR2 register description
Bit Name Function
7:5 - Reserved. Forced to 0 by hardware.
4AF
Acknowledge failure
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE = 1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE = 0).
The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set
at the same time.
0: No acknowledge failure
1: Acknowledge failure
Note: When an AF event occurs, the SCL line is not held low; however, the SDA line
can remain low if the last bits transmitted are all 0. It is then necessary to release
both lines by software.
3STOPF
Stop detection (Slave mode)
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE = 0).
The SCL line is not held low while STOPF = 1.
0: No Stop condition detected
1: Stop condition detected
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
173/247
16.7.4 I2C clock control register (CCR)
2ARLO
Arbitration lost
This bit is set by hardware when the interface loses the arbitration of the bus to
another master. An interrupt is generated if ITE = 1. It is cleared by software reading
SR2 register or by hardware when the interface is disabled (PE = 0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL = 0).
The SCL line is not held low while ARLO = 1.
0: No arbitration lost detected
1: Arbitration lost detected
Note: In a Multimaster environment, when the interface is configured in Master
Receive mode it does not perform arbitration during the reception of the
Acknowledge bit. Mishandling of the ARLO bit from the I2CSR2 register may occur
when a second master simultaneously requests the same data from the same slave
and the I2C master does not acknowledge the data. The ARLO bit is then left at 0
instead of being set.
1BERR
Bus error
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE = 1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE = 0).
The SCL line is not held low while BERR = 1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note: If a Bus Error occurs, a Stop or a repeated Start condition should be
generated by the Master to re-synchronize communication, get the transmission
acknowledged and the bus released for further communication.
0GCAL
General Call (Slave mode)
This bit is set by hardware when a general call address is detected on the bus while
ENGC = 1. It is cleared by hardware detecting a Stop condition (STOPF = 1) or
when the interface is disabled (PE = 0).
0: No general call address detected on bus
1: General call address detected on bus
Table 84. SR2 register description (continued)
Bit Name Function
CCR Reset value: 0000 0000 (00h)
76543210
FM/SM CC[6:0]
RW RW
Table 85. CCR register description
Bit Name Function
7FM/SM
Fast/Standard I2C mode
This bit is set and cleared by software. It is not cleared when the interface is
disabled (PE = 0).
0: Standard I2C mode
1: Fast I2C mode
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
174/247
16.7.5 I2C data register (DR)
16.7.6 I2C own address register (OAR1)
6:0 CC[6:0]
7-bit clock divider
These bits select the speed of the bus (fSCL) depending on the I2C mode. They are
not cleared when the interface is disabled (PE = 0).
Refer to the Electrical characteristics chapter for the table of values.
Note: The programmed fSCL assumes no load on SCL and SDA lines.
Table 85. CCR register description (continued)
Bit Name Function
DR Reset value: 0000 0000 (00h)
76543210
D[7:0]
RW
Table 86. DR register description
Bit Name Function
7:0 D[7:0]
8-bit Data Register
These bits contain the byte to be received or transmitted on the bus.
Transmitter mode: Byte transmission start automatically when the software writes
in the DR register.
Receiver mode: The first data byte is received automatically in the DR register
using the least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR
register.
OAR1 Reset value: 0000 0000 (00h)
76543210
ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
RW RW RW RW RW RW RW RW
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto I2C bus interface (I2C)
175/247
16.7.7 I2C own address register (OAR2)
Table 87. OAR1 register description
Bit Name
Function
7-bit addressing mode 10-bit addressing mode
7:1 ADD[7:1]
Interface address
These bits define the I2C bus address
of the interface. They are not cleared
when the interface is disabled
(PE = 0).
Not applicable
0 ADD0
Address direction bit
This bit is ‘don’t care’, the interface
acknowledges either 0 or 1. It is not
cleared when the interface is disabled
(PE = 0).
Address 01h is always ignored.
7:0 ADD[7:0] Not applicable
Interface address
These are the least significant bits of
the I2C bus address of the interface.
They are not cleared when the
interface is disabled (PE = 0).
OAR2 Reset value: 0100 0000 (40h)
76543210
FR[1:0] Reserved ADD[9:8] Reserved
RW - RW -
Table 88. OAR2 register description
Bit Name Function
7:6 FR[1:0]
Frequency bits
These bits are set by software only when the interface is disabled (PE = 0). To
configure the interface to I2C specified delays, select the value corresponding to
the CPU frequency fCPU.
00: fCPU < 6 MHz
01: fCPU = 6 to 8 MHz
5:3 - Reserved
2:1 ADD[9:8]
Interface address
These are the most significant bits of the I2C bus address of the interface (10-bit
mode only). They are not cleared when the interface is disabled (PE = 0).
0-Reserved
Obsolete Product(s) - Obsolete Product(s)
I2C bus interface (I2C) ST72321Bxxx-Auto
176/247
Table 89. I2C register map and reset values
Address
(Hex.)
Register
label 76543210
0018h I2CCR
Reset value 0 0
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0019h I2CSR1
Reset value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
001Ah I2CSR2
Reset value000
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
001Bh I2CCCR
Reset value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
001Ch I2COAR1
Reset value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
001Dh I2COAR2
Reset value
FR1
0
FR0
1000
ADD9
0
ADD8
00
001Eh I2CDR
Reset value
MSB
0000000
LSB
0
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 10-bit A/D converter (ADC)
177/247
17 10-bit A/D converter (ADC)
17.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pin out description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit data register. The A/D converter is
controlled through a control/status register.
17.2 Main features
●10-bit conversion
●Up to 16 channels with multiplexed input
●Linear successive approximation
●Data register (DR) which contains the results
●Conversion complete status flag
●On/off bit (to reduce consumption)
The block diagram is shown in Figure 70.
Figure 70. ADC block diagram
CH2 CH1EOC SPEED ADON 0 CH0 ADCCSR
AIN0
AIN1 ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
D4 D3D5D9 D8 D7 D6 D2
ADCDRH
4
DIV 4
fADC
fCPU
D1 D0
ADCDRL
0
1
00 00 00
CH3
DIV 2
Obsolete Product(s) - Obsolete Product(s)
10-bit A/D converter (ADC) ST72321Bxxx-Auto
178/247
17.3 Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Chapter 19:
Electrical characteristics.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
17.3.1 A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
Chapter 9: I/O ports. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
●Select the CS[3:0] bits to assign the analog channel to convert.
17.3.2 Starting the conversion
In the ADCCSR register:
●Set the ADON bit to enable the A/D converter and to start the conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●The EOC bit is set by hardware.
●The result is in the ADCDR registers.
A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit.
To read the 10 bits, perform the following steps:
1. Poll the EOC bit.
2. Read the ADCDRL register.
3. Read the ADCDRH register. This clears EOC automatically.
Note: The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit.
2. Read the ADCDRH register. This clears EOC automatically.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 10-bit A/D converter (ADC)
179/247
17.3.3 Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
17.4 Low power modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
17.5 Interrupts
None.
17.6 ADC registers
17.6.1 Control/status register (ADCCSR)
Table 90. Effect of low power modes on ADC
Mode Effect
Wait No effect on A/D converter
Halt
A/D converter disabled.
After wake-up from Halt mode, the A/D converter requires a stabilization time tSTAB (see
Electrical characteristics) before accurate conversions can be performed.
ADCCSR Reset value: 0000 0000 (00h)
76 543210
EOC SPEED ADON Reserved CH[3:0]
RO RW RW - RW
Table 91. ADCCSR register description
Bit Name Function
7EOC
End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
6 SPEED
ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
Obsolete Product(s) - Obsolete Product(s)
10-bit A/D converter (ADC) ST72321Bxxx-Auto
180/247
17.6.2 Data register (ADCDRH)
5ADON
A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
4 - Reserved. Must be kept cleared
3:0 CH[3:0]
Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
0000: Channel pin = AIN0
0001: Channel pin = AIN1
0010: Channel pin = AIN2
0011: Channel pin = AIN3
0100: Channel pin = AIN4
0101: Channel pin = AIN5
0110: Channel pin = AIN6
0111: Channel pin = AIN7
1000: Channel pin = AIN8
1001: Channel pin = AIN9
1010: Channel pin = AIN10
1011: Channel pin = AIN11
1100: Channel pin = AIN12
1101: Channel pin = AIN13
1110: Channel pin = AIN14
1111: Channel pin = AIN15
Note: The number of channels is device dependent. Refer to the device pinout
description.
Table 91. ADCCSR register description (continued)
Bit Name Function
ADCDRH Reset value: 0000 0000 (00h)
76543210
D[9:2]
RO
Table 92. ADCDRH register description
Bit Name Function
7:0 D[9:2] MSB of Converted Analog Value
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto 10-bit A/D converter (ADC)
181/247
17.6.3 Data register (ADCDRL)
17.6.4 ADC register map and reset values
ADCDRL Reset value: 0000 0000 (00h)
76543210
Reserved D[1:0]
-RO
Table 93. ADCDRL register description
Bit Name Function
7:2 - Reserved. Forced by hardware to 0.
1:0 D[1:0] LSB of Converted Analog Value
Table 94. ADC register map and reset values
Address
(Hex.)
Register
label 76543210
0070h ADCCSR
Reset value
EOC
0
SPEED
0
ADON
00
CH3
0
CH2
0
CH1
0
CH0
0
0071h ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0072h ADCDRL
Reset value000000
D1
0
D0
0
Obsolete Product(s) - Obsolete Product(s)
Instruction set ST72321Bxxx-Auto
182/247
18 Instruction set
18.1 CPU addressing modes
The CPU features 17 different addressing modes which can be classified in seven main
groups as listed in the following table:
The CPU instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be divided in two submodes called
long and short:
●Long addressing mode is more powerful because it can use the full 64 Kbyte address
space; however, it uses more bytes and more CPU cycles.
●Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 95. Addressing modes
Group Example
Inherent NOP
Immediate LD A,#$55
Direct LD A,$55
Indexed LD A,($55,X)
Indirect LD A,([$55],X)
Relative JRNE loop
Bit operation BSET byte,#5
Table 96. CPU addressing mode overview
Mode Syntax Destination
Pointer
address
(Hex.)
Pointer
size
(Hex.)
Length
(bytes)
Inherent nop + 0
Immediate ld A,#$55 + 1
Short Direct ld A,$10 00..FF + 1
Long Direct ld A,$1000 0000..FFFF + 2
No Offset Direct Indexed ld A,(X) 00..FF + 0
Short Direct Indexed ld A,($10,X) 00..1FE + 1
Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2
Short Indirect ld A,[$10] 00..FF 00..FF byte + 2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Instruction set
183/247
18.1.1 Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2
Relative Direct jrne loop PC+/-127 + 1
Relative Indirect jrne [$10] PC+/-127 00..FF byte + 2
Bit Direct bset $10,#7 00..FF + 1
Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2
Bit Direct Relative btjt $10,#7,skip 00..FF + 2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3
Table 96. CPU addressing mode overview (continued)
Mode Syntax Destination
Pointer
address
(Hex.)
Pointer
size
(Hex.)
Length
(bytes)
Table 97. Inherent instructions
Instruction Function
NOP No operation
TRAP S/W Interrupt
WFI Wait For Interrupt (Low Power Mode)
HALT Halt Oscillator (Lowest Power Mode)
RET Sub-routine Return
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask (level 3)
RIM Reset Interrupt Mask (level 0)
SCF Set Carry Flag
RCF Reset Carry Flag
RSP Reset Stack Pointer
LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
MUL Byte Multiplication
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP Swap Nibbles
Obsolete Product(s) - Obsolete Product(s)
Instruction set ST72321Bxxx-Auto
184/247
18.1.2 Immediate
Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte
contains the operand value.
18.1.3 Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF
addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after
the opcode.
18.1.4 Indexed (no offset, short, long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indexed addressing mode consists of three submodes:
Indexed (no offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed (short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE
addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the
opcode.
Table 98. Immediate instructions
Instruction Function
LD Load
CP Compare
BCP Bit Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC Arithmetic Operations
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Instruction set
185/247
18.1.5 Indirect (short, long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
18.1.6 Indirect indexed (short, long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect indexed (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect indexed (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing
space, and requires 1 byte after the opcode.
Table 99. Instructions supporting direct, indexed, indirect, and indirect indexed
addressing modes
Type Instruction Function
Long and short instructions
LD Load
CP Compare
AND, OR, XOR Logical operations
ADC, ADD, SUB, SBC Arithmetic Additions/Subtractions
operations
BCP Bit Compare
Obsolete Product(s) - Obsolete Product(s)
Instruction set ST72321Bxxx-Auto
186/247
18.1.7 Relative (direct, indirect)
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it.
The relative addressing mode consists of two submodes:
Relative (direct)
The offset is following the opcode.
Relative (indirect)
The offset is defined in memory, which address follows the opcode.
18.2 Instruction groups
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Short instructions only
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
BTJT, BTJF Bit Test and Jump Operations
SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
Table 99. Instructions supporting direct, indexed, indirect, and indirect indexed
addressing modes (continued)
Type Instruction Function
Table 100. Available relative direct/indirect instructions
Instruction Function
JRxx Conditional Jump
CALLR Call Relative
Table 101. Instruction groups
Group Instructions
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Instruction set
187/247
18.2.1 Using a prebyte
The instructions are described with one to four opcodes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC - 2 End of previous instruction
PC - 1 Prebyte
PC Opcode
PC + 1 Additional word (0 to 2) according to the number of bytes required to
compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or
inherent addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative
addressing mode to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to an
instruction using indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y
one.
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF
Table 101. Instruction groups (continued)
Group Instructions
Obsolete Product(s) - Obsolete Product(s)
Instruction set ST72321Bxxx-Auto
188/247
Table 102. Instruction set overview
Mnemo Description Function/Example Dst Src I1 H I0 N Z C
ADC Add with Carry A = A + M + C A M H N Z C
ADD Addition A = A + M A M H N Z C
AND Logical And A = A . M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 10
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if ext. INT pin = 1 (ext. INT pin high)
JRIL Jump if ext. INT pin = 0 (ext. INT pin low)
JRH Jump if H = 1 H = 1 ?
JRNH Jump if H = 0 H = 0 ?
JRM Jump if I1:0 = 11 I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
JRMI Jump if N = 1 (minus) N = 1 ?
JRPL Jump if N = 0 (plus) N = 0 ?
JREQ Jump if Z = 1 (equal) Z = 1 ?
JRNE Jump if Z = 0 (not equal) Z = 0 ?
JRC Jump if C = 1 C = 1 ?
JRNC Jump if C = 0 C = 0 ?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Instruction set
189/247
JRUGT Jump if (C + Z = 0) Unsigned >
JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2's compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A = A + M A M N Z
POP Pop from the Stack pop reg reg M
pop CC CC M I1 H I0 N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C = 0 0
RET Subroutine Return
RIM Enable Interrupts I1:0 = 10 (level 0) 1 0
RLC Rotate left true C C <= A <= C reg, M N Z C
RRC Rotate right true C C => A => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Subtract with Carry A = A - M - C A M N Z C
SCF Set carry flag C = 1 1
SIM Disable Interrupts I1:0 = 11 (level 3) 1 1
SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C
SLL Shift left Logic C <= A <= 0 reg, M N Z C
SRL Shift right Logic 0 => A => C reg, M 0 Z C
SRA Shift right Arithmetic A7 => A => C reg, M N Z C
SUB Subtraction A = A - M A M N Z C
SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1 1
WFI Wait for Interrupt 1 0
XOR Exclusive OR A = A XOR M A M N Z
Table 102. Instruction set overview (continued)
Mnemo Description Function/Example Dst Src I1 H I0 N Z C
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
190/223
19 Electrical characteristics
19.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
19.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA= 25°C and TA=T
Amax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3Σ).
19.1.2 Typical values
Unless otherwise specified, typical data is based on TA=25°C, V
DD = 5V. The typical values
are given only as design guidelines and are not tested.
19.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
19.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 71.
Figure 71. Pin loading conditions
19.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 72.
Figure 72. Pin input voltage
CL
ST7 PIN
VIN
ST7 PIN
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
191/223
19.2 Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
19.2.1 Voltage characteristics
Table 103. Voltage characteristics
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 6.5
V
VPP - VSS Programming voltage 13
VIN(1) Input voltage on true open-drain pin VSS - 0.3 to 6.5
Input voltage on any other pin VSS - 0.3 to VDD +0.3
|∆VDDx| and |∆VSSx| Variations between different digital power pins 50 mV
|VSSA - VSSx| Variations between digital and analog ground pins 50
VESD(HBM) Electrostatic discharge voltage (Human Body Model) See Section 19.7.3 on page 206.
VESD(MM) Electrostatic discharge voltage (Machine Model)
1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is
generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To
guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET,
10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
192/223
19.2.2 Current characteristics
19.2.3 Thermal characteristics
Table 104. Current characteristics
Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source)(1)
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.
150 mA
IVSS Total current out of VSS ground lines (sink)(1)
IIO
Output current sunk by any standard I/O and control pin 20
mA
Output current sunk by any high sink I/O pin 40
Output current source by any I/Os and control pin - 25
IINJ(PIN)(2)(3)
2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN >V
DD while a negative injection is induced by VIN <V
SS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected.
3. Negative injection may disturb the analog performance of the device. See Note 1 in Table 135: ADC
accuracy on page 223.
Injected current on VPP pin ± 5
Injected current on RESET pin ± 5
Injected current on OSC1 and OSC2 pins ± 5
Injected current on PC6 pin (Flash devices only) + 5
Injected current on any other pin(4)(5)
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5. True open-drain I/O port pins do not accept positive injection.
± 5
ΣIINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25
Table 105. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150 °C
TJMaximum junction temperature (see Section 20.2: Thermal characteristics on page 227)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
193/223
19.3 Operating conditions
19.3.1 General operating conditions
Figure 73. fCPU max versus VDD
Table 106. General operating conditions
Symbol Parameter Conditions Min Max Unit
fCPU Internal clock frequency 0 8 MHz
VDD
Standard voltage range (except Flash
Write/Erase) 3.8 5.5 V
Operating voltage for Flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5
TAAmbient temperature range
A suffix version
-40
85
°CB suffix version(1)
1. Available only on ROM and FASTROM devices. Refer to Section 21.2: ROM device ordering information
and transfer of customer code on page 232.
105
C suffix version 125
fCPU [MHz]
SUPPLY VOLTAGE [V]
8
4
2
1
0
3.5 4.0 4.5 5.5
FUNCTIONALITY
FUNCTIONALITY
GUARANTEED
IN THIS AREA
NOT GUARANTEED
IN THIS AREA
3.8
6 (UNLESS
OTHERWISE
SPECIFIED
IN THE TABLES
OF PARAMETRIC
DATA)
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
194/223
19.3.2 Operating conditions with low voltage detector (LVD)
Subject to general operating conditions for VDD, fCPU, and TA.
19.3.3 Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Table 107. Operating conditions with low voltage detector (LVD)
Symbol Parameter Conditions Min Typ Max Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
VD level = High in option byte 4.0(1) 4.2 4.5
V
VD level = Med. in option byte(2) 3.55(1) 3.75 4.0(1)
VD level = Low in option byte(2) 2.95(1) 3.15 3.35(1)
VIT-(LVD)
Reset generation threshold
(VDD fall)
VD level = High in option byte 3.8 4.0 4.25(1)
VD level = Med. in option byte(2) 3.35(1) 3.55 3.75(1)
VD level = Low in option byte(2) 2.8(1) 3.0 3.15(1)
Vhys(LVD)
LVD voltage threshold
hysteresis VIT+(LVD)-VIT-(LVD) 200 mV
VtPOR VDD rise time(2)(3) LVD enabled 6µs/V 100ms/V -
tg(VDD)
VDD glitches filtered (not
detected) by LVD(4) 40 ns
1. Data based on characterization results, tested in production for ROM devices only
2. Data based on characterization results, not tested in production
3. When VtPOR is faster than 100µs/V, the Reset signal is released after a delay of maximum 42µs after VDD crosses the
VIT+(LVD) threshold.
4. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range. Below
3.8V, device operation is not guaranteed.
Table 108. Auxiliary voltage detector (AVD) thresholds
Symbol Parameter Conditions Min Typ Max Unit
VIT+(AVD)
1⇒0 AVDF flag toggle threshold
(VDD rise)
VD level = High in option byte 4.4(1) 4.6 4.9(1)
V
VD level = Med. in option byte 3.95(1) 4.15 4.4(1)
VD level = Low in option byte 3.4(1) 3.6 3.8(1)
VIT-(AVD)
0⇒1 AVDF flag toggle threshold
(VDD fall)
VD level = High in option byte 4.2(1) 4.4 4.65(1)
VD level = Med. in option byte 3.75(1) 4.0 4.2(1)
VD level = Low in option byte 3.2(1) 3.4 3.6(1)
Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200
mV
∆VIT-
Voltage drop between AVD flag set
and LVD reset activated VIT-(AVD)-VIT-(LVD) 450
1. Data based on characterization results, tested in production for ROM devices only
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
195/223
19.3.4 External voltage detector (EVD) thresholds
Subject to general operating conditions for VDD, fCPU, and TA.
Table 109. External voltage detector (EVD) thresholds
Symbol Parameter Conditions Min Typ Max Unit
VIT+(EVD) 1⇒0 AVDF flag toggle threshold (VDD rise(1) 1.15 1.26 1.35 V
VIT-(EVD) 0⇒1 AVDF flag toggle threshold (VDD fall)(1) 1.1 1.2 1.3
Vhys(EVD) EVD voltage threshold hysteresis VIT+(EVD)-VIT-(EVD) 200 mV
1. Data based on characterization results, not tested in production
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
196/223
19.4 Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for Halt
mode, for which the clock is stopped).
19.4.1 Current consumption
Table 110. Current consumption
Symbol Parameter Conditions
Flash devices ROM devices
Unit
Typ Max(1) Typ Max(1)
IDD
Supply current in Run
mode(2)
fOSC = 2 MHz, fCPU =1MHz
fOSC = 4 MHz, fCPU =2MHz
fOSC = 8 MHz, fCPU =4MHz
fOSC =16MHz, f
CPU =8MHz
1.3
2.0
3.6
7.1
3.0
5.0
8.0
15.0
0.5
1.2
2.2
4.8
1.0
2.0
4.0
8.0
mA
Supply current in Slow
mode(2)
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
fOSC =16MHz, f
CPU =500kHz
600
700
800
1100
2700
3000
3600
4000
100
200
300
500
600
700
800
950
µA
Supply current in Wait
mode(2)
fOSC = 2 MHz, fCPU =1MHz
fOSC = 4 MHz, fCPU =2MHz
fOSC = 8 MHz, fCPU =4MHz
fOSC =16MHz, f
CPU =8MHz
0.8
1.2
2.0
3.5
3.0
4.0
5.0
7.0
0.5
0.8
1.5
3.0
1.0
1.3
2.2
4.0
mA
Supply current in Slow Wait
mode(2)
fOSC = 2 MHz, fCPU = 62.5 kHz
fOSC = 4 MHz, fCPU = 125 kHz
fOSC = 8 MHz, fCPU = 250 kHz
fOSC =16MHz, f
CPU =500kHz
580
650
770
1050
1200
1300
1800
2000
50
90
180
350
100
150
300
600
µA
Supply current in Halt
mode(3)
-40°C < TA<+85°C <1 10 <1 10 µA
-40°C < TA<+125°C 5 50 <1 50
Supply current in Active Halt
mode(4)
fOSC =2MHz
fOSC =4MHz
fOSC =8MHz
fOSC =16MHz
415
430
460
550
525
550
600
700
15
30
60
120
25
50
100
200
µA
1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. Measurements are done in the following conditions:
- Program executed from RAM, CPU running with RAM access
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals in reset state
- LVD disabled
- Clock input (OSC1) driven by external square wave
- In Slow and Slow Wait mode, fCPU is based on fOSC divided by 32
- To obtain the total current consumption of the device, add the clock source (Section 19.4.2) and the peripheral power
consumption (Section 19.4.3).
3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data based on
characterization results, tested in production at VDD max. and fCPU max.
4. Data based on characterization results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with a
static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the total
current consumption of the device, add the clock source consumption (Section 19.4.2).
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
197/223
19.4.2 Supply and clock managers
The previous current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To
obtain the total device consumption, the two current values must be added (except for Halt
mode).
Table 111. Oscillators, PLL and LVD current consumption
Symbol Parameter Conditions Typ Max Unit
IDD(RCINT) Supply current of internal RC oscillator 625
µA
IDD(RES)
Supply current of resonator
oscillator(1)(2)
1. Data based on characterization results done with the external components specified in Section 19.5.3, not
tested in production
2. As the oscillator is based on a current source, the consumption does not depend on the voltage.
see section 19.5.3 on page
200
IDD(PLL) PLL supply current VDD = 5V 360
IDD(LVD) LVD supply current 150 300
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
198/223
19.4.3 On-chip peripherals
Measured on LQFP64 generic board TA = 25°C, fCPU =4MHz.
Table 112. On-chip peripherals current consumption
Symbol Parameter Conditions Typ Unit
IDD(TIM) 16-bit timer supply current(1)
1. Data based on a differential IDD measurement between reset configuration (timer counter running at
fCPU/4) and timer counter stopped (only TIMD bit set). Data valid for one timer.
VDD =5.0V 50 µA
IDD(ART) ART PWM supply current(2)
2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer
counter enabled (only TCE bit set).
VDD =5.0V 75 µA
IDD(SPI) SPI supply current(3)
3. Data based on a differential IDD measurement between reset configuration (SPI disabled) and a permanent
SPI master communication at maximum speed (data sent equal to 55h). This measurement includes the
pad toggling consumption.
VDD =5.0V 400 µA
IDD(SCI) SCI supply current(4)
4. Data based on a differential IDD measurement between SCI low power state (SCID = 1) and a permanent
SCI data transmit sequence.
IDD(I2C) I2C supply current(5)
5. Data based on a differential IDD measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100 kHz (data sent equal to 55h). This measurement includes the pad
toggling consumption (27k ohm external pull-up on clock and data lines).
VDD =5.0V 175 µA
IDD(ADC) ADC supply current when converting(6)
6. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
VDD =5.0V 400 µA
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
199/223
19.5 Clock and timing characteristics
Subject to general operating conditions for VDD, fCPU, and TA.
19.5.1 General timings
19.5.2 External clock source
Figure 74. Typical application with an external clock source
Table 113. General timings
Symbol Parameter Conditions Min Typ(1)
1. Data based on typical application software.
Max Unit
tc(INST) Instruction cycle time 2312t
CPU
fCPU = 8 MHz 250 375 1500 ns
tv(IT)
Interrupt reaction time(2)
tv(IT) = ∆tc(INST) + 10
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles
needed to finish the current instruction execution.
10 22 tCPU
fCPU =8MHz 1.25 2.75 µs
Table 114. External clock source
Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage
See Figure 74
0.7xVDD VDD V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
tw(OSC1L)
OSC1 high or low time(1)
1. Data based on design simulation and/or technology characteristics, not tested in production.
5
ns
tr(OSC1)
tf(OSC1)
OSC1 rise or fall time(1) 15
Ilkg OSC1 input leakage current VSS < VIN < VDD ±1 µA
OSC1
OSC2
fOSC
EXTERNAL
ST72XXX
CLOCK SOURCE
Not connected internally
VOSC1L
VOSC1H
tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
Ilkg
90%
10%
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
200/223
19.5.3 Crystal and ceramic resonator oscillators
The ST7 internal clock can be supplied with four different crystal/ceramic resonator
oscillators. All the information given in this paragraph is based on characterization results
with specified typical external components. In the application, the resonator and the load
capacitors have to be placed as close as possible to the oscillator pins in order to minimize
output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator
manufacturer for more details (such as frequency, package or accuracy).
Figure 75. Typical application with a crystal or ceramic resonator
Table 115. Crystal and ceramic resonator oscillators
Symbol Parameter Conditions Min Typ Max Unit
fOSC Oscillator frequency(1)
1. The oscillator selection can be optimized in terms of supply current using a high-quality resonator with
small RS value. Refer to crystal/ceramic resonator manufacturer for more details.
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
1
>2
>4
>8
-
2
4
8
16
MHz
RFFeedback resistor(2)
2. Data based on characterization results, not tested in production. The relatively low value of the RF resistor
offers a good protection against issues resulting from use in a humid environment, due to the induced
leakage and the bias condition change. However, it is recommended to take this point into account if the
microcontroller is used in tough humidity conditions.
-20-40kΩ
CL1
CL2
Recommended load
capacitance versus
equivalent serial resistance of
the crystal or ceramic
resonator (RS)(3)
3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5pF to 25pF range (typ.)
designed for high-frequency applications and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included when sizing CL1 and CL2 (10pF can be used as a rough estimate of the combined pin and board
capacitance).
RS=200Ω
RS=200Ω
RS=200Ω
RS=100Ω
LP oscillator
MP oscillator
MS oscillator
HS oscillator
22
22
18
15
-
56
46
33
33
pF
i2OSC2 driving current VDD =5V, V
IN =V
SS
LP oscillator
MP oscillator
MS oscillator
HS oscillator
-
80
160
310
610
150
250
460
910
µA
OSC2
OSC1
fOSC
CL1
CL2
i2
RF
ST72XXX
RESONATOR
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
VDD/2
Ref
POWER DOWN
LOGIC
FEEDBACK
LOOP
LINEAR
AMPLIFIER
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
201/223
Figure 76. Application with a crystal or ceramic resonator for ROM (LQFP64 or any 48/60K ROM)
19.5.4 RC oscillators
Figure 77. Typical fOSC(RCINT) versus TA
OSC2
OSC1
fOSC
CL1
CL2
i2
RF
ST72XXX
RESONATOR
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
Table 116. OSCRANGE selection for typical resonators
Supplier fOSC (MHz)
Typical ceramic resonators(1)
1. Resonator characteristics given by the ceramic resonator manufacturer. For more information on these
resonators, please consult www.murata.com.
Reference Recommended OSCRANGE option bit
configuration
Murata
2 CSTCC2M00G56A-R0 MP mode(2)
2. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small
(> 0.8V).
4 CSTCR4M00G55B-R0 MS mode
8 CSTCE8M00G55A-R0 HS mode
16 CSTCE16M0G53A-R0
Table 117. RC oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC(RCINT)
Internal RC oscillator frequency
(see Figure 77)TA=25°C, V
DD =5V 2 3.5 5.6 MHz
3
3.2
3.4
3.6
3.8
4
-45 0 25 70 130
TA(°C)
fOSC(RCINT) (MHz)
Vdd = 5V
V dd = 5. 5V
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
202/223
Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling
capacitors between VDD and VSS as shown in Figure 97.
19.5.5 PLL characteristics
The user must take the PLL jitter into account in the application (for example, in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore, the longer the period of the
application signal, the less it is impacted by the PLL jitter.
Figure 78 shows the PLL jitter integrated on application signals in the range 125 kHz to
4 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
Figure 78. Integrated PLL jitter versus signal frequency(1)
1. Measurement conditions: fCPU = 8 MHz
19.6 Memory characteristics
19.6.1 RAM and hardware registers
Table 118. PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOSC PLL input frequency range 2 4 MHz
∆ fCPU/fCPU Instantaneous PLL jitter(1)
1. Data characterized but not tested
fOSC = 4 MHz 0.7 2 %
0
0.2
0.4
0.6
0.8
1
1.2
4 MHz 2 M Hz 1 MH z 500 kH z 250 kHz 125 kHz
Application Frequency
+/-Jitter (%)
FLASH typ
ROM max
ROM typ
Table 119. RAM supply voltage
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode(1)
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under RESET) or in
hardware registers (only in Halt mode). Not tested in production.
Halt mode (or RESET) 1.6 V
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
203/223
19.6.2 Flash memory
Warning: Do not connect 12V to VPP before VDD is powered on, as this
may damage the device.
Table 120. Dual voltage HDFlash memory
Symbol Parameter Conditions Min(1)
1. Data based on characterization results, not tested in production
Typ Max(1) Unit
fCPU Operating frequency Read mode 0 8 MHz
Write / Erase mode 1 8
VPP Programming voltage(2)
2. VPP must be applied only during the programming or erasing operation and not permanently for reliability
reasons.
4.5V < VDD < 5.5V 11.4 12.6 V
IDD Supply current(3)
3. Data based on simulation results, not tested in production
Run mode (fCPU = 4 MHz) 3 mA
Write / Erase 0
Power down mode / HALT 1 10 µA
IPP VPP current(3) Read (VPP = 12V) 200
Write / Erase 30 mA
tVPP
Internal VPP stabilization
time 10 µs
tRET Data retention TA=55°C 20 years
NRW Write erase cycles TA= 85°C 100 cycles
TPROG
TERASE
Programming or erasing
temperature range -40 25 85 °C
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
204/223
19.7 EMC (electromagnetic compatibility) characteristics
Susceptibility tests are performed on a sample basis during product characterization.
19.7.1 Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100pF capacitor until a functional disturbance occurs. This test conforms with
the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results given in Table 121
below are based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
205/223
.
19.7.2 EMI (electromagnetic interference)
Based on a simple application running on the product (toggling two LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 121. EMS test results
Symbol Parameter Conditions Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
All Flash and ROM devices,
VDD =5V, T
A= +25°C, fOSC =8 MHz,
conforms to IEC 1000-4-2
3B
VFFTB
Fast transient voltage burst limits to be applied
through 100pF on VDD and VDD pins to induce a
functional disturbance
32 Kbyte Flash device LQFP44(1),
VDD =5V, T
A= +25°C, fOSC = 8 MHz,
conforms to IEC 1000-4-4
3B
48/60 Kbyte Flash and all ROM devices,
VDD =5V, T
A= +25°C, fOSC = 8 MHz,
conforms to IEC 1000-4-4
4A
1. VFFTB test results unavailable for LQFP64 32 Kbyte Flash device at this time
Table 122. EMI emissions
Symbol Parameter
Conditions
Monitored
frequency band
Max vs [fOSC/fCPU](1)
Unit
VDD =5V, TA=+25°C,
conforming to SAE J 1752/3 8/4 MHz 16/8 MHz
SEMI Peak level
48/60 Kbyte Flash devices in
LQFP44 and LQFP64 packages
and
32 Kbyte Flash devices in
LQFP64 package
0.1 MHz to 30 MHz 15 20
dBµV30 MHz to 130 MHz 20 27
130MHz to 1GHz 7 12
SAE EMI Level 2.5 3 -
SEMI Peak level 32 Kbyte Flash devices in
LQFP44 package
0.1 MHz to 30 MHz 13 14
dBµV30 MHz to 130 MHz 20 25
130MHz to 1GHz 16 21
SAE EMI Level 3 3.5 -
SEMI Peak level
48/60 Kbyte ROM devices in
LQFP44 and LQFP64 packages
and
32 Kbyte ROM devices in
LQFP64 package
0.1 MHz to 30 MHz - 11
dBµV30 MHz to 130 MHz - 23
130MHz to 1GHz - 14
SAE EMI Level - 3 -
SEMI Peak level 32 Kbyte ROM devices in
LQFP44 package
0.1 MHz to 30 MHz 17 21
dBµV30 MHz to 130 MHz 24 30
130MHz to 1GHz 18 23
SAE EMI Level 3 3.5 -
1. Data based on characterization results, not tested in production.
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
206/223
19.7.3 Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note AN1181.
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin.
●A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 123. ESD absolute maximum ratings
Symbol Ratings Conditions Class Max. value(1) Unit
VESD(HBM)
Electrostatic discharge voltage
(Human Body Model)
TA = +25°C
conforming to AEC-Q100-002 H1C 2000
VVESD(MM)
Electrostatic discharge voltage
(Machine Model)
TA = +25°C
conforming to AEC-Q100-003 M2 200
VESD(CDM)
Electrostatic discharge voltage
(Charged Device Model)
TA = +25°C
conforming to AEC-Q100-011 C2 500
1. Data based on characterization results, not tested in production.
Table 124. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA=+125°C
conforming to JESD 78 II level A
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
207/223
19.8 I/O port pin characteristics
19.8.1 General characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Table 125. I/O port pin general characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage(1)
CMOS ports
0.3xVDD
VVIH Input high level voltage(1) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis(2) 0.7
IINJ(PIN)(3)
Injected current on PC6 pin (Flash devices
only)
VDD =5V
0+4
mAInjected current on an I/O pin ±4
ΣIINJ(PIN)(3) Total injected current (sum of all I/O and
control pins) ±25
Ilkg Input leakage current VSS < VIN < VDD ±1 µA
ISStatic current consumption Floating input mode(4)(5) 400
RPU Weak pull-up equivalent resistor(6) VIN =V
SS VDD = 5V 50 120 250 kΩ
CIO I/O pin capacitance 5 pF
tf(IO)out Output high to low level fall time(1) CL= 50pF
Between 10% and 90%
25 ns
tr(IO)out Output low to high level rise time(1) 25
tw(IT)in External interrupt pulse time(7) 1t
CPU
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specification. A
positive injection is induced by VIN >V
DD while a negative injection is induced by VIN <V
SS. Refer to Section 19.2.2:
Current characteristics for more details.
4. Static peak current value taken at a fixed VIN value, based on design simulation and technology characteristics, not tested
in production. This value depends on VDD and temperature values.
5. The Schmitt trigger that is connected to every I/O port is disabled for analog inputs only when ADON bit is ON and the
particular ADC channel is selected (with port configured in input floating mode). When the ADON bit is OFF, static current
consumption may result. This can be avoided by keeping the input voltage of this pin close to VDD or VSS.
6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in
Figure 80).
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
208/223
19.8.2 Output driving current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Figure 79. Unused I/O pins configured as
input
Figure 80. Typical IPU vs VDD with VIN =V
SS
10kΩ
ST7XXX
10kΩ
UNUSED I/O PORT
ST7XXX
VDD
Note: I/O can be left unconnected if it is configured as output
greater EMC robustness and lower cost.
(0 or 1) by the software. This has the advantage of
UNUSED I/O PORT
0
10
20
30
40
50
60
70
80
90
22.533.544.555.56
Vdd(V)
Ipu(uA)
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
Table 126. Output driving current
Symbol Parameter Conditions Min Max Unit
VOL(1)
Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 81)
VDD =5V
IIO =+5mA 1.2
V
IIO =+2mA 0.5
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 82 and Figure 84)
IIO = +20mA,
TA<85°C
TA>85°C
1.3
1.5
IIO =+8mA 0.6
VOH(2) Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 83 and Figure 86)
IIO =-5mA,
TA<85°C
TA>85°C
VDD -1.4
VDD -1.6
IIO =-2mA V
DD -0.7
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVDD. True open-drain I/O pins do not have VOH.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
209/223
Figure 81. Typical VOL at VDD = 5V (standard) Figure 82. Typical VOL at VDD = 5V (high-sink)
Figure 83. Typical VOH at VDD =5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.005 0.01 0.015
Iio(A)
Vol (V) at Vdd=5V
Ta=140°C "
Ta=95°C
Ta=25°C
Ta=-45°C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.01 0.02 0.03
Iio(A)
Vol(V) at Vdd=5V
Ta= 140 °C
Ta=95°C
Ta=25°C
Ta=-45°C
2
2.5
3
3.5
4
4.5
5
5.5
-0.01 -0.008 -0.006 -0.004 -0.002 0
Iio (A)
Vdd-Voh (V) at Vdd =5V
Vdd=5V 140° C min
V dd=5v 95°C m in
V dd=5v 25°C m in
V dd=5v -4 5°C m i n
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
210/223
Figure 84. Typical VOL versus VDD (standard)
Figure 85. Typical VOL versus VDD (high-sink)
Figure 86. Typical VDD-VOH versus VDD
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
Vol(V) at Iio=5mA
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
Vol(V) at Iio=2mA
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
0
0.1
0.2
0.3
0.4
0.5
0.6
22.533.544.555.56
Vdd(V)
Vol(V ) at Iio=8mA
Ta= 140°C
Ta=9 5°C
Ta=25°C
Ta=-45°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
22.533.544.555.56
Vdd(V)
Vol(V ) at I io=20mA
Ta = 1 40° C
Ta=95°C
Ta=25°C
Ta=-45°C
0
1
2
3
4
5
6
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
V dd-Voh( V) at I io= - 5m
A
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
2
2.5
3
3.5
4
4.5
5
5.5
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd(V)
Vdd-Voh(V) at Iio=-2m A
Ta=-45°C
Ta=25°C
Ta=95°C
Ta=140°C
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
211/223
19.9 Control pin characteristics
19.9.1 Asynchronous RESET pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 127. Asynchronous RESET pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage(1) 0.3xVDD
V
VIH Input high level voltage(1) 0.7xVDD
Vhys
Schmitt trigger voltage
hysteresis(2) 2.5
VOL Output low level voltage(3) VDD =5V, I
IO = +2mA 0.2 0.5
IIO Input current on RESET pin 2 mA
RON Weak pull-up equivalent resistor 20 30 120 kΩ
tw(RSTL)out Generated reset pulse duration Stretch applied on external pulse 0 42(4)
µsInternal reset sources 20 30 42(4)
th(RSTL)in External reset pulse hold time(5) 2.5
tg(RSTL)in Filtered glitch duration(6) 200 ns
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The IIO current sunk must always respect the absolute maximum rating specified in Section 19.2.2 and the sum of IIO (I/O
ports and control pins) must not exceed IVSS.
4. Data guaranteed by design, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the
RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy
environments.
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
212/223
Figure 87. RESET pin protection when LVD is enabled
Note: 1 - The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
- Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the VIL maximum level specified in Section 19.9.1 on page 211.
Otherwise the reset will not be taken into account internally.
- Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than the
absolute maximum value specified for IINJ(RESET) in Section 19.2.2 on page 192.
2 When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A
10nF pull-down capacitor is required to filter noise on the reset line.
3 In case a capacitive power supply is used, it is recommended to connect a 1M
Ω
pull-down
resistor to the RESET pin to discharge any residual voltage induced by the capacitive effect
of the power supply (this will add 5µA to the power consumption of the MCU).
4 Tips when using the LVD:
A. Check that all recommendations related to reset circuit have been applied (see notes
above).
B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a 100nF +
1M
Ω
pull-down on the RESET pin.
C. The capacitors connected on the RESET pin and also the power supply are key to avoid
any start-up marginality. In most cases, steps A and B above are sufficient for a robust
solution. Otherwise, replace 10nF pull-down on the RESET pin with a 5µF to 20µF
capacitor.
0.01µF
ST72XXX
PULSE
GENERATOR
Filter
RON
VDD
WATCHDOG
LVD RESET
INTERNAL
RESET
RESET
EXTERNAL
Required
1MΩ
Optional
(note 3)
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
213/223
Figure 88. RESET pin protection when LVD is disabled
Note: - The reset network protects the device against parasitic resets.
- The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
- Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the VIL maximum level specified in Section 19.9.1 on page 211.
Otherwise the reset will not be taken into account internally.
- Because the reset circuit is designed to allow the internal RESET to be output in the
RESET pin, the user must ensure that the current sunk on the RESET pin is less than the
absolute maximum value specified for IINJ(RESET) in Section 19.2.2 on page 192.
19.9.2 ICCSEL/VPP pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
0.01µF
EXTERNAL
RESET
CIRCUIT
USER
Required
ST72XXX
PULSE
GENERATOR
Filter
RON
VDD
WATCHDOG
INTERNAL
RESET
Table 128. ICCSEL/VPP pin characteristics
Symbol Parameter Conditions Min Max(1)
1. Data based on design simulation and/or technology characteristics, not tested in production
Unit
VIL Input low level voltage(1) VSS 0.3 x VDD V
VIH Input high level voltage(1) 0.7 x VDD VDD
Ilkg Input leakage current VIN =V
SS ±1 µA
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
214/223
Figure 89. Two typical applications with ICCSEL/VPP pin(1)
1. When ICC mode is not required by the application, the ICCSEL/VPP pin must be tied to VSS.
19.10 Timer peripheral characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (such as output compare, input capture, external clock, or
PWM output).
ICCSEL/VPP
ST72XXX 10kΩ
PROGRAMMING
TOOL
VPP
ST72XXX
Table 129. 8-bit PWM-ART auto-reload timer characteristics
Symbol Parameter Conditions Min Typ Max Unit
tres(PWM) PWM resolution time 1t
CPU
fCPU =8MHz 125 ns
fEXT ART external clock frequency 0f
CPU/2 MHz
fPWM PWM repetition rate
ResPWM PWM resolution 8 bit
VOS PWM/DAC output step voltage VDD =5V,
Resolution = 8 bits 20 mV
Table 130. 16-bit timer characteristics
Symbol Parameter Conditions Min Typ Max Unit
tw(ICAP)in Input capture pulse time 1 tCPU
tres(PWM) PWM resolution time 2t
CPU
fCPU = 8 MHz 250 ns
fEXT Timer external clock frequency 0f
CPU/4 MHz
fPWM PWM repetition rate
ResPWM PWM resolution 16 bit
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
215/223
19.11 Communication interface characteristics
19.11.1 SPI (serial peripheral interface)
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (SS, SCK, MOSI, MISO).
Table 131. SPI characteristics
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency Master, fCPU =8MHz f
CPU/128 = 0.0625 fCPU/4 = 2 MHz
Slave, fCPU =8MHz 0 f
CPU/2 = 4
tr(SCK)
tf(SCK)
SPI clock rise and fall time see I/O port pin description
tsu(SS)(1) SS setup time(2) Slave tCPU + 50
ns
th(SS)(1) SS hold time Slave 120
tw(SCKH)(1)
tw(SCKL)(1) SCK high and low time Master
Slave
100
90
tsu(MI)(1)
tsu(SI)(1) Data input setup time Master
Slave
100
100
th(MI)(1)
th(SI)(1) Data input hold time Master
Slave
100
100
ta(SO)(1) Data output access time Slave 0 120
tdis(SO)(1) Data output disable time Slave 240
tv(SO)(1) Data output valid time Slave (after enable edge) 120
th(SO)(1) Data output hold time 0
tv(MO)(1) Data output valid time Master (after enable edge) 120 tCPU
th(MO)(1) Data output hold time 0
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125 ns and tsu(SS) = 175 ns.
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
216/223
Figure 90. SPI slave timing diagram with CPHA = 0(1)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends on the I/O port configuration.
Figure 91. SPI slave timing diagram with CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS INPUT
SCK INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI) th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
See note 2
CPOL=0
CPOL=1
tsu(SS)th(SS)
tdis(SO)
th(SO)
See
note 2
BIT1 IN
SS INPUT
SCK INPUT
CPHA=1
MOSI INPUT
MISO OUTPUT
CPHA=1
tw(SCKH)
tw(SCKL) tr(SCK)
tf(SCK)
ta(SO)
tsu(SI) th(SI)
MSB OUT BIT6 OUT LSB OUT
See
CPOL=0
CPOL=1
tsu(SS)th(SS)
tdis(SO)
th(SO)
See
note 2note 2
tc(SCK)
HZ
tv(SO)
MSB IN LSB IN
BIT1 IN
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
217/223
Figure 92. SPI master timing diagram(1)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS INPUT
SCK INPUT
CPHA = 0
MOSI OUTPUT
MISO INPUT
CPHA = 0
CPHA = 1
CPHA = 1
tc(SCK)
tw(SCKH)
tw(SCKL)
th(MI)
tsu(MI)
MSB IN
MSB OUT
BIT6 IN
BIT6 OUT LSB OUT
LSB IN
See note 2 See note 2
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
tr(SCK)
tf(SCK)
th(MO)
tv(MO)
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
218/223
19.11.2 I2C - inter IC control interface
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the
requirements of the standard I2C communication protocol described in the following table.
Table 132. I2C control interface characteristics
Symbol Parameter
Standard mode I2CFast mode I
2C(1)
Unit
Min(2) Max(2) Min(2) Max(2)
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
ns
th(SDA) SDA data hold time 0(3) 0(4) 900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time 1000
20+0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time 300
th(STA) START condition hold time 4.0
0.6 µs
tsu(STA) Repeated START condition setup time 4.7
tsu(STO) STOP condition setup time 4.0
tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3
CbCapacitive load for each bus line 400 400 pF
1. At 4 MHz fCPU, maximum I2C speed (400 kHz) is not achievable. In this case, maximum I2C speed will be approximately
260 kHz.
2. Data based on standard I2C protocol requirement, not tested in production.
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL
signal.
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
219/223
Figure 93. Typical application with I2C BUS and timing diagram(1)
1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
The following table provides the values to be written in the I2CCCR register to obtain the
required I2C SCL line frequency.
Legend:
RP = External pull-up resistance
fSCL = I2C speed
Note: - For speeds around 200 kHz, the achieved speed can have a ±5% tolerance.
- For other speed ranges, the achieved speed can have a ±2% tolerance.
The above variations depend on the accuracy of the external components used.
REPEATED START
START
STOP
START
tf(SDA) tr(SDA) tsu(SDA) th(SDA)
tf(SCK)
tr(SCK)
tw(SCKL)
tw(SCKH)
th(STA) tsu(STO)
tsu(STA) tw(STO:STA)
SDA
SCK
4.7kΩSDAI
ST72XXX
SCLI
VDD
100Ω
100Ω
VDD
4.7kΩ
I2CBUS
Table 133. SCL frequency table
fSCL
(kHz)
I2CCCR value
fCPU =4MHz f
CPU =8MHz
VDD = 4.1V VDD = 5V VDD = 4.1V VDD = 5V
RP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩ
400 Not achievable 83h
300 Not achievable 85h
200 83h 8Ah 89h 8Ah
100 10h 24h 23h 24h 23h
50 24h 4Ch
20 5Fh FFh
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
220/223
19.12 10-bit ADC characteristics
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Table 134. 10-bit ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
fADC ADC clock frequency 0.4 2 MHz
VAREF Analog reference voltage 0.7*VDD < VAREF < VDD 3.8 VDD V
VAIN Conversion voltage range(1) VSSA VAREF
Ilkg
Input leakage current for analog
input(2)
-40°C < TA<85°C range ±250 nA
Other TA ranges ±1 µA
RAIN External input impedance See
Figure 94
and
Figure 95
kΩ
CAIN External capacitor on analog input pF
fAIN
Variation frequency of analog input
signal Hz
CADC Internal sample and hold capacitor 12 pF
tADC
Conversion time (Sample + Hold)
fCPU = 8 MHz, speed = 0,
fADC =2MHz
7.5 µs
tADC
No. of sample capacitor loading
cycles 41/fADC
No. of hold conversion cycles 11
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. Injecting negative current on adjacent pins may result in increased leakage currents. Software filtering of the converted
analog value is recommended.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
221/223
Figure 96. Typical A/D converter application
19.12.1 Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate VAREF and VSSA
analog power supply pins. These pins supply power to the A/D converter cell and function
as the high and low reference voltages for the conversion.
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see Section 19.12.2: General PCB
design guidelines).
Figure 94. RAIN maximum versus fADC with
CAIN =0pF
(1) Figure 95. Recommended CAIN and RAIN
values(1)
1. CPARASITIC represents the capacitance of the PCB
(dependent on soldering and PCB layout quality) plus
the pad capacitance (3pF). A high CPARASITIC value will
downgrade conversion accuracy. To remedy this, fADC
should be reduced.
1. This graph shows that, depending on the input signal
variation (fAIN), CAIN can be increased for stabilization
time and decreased to allow the use of a larger serial
resistor (RAIN).
0
5
10
15
20
25
30
35
40
45
0103070
CPARASITIC (pF)
Max. RAIN (Kohm)
2 MHz
1 MHz
0.1
1
10
100
1000
0.01 0.1 1 10
fAIN(KHz)
Max. RAIN (Kohm)
Cain 10 nF
Cain 22 nF
Cain 47 nF
AINx
ST72XXX
VDD
Ilkg
VT
0.6V
VT
0.6V CADC
12pF
VAIN
RAIN 10-bit A/D
conversion
2kΩ(max)
CAIN
Obsolete Product(s) - Obsolete Product(s)
Electrical characteristics ST72321Bxxx-Auto
222/223
19.12.2 General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1µF and optionally, if needed 10pF capacitors as close as possible to the ST7 power
supply pins and a 1 to 10µF capacitor close to the power source (see Figure 97).
●The analog and digital power supplies should be connected in a star network. Do not
use a resistor, as VAREF is used as a reference voltage by the A/D converter and any
resistance would cause a voltage drop and a loss of accuracy.
●Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
Figure 97. Power supply filtering
VSS
VDD
VDD
ST72XXX
VAREF
VSSA
POWER
SUPPLY
SOURCE
ST7
DIGITAL NOISE
FILTERING
EXTERNAL
NOISE
FILTERING
1 to 10µF 0.1µF
0.1µF
+
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Electrical characteristics
223/223
19.12.3 ADC accuracy
Figure 98. ADC error classification
Table 135. ADC accuracy
Symbol Parameter(1)
1. ADC Accuracy versus Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion
being performed on another analog input. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN)
in Section 19.8 does not affect the ADC accuracy.
Conditions Typ
Max(2)
2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C to
125°C (± 3σ distribution limits).
Unit
ROM and
48/60 Kbyte
Flash
32 Kbyte
Flash
|ET| Total unadjusted error
VDD =5V
(1)
CPU in run mode @ fADC 2 MHz
34 6
LSB
|EO| Offset error 2 3 5
|EG| Gain error 0.5 3 4.5
|ED| Differential linearity error 12 2
|EL| Integral linearity error 3
EO
EG
1LSB
IDEAL
1LSBIDEAL
VAREF VSSA
–
1024
--------------------------------------------=
Vin (LSBIDEAL)
Digital Result ADCDR
1023
1022
1021
5
4
3
2
1
0
7
6
1234567 1021 1022 1023 1024
(1)
(2)
ET
ED
EL
(3)
VAREF
VSSA
Legend:
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET= Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO= Offset Error: deviation between the first
actual transition and the first ideal one.
EG= Gain Error: deviation between the last ideal
transition and the last actual one.
ED= Differential Linearity Error: maximum
deviation between actual steps and the ideal
one.
EL= Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Obsolete Product(s) - Obsolete Product(s)
Package characteristics ST72321Bxxx-Auto
224/247
20 Package characteristics
20.1 Package mechanical data
Figure 99. 64-pin (14x14) low profile quad flat package outline
Table 136. 64-pin (14x14) low profile quad flat package mechanical data
Dimension
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 0.200 0.0035 0.0079
D 16.000 0.6299
D1 14.000 0.5512
E 16.000 0.6299
E1 14.000 0.5512
e 0.800 0.0315
θ0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
c
θ
L
L1
e
b
A
A1
A2
EE1
D
D1
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Package characteristics
225/247
Figure 100. 64-pin (10x10) low profile quad flat package outline
Table 137. 64-pin (10x10) low profile quad flat package mechanical data
Dimension
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 12.000 0.4724
D1 10.000 0.3937
E 12.000 0.4724
E1 10.000 0.3937
e 0.500 0.0197
θ0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
A
A2
A1
c
θ
L1
L
E
E1
D
D1
e
b
Obsolete Product(s) - Obsolete Product(s)
Package characteristics ST72321Bxxx-Auto
226/247
Figure 101. 44-pin (10x10) low profile quad flat package outline
Table 138. 44-pin (10x10) low profile quad flat package mechanical data
Dimension
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
C 0.090 0.200 0.0035 0.0079
D 12.000 0.4724
D1 10.000 0.3937
E 12.000 0.4724
E1 10.000 0.3937
e 0.800 0.0315
θ0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
A
A2
A1
b
e
L1
Lθ
c
E
E1
D
D1
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Package characteristics
227/247
20.2 Thermal characteristics
20.3 Soldering information
In accordance with the RoHS European directive, all STMicroelectronics packages have
been converted to lead-free technology, named ECOPACK®.
●ECOPACK® packages are qualified according to the JEDEC STD-020B compliant
soldering profile.
●Detailed information on the STMicroelectronics ECOPACK® transition program is
available on www.st.com/stonline/leadfree/, with specific technical application notes
covering the main technical aspects related to lead-free conversion (AN2033, AN2034,
AN2035 and AN2036).
20.3.1 Compatibility
ECOPACK® LQFP packages are fully compatible with lead (Pb) containing soldering
process (see application note AN2034).
Table 139. Thermal characteristics
Symbol Ratings Value Unit
RthJA
Package thermal resistance (junction to ambient)
LQFP64 14x14
LQFP64 10x10
LQFP44 10x10
47
50
52
°C/W
PDPower dissipation(1)
1. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation
of an application can be defined by the user with the formula: PD=P
INT +P
PORT where PINT is the chip
internal power (IDD xV
DD) and PPORT is the port power dissipation depending on the ports used in the
application.
500 mW
TJmax Maximum junction temperature(2)
2. The maximum chip-junction temperature is based on technology characteristics.
150 °C
Table 140. Soldering compatibility (wave and reflow soldering process)
Package Plating material Pb solder paste Pb-free solder paste
LQFP Sn (pure tin) Yes Yes
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
228/247
21 Device configuration and ordering information
Each device is available for production in user programmable versions (Flash) as well as in
factory coded versions (ROM/FASTROM).
ST72321B-Auto devices are ROM versions. ST72P321B-Auto devices are Factory
Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed
HDFlash devices. Flash devices are shipped to customers with a default content, whereas
ROM/FASTROM factory coded parts contain the code supplied by the customer. This
implies that Flash devices have to be configured by the customer using the option bytes
while the ROM/FASTROM devices are factory-configured.
Detailed device configuration and ordering information is presented in the following
Section 21.1: Flash devices and Section 21.2: ROM device ordering information and
transfer of customer code.
21.1 Flash devices
21.1.1 Flash configuration
The option bytes allow the hardware configuration of the microcontroller to be selected.
They have no address in the memory map and can be accessed only in programming mode
(for example, using a standard ST7 programming tool). The default content of the Flash is
fixed to FFh. To program the Flash devices directly using ICP, Flash devices are shipped to
customers with the internal RC clock source enabled. In masked ROM devices, the option
bytes are fixed in hardware by the ROM code (see option list).
Table 141. Flash option bytes
Static option byte 0 Static option byte 1
7654321076543210
WDG
Res
VD
Reserved
FMP_R
PKG1
RSTC
OSCTYPE OSCRANGE
PLLOFF
HALTSW 10 10210
Default
value: 11100111
(1) 1100111
1. Depends on device type as defined in Table 144: Package selection (OPT7) on page 230
Table 142. Option byte 0 bit description
Bit Name Function
OPT7 WDG HALT
Watchdog and Halt mode
This option bit determines if a RESET is generated when entering
Halt mode while the Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Device configuration and ordering information
229/247
OPT6 WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 - Reserved, must be kept at default value.
OPT4:3 VD[1:0]
Voltage detection
These option bits enable the voltage detection block (LVD and AVD)
with a selected threshold for the LVD and AVD (EVD + AVD).
00: Selected LVD = Highest threshold (VDD~4V)
01: Selected LVD = Medium threshold (VDD~3.5V)
10: Selected LVD = Lowest threshold (VDD~3V)
11: LVD and AVD off
Caution: If the medium or low thresholds are selected, the detection
may occur outside the specified operating voltage range. Below 3.8V,
device operation is not guaranteed. For details on the AVD and LVD
threshold levels refer to Section 19.3.2: Operating conditions with low
voltage detector (LVD) on page 194.
OPT2:1 - Reserved, must be kept at default value
OPT0 FMP_R
Flash memory readout protection
Readout protection, when selected, provides a protection against
program memory content extraction and against write access to Flash
memory.
Erasing the option bytes when the FMP_R option is selected causes
the whole user memory to be erased first, after which the device can
be reprogrammed. Refer to Section 4.3.1: Readout protection on
page 37 and the ST7 Flash Programming Reference Manual for more
details.
0: Readout protection enabled
1: Readout protection disabled
Table 143. Option byte 1 bit description
Bit Name Function
OPT7 PKG1
Package selection bit 1
This option bit selects the package (see Table 144: Package selection
(OPT7)).
OPT6 RSTC
RESET clock cycle selection
This option bit selects the number of CPU cycles applied during the
RESET phase and when exiting Halt mode. For resonator oscillators,
it is advised to select 4096 due to the long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
OPT5:4 OSCTYPE[1:0]
Oscillator type
These option bits select the ST7 main clock source type.
00: Clock source = Resonator oscillator
01: Reserved
10: Clock source = Internal RC oscillator
11: Clock source = External source
Table 142. Option byte 0 bit description (continued)
Bit Name Function
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
230/247
Note: On the chip, each I/O port has up to eight pads. Pads that are not bonded to external pins
are in input pull-up configuration after reset. The configuration of these pads must be kept at
reset state to avoid added current consumption.
OPT3:1 OSCRANGE[2:0]
Oscillator range
When the resonator oscillator type is selected, these option bits select
the resonator oscillator current source corresponding to the frequency
range of the resonator used. When the external clock source is
selected, these bits are set to medium power (2 ~ 4 MHz).
000: Typ. frequency range = 1 ~ 2 MHz
001: Typ. frequency range = 2 ~ 4 MHz
010: Typ. frequency range = 4 ~ 8 MHz
011: Typ. frequency range = 8 ~ 16 MHz
OPT0 PLLOFF
PLL activation
This option bit activates the PLL which allows multiplication by two of
the main input clock frequency. The PLL is guaranteed only with an
input frequency between 2 and 4 MHz. For this reason the PLL must
not be used with the internal RC oscillator.
0: PLL x2 enabled
1: PLL x2 disabled
Caution: The PLL can be enabled only if the OSCRANGE (OPT3:1) bits
are configured to 2 ~ 4 MHz. Otherwise, the device functionality is not
guaranteed.
Table 144. Package selection (OPT7)
Version Selected package Flash size PKG1
R/AR LQFP64 32/48/60 Kbytes 1
JLQFP44
48/60 Kbytes 0
32 Kbytes 1
Table 143. Option byte 1 bit description (continued)
Bit Name Function
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Device configuration and ordering information
231/247
21.1.2 Flash ordering information
The following Tab l e 1 4 5 serves as a guide for ordering.
Figure 102. Flash commercial product code structure
Table 145. Flash user programmable device types
Order code(1)
1. R = Tape and Reel (left blank if Tray)
Package Memory (Kbytes) Temperature range
ST72F321BJ6TARE
LQFP44 (10 x 10)
32
-40°C to +85°C
ST72F321BJ7TARE 48
ST72F321BJ9TARE 60
ST72F321BAR6TARE
LQFP64 (10 x 10)
32
ST72F321BAR7TARE 48
ST72F321BAR9TARE 60
ST72F321BR6TARE
LQFP64 (14 x 14)
32
ST72F321BR7TARE 48
ST72F321BR9TARE 60
ST72F321BJ6TCRE
LQFP44 (10 x 10)
32
-40°C to +125°C
ST72F321BJ7TCRE 48
ST72F321BJ9TCRE 60
ST72F321BAR6TCRE
LQFP64 (10 x 10)
32
ST72F321BAR7TCRE 48
ST72F321BAR9TCRE 60
ST72F321BR6TCRE
LQFP64 (14 x 14)
32
ST72F321BR7TCRE 48
ST72F321BR9TCRE 60
DEVICE PACKAGE R EPINOUT PROG MEM
E = Lead-free (ECOPACK®)
Conditioning options:
R = Tape and Reel (left blank if Tray)
A = -40 to +85°C
C = -40 to +125°C
T = Low profile quad flat pack
6 = 32 Kbytes
7 = 48 Kbytes
9 = 60 Kbytes
J = 44 pins
AR = 64 pins (10x10)
R = 64 pins (14x14)
ST72F321B
TEMP RANGE
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
232/247
21.2 ROM device ordering information and transfer of customer
code
Customer code is made up of the ROM/FASTROM contents and the list of the selected
options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic
means, with the S19 hexadecimal file generated by the development tool. All unused bytes
must be set to FFh.
Complete the appended ST72321B-Auto MIcrocontroller FASTROM/ROM Option List on
page 236 to communicate the selected options to STMicroelectronics and check for regular
updates of the option list on the ST website or ask your ST representative.
Refer to application note AN1635 for information on the counter listing returned by ST after
code has been transferred.
The following Table 146: FASTROM factory coded device types and Table 147: ROM factory
coded device types on page 234 serve as guides for ordering. The STMicroelectronics
Sales Organization will be pleased to provide detailed information on contractual points.
Caution: The Readout Protection binary value is inverted between ROM and Flash products. The
option byte checksum will differ between ROM and Flash.
Table 146. FASTROM factory coded device types
Order code(1) Package Memory (Kbytes) Temperature range
ST72P321B(J6)TAxxxRE
LQFP44 (10 x 10)
32
-40°C to +85°C
ST72P321B(J7)TAxxxRE 48
ST72P321B(J9)TAxxxRE 60
ST72P321B(AR6)TAxxxRE
LQFP64 (10 x 10)
32
ST72P321B(AR7)TAxxxRE 48
ST72P321B(AR9)TAxxxRE 60
ST72P321B(R6)TAxxxRE
LQFP64 (14 x 14)
32
ST72P321B(R7)TAxxxRE 48
ST72P321B(R9)TAxxxRE 60
ST72P321B(J6)TBxxxRE
LQFP44 (10 x 10)
32
-40°C to +105°C
ST72P321B(J7)TBxxxRE 48
ST72P321B(J9)TBxxxRE 60
ST72P321B(AR6)TBxxxRE
LQFP64 (10 x 10)
32
ST72P321B(AR7)TBxxxRE 48
ST72P321B(AR9)TBxxxRE 60
ST72P321B(R6)TBxxxRE
LQFP64 (14 x 14)
32
ST72P321B(R7)TBxxxRE 48
ST72P321B(R9)TBxxxRE 60
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Device configuration and ordering information
233/247
Figure 103. FASTROM commercial product code structure
ST72P321B(J6)TCxxxRE
LQFP44 (10 x 10)
32
-40°C to +125°C
ST72P321B(J7)TCxxxRE 48
ST72P321B(J9)TCxxxRE 60
ST72P321B(AR6)TCxxxRE
LQFP64 (10 x 10)
32
ST72P321B(AR7)TCxxxRE 48
ST72P321B(AR9)TCxxxRE 60
ST72P321B(R6)TCxxxRE
LQFP64 (14 x 14)
32
ST72P321B(R7)TCxxxRE 48
ST72P321B(R9)TCxxxRE 60
1. - The two or three characters in parentheses which represent the pinout and program memory size are for
reference only and are not visible in the final commercial product order code.
- ‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
- R = Tape and Reel (left blank if Tray)
Table 146. FASTROM factory coded device types (continued)
Order code(1) Package Memory (Kbytes) Temperature range
DEVICE PACKAGE xxx
E = Lead-free (ECOPACK®)
Conditioning options:
R = Tape and Reel (left blank if Tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to 85°C
B = -40 to 105°C
C = -40 to 125°C
T = Low profile quad flat pack
ST72P321B
R ETEMP RANGE
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
234/247
Table 147. ROM factory coded device types
Order code(1)
1. - The two or three characters in parentheses which represent the pinout and program memory size are for
reference only and are not visible in the final commercial product order code.
- ‘xxx’ represents the code name defined by STMicroelectronics: It denotes the ROM code, pinout and
program memory size.
- R = Tape and Reel (left blank if Tray)
Package Memory (Kbytes) Temperature range
ST72321B(J6)TA/xxxRE
LQFP44 (10 x 10)
32
-40°C to +85°C
ST72321B(J7)TA/xxxRE 48
ST72321B(J9)TA/xxxRE 60
ST72321B(AR6)TA/xxxRE
LQFP64 (10 x 10)
32
ST72321B(AR7)TA/xxxRE 48
ST72321B(AR9)TA/xxxRE 60
ST72321B(R6)TA/xxxRE
LQFP64 (14 x 14)
32
ST72321B(R7)TA/xxxRE 48
ST72321B(R9)TA/xxxRE 60
ST72321B(J6)TB/xxxRE
LQFP44 (10 x 10)
32
-40°C to +105°C
ST72321B(J7)TB/xxxRE 48
ST72321B(J9)TB/xxxRE 60
ST72321B(AR6)TB/xxxRE
LQFP64 (10 x 10)
32
ST72321B(AR7)TB/xxxRE 48
ST72321B(AR9)TB/xxxRE 60
ST72321B(R6)TB/xxxRE
LQFP64 (14 x 14)
32
ST72321B(R7)TB/xxxRE 48
ST72321B(R9)TB/xxxRE 60
ST72321B(J6)TC/xxxRE
LQFP44 (10 x 10)
32
-40°C to +125°C
ST72321B(J7)TC/xxxRE 48
ST72321B(J9)TC/xxxRE 60
ST72321B(AR6)TC/xxxRE
LQFP64 (10 x 10)
32
ST72321B(AR7)TC/xxxRE 48
ST72321B(AR9)TC/xxxRE 60
ST72321B(R6)TC/xxxRE
LQFP64 (14 x 14)
32
ST72321B(R7)TC/xxxRE 48
ST72321B(R9)TC/xxxRE 60
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Device configuration and ordering information
235/247
Figure 104. ROM commercial product code structure
DEVICE PACKAGE xxx/ R E
E = Lead-free (ECOPACK®)
Conditioning options:
R = Tape and Reel (left blank if Tray)
Code name (defined by STMicroelectronics)
(denotes ROM code, pinout and program memory size)
A = -40 to 85°C
B = -40 to 105°C
C = -40 to 125°C
T = Low profile quad flat pack
ST72321B
TEMP RANGE
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
236/247
ST72321B-Auto MIcrocontroller FASTROM/ROM Option List
(Last update: October 2007)
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The FASTROM/ROM code name is assigned by STMicroelectronics.
FASTROM/ROM code must be sent in .S19 format. .Hex extension cannot be processed.
Device Type/Memory Size/Package (check only one option):
------------------------------------------------------------------------------------------------------------------------------------------------------
FASTROM DEVICE: 60K 48K 32K
------------------------------------------------------------------------------------------------------------------------------------------------------
LQFP44 10x10: [ ] ST72P321B(J9)T [ ] ST72P321B(J7)T [ ] ST72P321B(J6)T
LQFP64 10x10: [ ] ST72P321B(AR9)T [ ] ST72P321B(AR7)T [ ] ST72P321B(AR6)T
LQFP64 14x14: [ ] ST72P321B(R9)T [ ] ST72P321B(R7)T [ ] ST72P321B(R6)T
-------------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------------
ROM DEVICE: 60K 48K 32K
-------------------------------------------------------------------------------------------------------------------------------------------------------
LQFP44 10x10: [ ] ST72321B(J9)T [ ] ST72321B(J7)T [ ] ST72321B(J6)T
LQFP64 10x10: [ ] ST72321B(AR9)T [ ] ST72321B(AR7)T [ ] ST72321B(AR6)T
LQFP64 14x14: [ ] ST72321B(R9)T [ ] ST72321B(R7)T [ ] ST72321B(R6)T
-------------------------------------------------------------------------------------------------------------------------------------------------------
Conditioning for LQFP package (check only one option):
[ ] Tape & Reel [ ] Tray
Temperature range : [ ] A (-40°C to +85°C)
[ ] B (-40°C to +105°C)
[ ] C (-40°C to +125°C)
Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 characters max)
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Clock Source Selection: [ ] Resonator:
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal RC
[ ] External Clock (sets MP Medium Power resonator in Option Byte)
PLL (1)(2) [ ] Disabled [ ] Enabled
LVD Reset [ ] Disabled [ ] High threshold
[ ] Med.threshold [ ] Low threshold
Reset Delay [ ] 256 Cycles [ ] 4096 Cycles
Watchdog Selection [ ] Software Activation [ ] Hardware Activation
Halt when Watchdog on [ ] Reset [ ] No reset
Readout Protection [ ] Disabled [ ] Enabled
Date . . . . . . . . Signature . . . . . . . . . . . . . . . .
Note 1 : PLL must be disabled if internal RC Network is selected.
Note 2 : The PLL can be enabled only if the resonator is configured to “Medium Power: 2~4 MHz”.
CAUTION: The Readout Protection binary value is inverted between ROM and Flash products. The option byte checksum will
differ between ROM and Flash.
Please download the latest version of this option list from www.st.com.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Device configuration and ordering information
237/247
21.3 Development tools
21.3.1 Introduction
Development tools for the ST7 microcontrollers include a complete range of hardware
systems and software tools from STMicroelectronics and third-party tool suppliers. The
range of tools includes solutions to help you evaluate microcontroller peripherals, develop
and debug your application, and program your microcontrollers.
21.3.2 Evaluation tools and starter kits
ST offers complete, affordable starter kits and full-featured evaluation boards that allow you
to evaluate microcontroller features and quickly start developing ST7 applications. Starter
kits are complete, affordable hardware/software tool packages that include features and
samples to help you quickly start developing your application. ST evaluation boards are
open-design, embedded systems, which are developed and documented to serve as
references for your application design. They include sample application software to help you
demonstrate, learn about and implement your ST7’s features.
21.3.3 Development and debugging tools
Application development for ST7 is supported by fully optimizing C Compilers and the ST7
Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated
development environments in order to facilitate the debugging and fine-tuning of your
application. The Cosmic C Compiler is available in a free version that outputs up to
16 Kbytes of code.
The range of hardware tools includes cost effective ST7-DVP3 series emulators. These
tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7
integrated development environment (IDE) with high-level language debugger, editor,
project manager and integrated programming interface.
21.3.4 Programming tools
During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the
RLink provide in-circuit programming capability for programming the Flash microcontroller
on your application board.
ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as
ST7 socket boards which provide all the sockets required for programming any of the
devices in a specific ST7 subfamily on a platform that can be used with any tool with in-
circuit programming capability for ST7.
For production programming of ST7 devices, ST’s third-party tool partners also provide a
complete range of gang and automated programming solutions, which are ready to integrate
into your production environment.
For additional ordering codes for spare parts, accessories and tools available for the ST7
(including from third party manufacturers), refer to the online product selector at
www.st.com/mcu.
Obsolete Product(s) - Obsolete Product(s)
Device configuration and ordering information ST72321Bxxx-Auto
238/247
21.3.5 Socket and emulator adapter information
For information on the type of socket that is supplied with the emulator, refer to the
suggested list of sockets in Ta bl e 1 4 9 .
Note: Before designing the board layout, it is recommended to check the overall dimensions of the
socket as they may be greater than the dimensions of the device.
For footprint and other mechanical information about these sockets and adapters, refer to
the manufacturer’s datasheet.
Related documentation
ST7 Visual Develop Software Key Debugging Features (AN 978)
ST7 Visual Develop for ST7 Cosmic C toolset users (AN 1938)
ST7 Visual Develop for ST7 Assembler Linker toolset users (AN 1940)
21.4 ST7 application notes
All relevant ST7 application notes can be found on www.st.com.
Table 148. STMicroelectronics development tools
Supported
products
Emulation Programming
ST7 DVP3 series ST7 EMU3 series
ICC socket
board
Emulator Connection kit Emulator Active probe
and T.E.B.
ST72321BAR,
ST72F321BAR
ST7MDT20-
DVP3
ST7MDT20-
T6A/DVP ST7MDT20M-
EMU3
ST7MDT20M-
TEB ST7SB20M/xx(1)
ST72321BR,
ST72F321BR
ST7MDT20-
T64/DVP
ST72321BJ,
ST72F321BJ
ST7MDT20-
T44/DVP
ST7MDT20J-
EMU3
ST7MDT20J-
TEB ST7SB20J/xx(1)
1. Add suffix /EU, /UK, /US for the power supply of your region.
Table 149. Suggested list of socket types
Device Socket
(supplied with ST7MDT20M-EMU3)
Emulator adapter
(supplied with ST7MDT20M-EMU3)
LQFP64 14 x14 CAB 3303262 CAB 3303351
LQFP64 10 x10 YAMAICHI IC149-064-*75-*5 YAMAICHI ICP-064-6
LQFP44 10 x10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Known limitations
239/247
22 Known limitations
22.1 All Flash and ROM devices
22.1.1 Unexpected reset fetch
If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt
controller does not recognize the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.
22.1.2 External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period will not be detected and will not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1
cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is
changed to level '0' inside the interrupt routine. When a level change is detected, the
semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In
this case, the interrupt routine is invoked with the call instruction.
There is another possible case, that is, if PxOR or PxDDR are written to with global
interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’
when the level change is detected. Detecting a missed interrupt is done after the global
interrupts are enabled (interrupt mask bit reset) and by checking the status of the
semaphore. If it is ‘1’, it means that the last interrupt was missed and the interrupt routine is
invoked with the call instruction.
To implement the workaround, the following software sequence is to be followed for writing
into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt
sensitivity. The software sequence is given for both cases (global interrupts disabled / global
interrupts enabled):
Case 1: Writing to PxOR or PxDDR with global interrupts enabled:
LD A,#01
Obsolete Product(s) - Obsolete Product(s)
Known limitations ST72321Bxxx-Auto
240/247
LD sema,A
; set the semaphore to '1'
LD A,PFDR
AND A,#02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write to PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
; check the semaphore status if edge is detected
CP A,#01
jrne OUT
call call_routine
; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Known limitations
241/247
.ext1_rt
; entry to interrupt routine
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with global interrupts disabled:
SIM
; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to PxOR/PxDDR
LD A,#$90
LD PFDDR,A
; Write into PFDDR
LD A,#$ff
LD PFOR,A
; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A
; store the level after writing to PxOR/PxDDR
LD A,X
; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A
; set the semaphore to '1' if edge is detected
RIM
; reset the interrupt mask
LD A,sema
; check the semaphore status
CP A,#$01
Obsolete Product(s) - Obsolete Product(s)
Known limitations ST72321Bxxx-Auto
242/247
jrne OUT
call call_routine
; call the interrupt routine
RIM
OUT:
RIM
JP while_loop
.call_routine
; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
22.1.3 Clearing active interrupts outside interrupt routine
When an active interrupt request occurs at the same time as the related flag is being
cleared, an unwanted reset may occur.
Note: Clearing the related interrupt mask will not generate an unwanted reset.
Concurrent interrupt context
The symptom does not occur when the interrupts are handled normally, that is, when:
●The interrupt flag is cleared within its own interrupt routine
●The interrupt flag is cleared within any interrupt routine
●The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
Perform SIM and RIM operation before and after resetting an active interrupt request.
Example:
SIM
Reset interrupt flag
RIM
Nested interrupt context
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Known limitations
243/247
The symptom does not occur when the interrupts are handled normally, that is, when:
●The interrupt flag is cleared within its own interrupt routine
●The interrupt flag is cleared within any interrupt routine with higher or identical priority
level
●The interrupt flag is cleared in any part of the code while this interrupt is disabled
If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
PUSH CC
SIM
Reset interrupt flag
POP CC
22.1.4 SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
●20 bits instead of 10 bits if M = 0
●22 bits instead of 11 bits if M = 1
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generating one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baud rate. With a transmit
frequency of 19200 baud (fCPU = 8 MHz and SCIBRR = 0xC9), the wrong break duration
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
●Disable interrupts
●Reset and Set TE (IDLE request)
●Set and Reset SBK (Break Request)
●Re-enable interrupts
22.1.5 16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
Obsolete Product(s) - Obsolete Product(s)
Known limitations ST72321Bxxx-Auto
244/247
22.1.6 TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs, the output
compare flag then gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If the output compare interrupt is enabled, then the output compare flag cannot be cleared in
the timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer, then the timer interrupts.
●Perform the following to disable the timer:
– TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
– TACSR | or TBCSR | = 0x40; // Disable the timer
●Perform the following to enable the timer again:
– TACSR & or TBCSR & = ~0x40; // Enable the timer
– TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
22.1.7 I2C multimaster
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a restart and Slave address to re-initiate communication.
22.1.8 Pull-up always active on PE2
The I/O port internal pull-up is always active on I/O port E2. As a result, if PE2 is in output
mode low level, current consumption in Halt/Active Halt mode is increased.
22.2 Limitations specific to 44-pin 32 Kbyte ROM devices
22.2.1 Halt/Active Halt mode power consumption with external clock
enabled
The power consumption in Halt/Active Halt mode with external clock enabled is increased by
40µA typ.
22.2.2 Active Halt power consumption
The power consumption in Active Halt mode is 190µA typ. and 300µA max. These
measurements are done with an external clock source. However to obtain the total device
consumption, the clock source consumption has to be added.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto Known limitations
245/247
22.2.3 I²C exit from Halt/Active Halt
Contrary to the behavior specified in the datasheet, the I2C interrupt is capable of exiting the
device from Halt/Active Halt mode.
Obsolete Product(s) - Obsolete Product(s)
ST72321Bxxx-Auto
247/247
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
