PRELIMINARY ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS844011 is a Fibre Channel Clock Generator ICS and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS844011 uses an 18pF parallel resonant crystal over the range of 20.4MHz - 28.3MHz. For Fibre Channel applications, a 26.5625MHz crystal is used. The ICS844011 has excellent <1ps phase jitter performance, over the 637kHz - 10MHz integration range. The ICS844011 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * One differential LVDS output * Crystal oscillator interface, 18pF parallel resonant crystal (20.4MHz - 28.3MHz) * Output frequency range: 81.66MHz - 113.33MHz * VCO range: 490MHz - 680MHz * RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.75ps (typical) * 3.3V or 2.5V operating supply * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages COMMON CONFIGURATION TABLE - FIBRE CHANNEL Inputs Crystal Frequency (MHz) M N 26.5625 24 6 Multiplication Value M/N 4 25 24 6 4 Output Frequency (MHz) 106.25 100 BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO 490MHz - 680MHz N = /6 (fixed) Q nQ VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ OE ICS844011 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = /24 (fixed) The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT TM / ICSTM LVDS CLOCK GENERATOR 1 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Analog supply pin. 2 GND XTAL_OUT, XTAL_IN Power 5 OE Input 6, 7 nQ, Q Output Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Output enable pin. When HIGH, Q/nQ output is active. When LOW, the Q/nQ output is in a high impedance state. LVCMOS/LVTTL interface levels. Differential clock outputs. LVDS interface levels. 8 VDD Power Core supply pin. 3, 4 Type Input Pullup Description NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k IDT TM / ICSTM LVDS CLOCK GENERATOR Test Conditions Minimum 2 Typical Maximum Units ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.3 VDD VDD - IDDA*10 VDDA Analog Supply Voltage IDD Power Supply Current TBD mA V IDDA Analog Supply Current TBD mA TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 2.5 VDD VDD - IDDA*10 VDDA Analog Supply Voltage IDD Power Supply Current TBD mA V IDDA Analog Supply Current TBD mA TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, TA = 0C TO 70C Symbol VIH Parameter Input High Voltage Test Conditions Minimum Maximum Units VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 A VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V or 2.625V IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V IDT TM / ICSTM LVDS CLOCK GENERATOR Typical 3 -150 A ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 350 mV 50 mV 1.25 V 50 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 V VOS VOS Magnitude Change 50 mV NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 28.3 MHz Fundamental Frequency 20.4 Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units 113.33 MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency tjit(O) t R / tF RMS Phase Jitter ( Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 100MHz @ Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. TBD ps 0.75 ps 275 ps 50 % TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = 0C TO 70C Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter ( Random); NOTE 1 t R / tF Output Rise/Fall Time Test Conditions Typical 81.66 106.25MHz @ Integration Range: 637kHz - 10MHz 100MHz @ Integration Range: 637kHz - 10MHz 20% to 80% odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plots following this section. IDT TM / ICSTM LVDS CLOCK GENERATOR Minimum 4 Maximum Units 113.33 MHz TBD ps 0.93 ps 295 ps 50 % ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION Qx 3.3V5% POWER SUPPLY + Float GND - SCOPE Qx 2.5V5% POWER SUPPLY + Float GND - LVDS SCOPE LVDS nQx nQx LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT Phase Noise Plot Noise Power nQ Q t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD out 80% DC Input VSW I N G Clock Outputs LVDS 80% 20% 20% tR out tF VOS/ VOS OFFSET VOLTAGE SETUP OUTPUT RISE/FALL TIME VDD LVDS 100 VOD/ VOD out DC Input out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT TM / ICSTM LVDS CLOCK GENERATOR 5 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844011 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V or 2.5V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS844011 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUT INTERFACE IDT TM / ICSTM LVDS CLOCK GENERATOR 6 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT TM / ICSTM LVDS CLOCK GENERATOR 7 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY RELIABILITY INFORMATION TABLE 6. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS844011 is: 2533 IDT TM / ICSTM LVDS CLOCK GENERATOR 8 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 8 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 E E1 3.10 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM LVDS CLOCK GENERATOR 9 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS844011AG 4011A 8 lead TSSOP tube 0C to 70C ICS844011AGT 4011A 8 lead TSSOP 2500 tape & reel 0C to 70C ICS844011AGLF TBD 8 lead "Lead-Free" TSSOP tube 0C to 70C ICS844011AGLFT TBD 8 lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM LVDS CLOCK GENERATOR 10 ICS844011AG REV A OCTOBER 6, 2006 ICS844011 FEMTOCLOCKSTM CRYSTAL-TO-LVDS CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA