ICL7106, ICL7107, ICL7107S (R) Data Sheet December 1, 2005 3 1/2 Digit, LCD/LED Display, A/D Converters FN3082.8 Features * Guaranteed Zero Reading for 0V Input on All Scales The Intersil ICL7106 and ICL7107 are high performance, low power, 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less than 10V, zero drift of less than 1V/oC, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. * True Polarity at Zero for Precise Null Detection * 1pA Typical Input Current * True Differential Input and Reference, Direct Display Drive - LCD ICL7106, LED lCL7107 * Low Noise - Less Than 15VP-P * On Chip Clock and Reference * Low Power Dissipation - Typically Less Than 10mW * No Additional Active Circuits Required * Enhanced Display Stability * Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NO. PART MARKING ICL7106CPL ICL7106CPL TEMP. RANGE (C) 0 to 70 PACKAGE PKG. DWG. # 40 Ld PDIP E40.6 ICL7106CPLZ (Note 2) ICL7106CPLZ 0 to 70 40 Ld PDIP(Pb-free) (Note 3) E40.6 ICL7106CM44 ICL7106CM44 0 to 70 44 Ld MQFP Q44.10x10 ICL7106CM44Z (Note 2) ICL7106CM44Z 0 to 70 44 Ld MQFP (Pb-free) Q44.10x10 ICL7106CM44ZT (Note 2) ICL7106CM44Z 0 to 70 44 Ld MQFP Tape and Reel (Pb-free) Q44.10x10 ICL7107CPL ICL7107CPL 0 to 70 40 Ld PDIP E40.6 ICL7107CPLZ (Note 2) ICL7107CPLZ 0 to 70 40 Ld PDIP(Pb-free) (Note 3) E40.6 ICL7107RCPL ICL7107RCPL 0 to 70 40 Ld PDIP (Note 1) E40.6 ICL7107RCPLZ (Note 2) ICL7107RCPLZ 0 to 70 40 Ld PDIP (Pb-free) (Notes 1, 3) E40.6 ICL7107SCPL ICL7107SCPL 0 to 70 40 Ld PDIP (Notes 1, 3) E40.6 ICL7107SCPLZ (Note 2) ICL7107SCPLZ 0 to 70 40 Ld PDIP (Pb-free) (Notes 1, 3) E40.6 ICL7107CM44 ICL7107CM44 0 to 70 44 Ld MQFP Q44.10x10 ICL7107CM44T ICL7107CM44 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10 ICL7107CM44Z (Note 2) ICL7107CM44Z 0 to 70 44 Ld MQFP (Pb-free) Q44.10x10 ICL7107CM44ZT (Note 2) ICL7107CM44Z 0 to 70 44 Ld MQFP Tape and Reel (Pb-free) Q44.10x10 NOTES: 1. "R" indicates device with reversed leads for mounting to PC board underside. "S" indicates enhanced stability. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICL7106, ICL7107, ICL7107S Pinouts ICL7106, ICL7107 (PDIP) TOP VIEW ICL7107R (PDIP) TOP VIEW V+ 1 40 OSC 1 D1 2 39 OSC 2 C1 3 B1 4 A1 5 F1 6 G1 7 E1 8 D2 9 C2 10 B2 11 A2 12 F2 13 28 BUFF E2 14 27 INT D3 15 B3 16 F3 17 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 35 REF LO 34 CREF+ 33 CREF- 3 38 C1 TEST 4 37 B1 REF HI 5 36 A1 REF LO 6 35 F1 CREF+ 7 34 G1 CREF- 8 33 E1 COMMON 9 32 D2 IN HI 10 31 C2 IN LO 11 30 B2 A-Z 12 29 A2 BUFF 13 28 F2 INT 14 27 E2 V- 15 26 D3 G2 (10's) 16 25 B3 C3 17 24 F3 32 COMMON 31 IN HI 30 IN LO 29 A-Z 26 V25 G2 (10's) 24 C3 (100's) (100's) (1's) (10's) (100's) A3 18 23 E3 G3 19 22 (1000) AB4 BP/GND 20 21 POL 21 BP/GND (MINUS) V- INT BUFF A-Z IN LO IN HI COMMON ICL7106, ICL7107 (MQFP) TOP VIEW CREF+ (MINUS) 39 D1 OSC 3 36 REF HI CREF- (100's) 40 V+ 2 37 TEST REF LO (10's) 1 OSC 2 38 OSC 3 REF HI (1's) OSC 1 44 43 42 41 40 39 38 37 36 35 34 33 2 32 NC TEST 3 31 C3 OSC 3 4 30 A3 NC 5 29 G3 OSC 2 6 28 BP/GND OSC 1 7 27 POL V+ 8 26 AB4 D1 9 25 E3 C1 10 24 F3 B1 11 23 12 13 14 15 16 17 18 19 20 21 22 B3 NC NC 1 G2 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 2 FN3082.8 ICL7106, ICL7107, ICL7107S Absolute Maximum Ratings Thermal Information Supply Voltage ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input). . . . . . . . . . . . . . . . . V+ to VClock Input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+ Thermal Resistance (Typical, Note 2) Operating Conditions JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP - Lead Tips Only) NOTE: Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to 100A. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full Scale = 200mV -000.0 000.0 +000.0 Digital Reading Stability (Last Digit) (ICL7106S, ICL7107S Only) Fixed Input Voltage (Note 6) -000.0 000.0 +000.0 Digital Reading Ratiometric Reading VlN = VREF , VREF = 100mV 999 999/10 00 1000 Digital Reading Rollover Error -VIN = +VlN 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale - 0.2 1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 5) - 0.2 1 Counts Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - V/V Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) - 15 - V Leakage Current Input VlN = 0 (Note 5) - 1 10 pA Zero Reading Drift VlN = 0, 0oC To 70oC (Note 5) VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/x oC) (Note 5) - 0.2 1 V/oC - 1 5 ppm/oC - 1.0 1.8 mA - 0.6 1.8 mA Scale Factor Temperature Coefficient End Power Supply Character V+ Supply Current VIN = 0 (Does Not Include LED Current for ICL7107) End Power Supply Character V- Supply Current ICL7107 Only COMMON Pin Analog Common Voltage 25k Between Common and Positive Supply (With Respect to + Supply) 2.4 3.0 3.2 V Temperature Coefficient of Analog Common 25k Between Common and Positive Supply (With Respect to + Supply) - 80 - ppm/oC V+ = to V- = 9V (Note 4) 4 5.5 6 V DISPLAY DRIVER ICL7106 ONLY Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage 3 FN3082.8 ICL7106, ICL7107, ICL7107S Electrical Specifications (Note 3) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Except Pins AB4 and POL 5 8 - mA Pin AB4 Only 10 16 - mA Pin POL Only 4 7 - mA DISPLAY DRIVER ICL7107 ONLY Segment Sinking Current V+ = 5V, Segment Voltage = 3V NOTES: 3. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = 25oC, fCLOCK = 48kHz. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 4. Back plane drive is in phase with segment drive for "off" segment, 180 degrees out of phase for "on" segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 5. Not tested, guaranteed by design. 6. Sample Tested. Typical Applications and Test Circuits IN A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 18 E3 17 F3 V- 26 G2 25 16 B3 INT 27 DISPLAY 15 D3 14 E2 A-Z 29 BUFF 28 C3 13 F2 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 TEST 37 C5 C1 R4 REF HI 36 OSC 3 38 OSC 2 39 OSC 1 40 C4 + R5 R1 R3 9V - - + 12 A2 11 B2 D2 9 10 C2 E1 8 A1 5 F1 B1 4 G1 C1 3 7 D1 2 6 V+ 1 ICL7106 C1 = 0.1F C2 = 0.47F C3 = 0.22F C4 = 100pF C5 = 0.02F R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M DISPLAY FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE +5V + IN INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 14 E2 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL DISPLAY BUFF 28 A-Z 29 C3 13 F2 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 IN HI 31 C5 C1 R4 REF HI 36 TEST 37 OSC 3 38 OSC 2 39 OSC 1 40 C4 -5V R5 R1 R3 - B1 A1 F1 G1 E1 D2 4 5 6 7 8 9 12 A2 C1 3 11 B2 D1 2 10 C2 V+ 1 ICL7107 C1 = 0.1F C2 = 0.47F C3 = 0.22F C4 = 100pF C5 = 0.02F R1 = 24k R2 = 47k R3 = 100k R4 = 1k R5 = 1M DISPLAY FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 4 FN3082.8 ICL7106, ICL7107, ICL7107S Design Information Summary Sheet * DISPLAY COUNT * OSCILLATOR FREQUENCY V IN COUNT = 1000 x --------------V REF fOSC = 0.45/RC COSC > 50pF; ROSC > 50k fOSC (Typ) = 48kHz * CONVERSION CYCLE * OSCILLATOR PERIOD tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms tOSC = RC/0.45 * INTEGRATION CLOCK FREQUENCY * COMMON MODE INPUT VOLTAGE fCLOCK = fOSC/4 (V- + 1V) < VlN < (V+ - 0.5V) * INTEGRATION PERIOD * AUTO-ZERO CAPACITOR tINT = 1000 x (4/fOSC) 0.01F < CAZ < 1F * 60/50Hz REJECTION CRITERION * REFERENCE CAPACITOR tINT/t60Hz or tlNT/t60Hz = Integer 0.1F < CREF < 1F * OPTIMUM INTEGRATION CURRENT * VCOM Biased between Vi and V-. IINT = 4A * FULL SCALE ANALOG INPUT VOLTAGE * VCOM V+ - 2.8V Regulation lost when V+ to V- < 6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. VlNFS (Typ) = 200mV or 2V * INTEGRATE RESISTOR V INFS R INT = ---------------I INT * ICL7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND V+ - 4.5V * INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = ------------------------------V INT * ICL7106 DISPLAY: LCD * INTEGRATOR OUTPUT VOLTAGE SWING ( t INT ) ( I INT ) V INT = ------------------------------C INT Type: Direct drive with digital logic supply amplitude. * ICL7107 POWER SUPPLY: DUAL 5.0V V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND * VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V * ICL7107 DISPLAY: LED Type: Non-Multiplexed Common Anode Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC 5 FN3082.8 ICL7106, ICL7107, ICL7107S Detailed Description output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: Analog Section V IN DISPLAY COUNT = 1000 --------------- . V REF Figure 3 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10V. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the STRAY STRAY CREF CREF+ REF HI 34 36 V+ RINT REF LO 35 CREF - CAZ BUFFER V+ 33 1 28 CINT A-Z INT 29 27 INTEGRATOR A-Z A-Z - - 10A + + 31 - + 2.8V TO DIGITAL SECTION IN HI DE- INT DE+ 6.2V INPUT HIGH A-Z A-Z N DE+ 32 DE- COMPARATOR - + COMMON INT INPUT LOW A-Z AND DE() 30 IN LO V- FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 6 FN3082.8 ICL7106, ICL7107, ICL7107S Analog COMMON V+ This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (15), and a temperature coefficient typically less than 80ppm/xoC. The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25V to 80VP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-overrange count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10A of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. 7 V REF HI 6.8V ZENER REF LO IZ ICL7106 ICL7107 V- FIGURE 4A. V+ V 6.8k 20k ICL7106 ICL7107 ICL8069 1.2V REFERENCE REF HI REF LO COMMON FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500 resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. V+ 1M TO LCD DECIMAL POINT ICL7106 BP TEST 21 37 TO LCD BACKPLANE FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT The second function is a "lamp test". When TEST is pulled high (to V+) all segments will be turned on and the display should read "1888". The TEST pin will sink about 15mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. FN3082.8 ICL7106, ICL7107, ICL7107S absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. V+ V+ BP ICL7106 TO LCD DECIMAL POINTS DECIMAL POINT SELECT Figure 8 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. TEST CD4030 GND FIGURE 6. EXCLUSIVE `OR' GATE FOR DECIMAL POINT DRIVE Digital Section In both devices, the polarity indication is "on" for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. Figures 7 and 8 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to a a f a g b e a f b b f g c e c d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE /200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK /4 LOGIC CONTROL 6.2V 500 THREE INVERTERS INTERNAL DIGITAL GROUND ONE INVERTER SHOWN FOR CLARITY TEST VTH = 1V 37 26 40 OSC 1 39 OSC 2 38 V- OSC 3 FIGURE 7. ICL7106 DIGITAL SECTION 8 FN3082.8 ICL7106, ICL7107, ICL7107S a a a f g b f b e a f b g c e c d e c d 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ b g c d 7 SEGMENT DECODE 7 SEGMENT DECODE LATCH 0.5mA TO SEGMENT 1000's COUNTER 100's COUNTER 10's COUNTER 1's COUNTER 8mA TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND V+ 1 V+ CLOCK /4 37 LOGIC CONTROL THREE INVERTERS 27 ONE INVERTER SHOWN FOR CLARITY 40 OSC 1 TEST 500 39 OSC 2 DIGITAL GROUND 38 OSC 3 FIGURE 8. ICL7107 DIGITAL SECTION System Timing INTERNAL TO PART Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: /4 CLOCK /4 CLOCK 1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 9 40 39 38 GND ICL7107 TEST ICL7106 FIGURE 9A. INTERNAL TO PART 40 39 38 R C RC OSCILLATOR FIGURE 9B. FIGURE 9. CLOCK CIRCUITS FN3082.8 ICL7106, ICL7107, ICL7107S Component Value Selection Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100A of quiescent current. They can supply 4A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470k is near optimum and similarly a 47k for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7106 or the ICL7107, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7107 with +5V supplies and analog COMMON tied to supply ground, a 3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22F and 0.10F, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47F capacitor is recommended. On the 2V scale, a 0.047F capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor Reference Voltage The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 120k and 0.22F. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7107 with 5V supplies can accept input signals up to 4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. ICL7107 Power Supplies The ICL7107 is designed to work from 5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See ICL7660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than 1.5V. 3. An external reference is used. V+ A 0.1F capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1F will hold the roll-over error to 0.5 count in this instance. Oscillator Components CD4009 V+ OSC 1 1N914 OSC 2 OSC 3 0.047 F + 10 F - ICL7107 For all ranges of frequency a 100k resistor is recommended and the capacitor is selected from the equation: 0.45 f = ----------- For 48kHz Clock (3 Readings/sec), RC 1N914 GND V- V- = 3.3V C = 100pF. FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V 10 FN3082.8 ICL7106, ICL7107, ICL7107S Typical Applications Application Notes The ICL7106 and ICL7107 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of these A/D converters. The following application notes contain very useful information on understanding and applying this part and are available from Intersil Corporation. NOTE # DESCRIPTION AN016 "Selecting A/D Converters" AN017 "The Integrating A/D Converter" AN018 "Do's and Don'ts of Applying A/D Converters" AN023 "Low Cost Digital Panel Meter Designs" AN032 "Understanding the Auto-Zero and Common Mode Performance of the ICL7136/7/9 Family" AN046 "Building a Battery-Operated Auto Ranging DVM with the ICL7106" AN052 "Tips for Using Single Chip 31/2 Digit A/D Converters" AN9609 "Overcoming Common Mode Range Issues When Using Intersil Integrating Converters" Typical Applications TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100k OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF HI 36 REF HI 36 REF LO 35 REF LO 35 CREF 34 CREF 33 1k 22k CREF 34 0.1F COMMON 32 CREF 33 1M A-Z 29 - 47k BUFF 28 + 9V - INT 27 V - 26 IN 0.01F 0.47F 0.22F G2 25 C3 24 A3 23 SET VREF = 100mV 100pF +5V 1k 22k 0.1F COMMON 32 + IN HI 31 IN LO 30 100k OSC 2 39 1M + IN HI 31 IN LO 30 A-Z 29 BUFF 28 IN 0.01F 0.47F - 47k INT 27 V - 26 0.22F -5V G2 25 TO DISPLAY G3 22 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE GND 21 Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). Values shown are for 200mV full scale, 3 readings/sec. IN LO may be tied to either COMMON for inputs floating with respect to supplies, or GND for single ended inputs. (See discussion under Analog COMMON). FIGURE 11. ICL7106 USING THE INTERNAL REFERENCE FIGURE 12. ICL7107 USING THE INTERNAL REFERENCE 11 FN3082.8 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100k OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 OSC 3 38 SET VREF = 100mV 100pF TEST 37 REF HI 36 CREF 33 V+ 1k 10k 10k CREF 33 1.2V (ICL8069) 1M A-Z 29 BUFF 28 0.47F IN IN LO 30 - A3 23 1M V- V - 26 C3 24 TO DISPLAY A3 23 G3 22 IN LO is tied to supply COMMON establishing the correct common mode voltage. If COMMON is not shorted to GND, the input voltage may float with respect to the power supply and COMMON acts as a pre-regulator for the reference. If COMMON is shorted to GND, the input is single ended (referred to supply GND) and the pre-regulator is overridden. FIGURE 13. ICL7107 WITH AN EXTERNAL BAND-GAP REFERENCE (1.2V TYPE) 47k 0.22F Since low TC zeners have breakdown voltages ~ 6.8V, diode must be placed across the total supply (10V). As in the case of Figure 12, IN LO may be tied to either COMMON or GND. FIGURE 14. ICL7107 WITH ZENER DIODE REFERENCE TO PIN 1 OSC 1 40 100k OSC 2 39 OSC 3 38 SET VREF = 1V 100pF TEST 37 V+ 25k 24k CREF 33 1M + - BUFF 28 15k 0.1F 1.2V (ICL8069) 1M + IN 0.01F 0.47F - 47k INT 27 INT 27 0.22F V - 26 V- G2 25 A3 23 IN LO 30 A-Z 29 470k BUFF 28 10k IN HI 31 IN 0.01F 0.047F +5V 1k COMMON 32 IN HI 31 A-Z 29 REF LO 35 CREF 34 0.1F COMMON 32 C3 24 SET VREF = 100mV 100pF REF HI 36 REF HI 36 REF LO 35 V - 26 100k OSC 2 39 OSC 3 38 IN LO 30 -5V TO DISPLAY TO PIN 1 CREF 33 - G2 25 GND 21 CREF 34 IN 0.47F INT 27 0.22F G3 22 TEST 37 + 0.01F BUFF 28 GND 21 OSC 1 40 6.8V 0.1F A-Z 29 47k G2 25 C3 24 100k IN HI 31 INT 27 V - 26 1k COMMON 32 + IN HI 31 0.01F +5V REF LO 35 CREF 34 0.1F COMMON 32 IN LO 30 SET VREF = 100mV 100pF REF HI 36 REF LO 35 CREF 34 100k G2 25 C3 24 TO DISPLAY 0.22F A3 23 TO DISPLAY G3 22 G3 22 GND 21 BP/GND 21 An external reference must be used in this application, since the voltage between V+ and V- is insufficient for correct operation of the internal reference. FIGURE 15. ICL7106 AND ICL7107: RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE 12 FIGURE 16. ICL7107 OPERATED FROM SINGLE +5V FN3082.8 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) TO PIN 1 OSC 1 40 TO PIN 1 V+ OSC 1 40 100k 100k OSC 2 39 OSC 2 39 OSC 3 38 OSC 3 38 100pF TEST 37 REF HI 36 REF HI 36 REF LO 35 REF LO 35 CREF 34 CREF 34 0.1F CREF 33 CREF 33 100k 1M 100k 220k 0.1F 22k COMMON 32 COMMON 32 IN HI 31 IN HI 31 IN LO 30 IN LO 30 0.47F 47k BUFF 28 ZERO ADJUST 0.01F 0.47F A-Z 29 A-Z 29 SILICON NPN MPS 3704 OR SIMILAR 47k BUFF 28 9V INT 27 INT 27 0.22F V - 26 V - 26 0.22F G2 25 G2 25 C3 24 C3 24 TO DISPLAY A3 23 A3 23 G3 22 G3 22 GND 21 BP 21 The resistor values within the bridge are determined by the desired sensitivity. FIGURE 17. ICL7107 MEASUREING RATIOMETRIC VALUES OF QUAD LOAD CELL TO DISPLAY TO BACKPLANE A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. FIGURE 18. ICL7106 USED AS A DIGITAL CENTIGRADE THERMOMETER +5V V+ TO LOGIC VCC 1 V+ OSC 1 40 1 V+ OSC 1 40 2 D1 OSC 2 39 2 D1 OSC 2 39 3 C1 OSC 3 38 3 C1 OSC 3 38 4 B1 TEST 37 4 B1 TEST 37 5 A1 REF HI 36 5 A1 REF HI 36 6 F1 REF LO 35 6 F1 REF LO 35 7 G1 CREF 34 7 G1 8 E1 O/RANGE TO CREF 34 LOGIC GND CREF 33 TO LOGIC VCC 8 E1 CREF 33 COMMON 32 COMMON 32 12k 9 D2 10 C2 IN HI 31 IN HI 31 IN LO 30 11 B2 IN LO 30 12 A2 A-Z 29 The LM339 is required to ensure logic compatibility with heavy display loading. 10 C2 11 B2 12 A2 A-Z 29 13 F2 BUFF 28 LM339 13 F2 BUFF 28 14 E2 INT 27 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 9 D2 + - V- U/RANGE CD4023 OR 74C10 SCALE FACTOR ADJUST 100pF TEST 37 O/RANGE + - + - U/RANGE CD4023 OR 74C10 - 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 V- + 33k CD4077 FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM ICL7106 OUTPUTS 13 FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUT FN3082.8 ICL7106, ICL7107, ICL7107S Typical Applications (Continued) TO PIN 1 OSC 1 40 100k OSC 2 39 10F SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 TEST 37 100pF 5F CA3140 REF HI 36 - REF LO 35 CREF 34 CREF 33 100k + AC IN 1N914 1k 22k 470k 0.1F 2.2M COMMON 32 10k 1F IN HI 31 1F 10k 1F 4.3k IN LO 30 0.47F A-Z 29 0.22F 47k BUFF 28 10F + 9V - INT 27 100pF (FOR OPTIMUM BANDWIDTH) 0.22F V - 26 G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 TO BACKPLANE Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 21. AC TO DC CONVERTER WITH ICL7106 +5V LED SEGMENTS DM7407 ICL7107 130 130 130 FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT 14 FN3082.8 ICL7106, ICL7107, ICL7107S Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -BD A2 SEATING PLANE e B1 D1 A1 eC B 0.010 (0.25) M C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - 0.13 A L D1 MIN A E -C- MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 50.3 53.2 5 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 15 FN3082.8 ICL7106, ICL7107, ICL7107S Metric Plastic Quad Flatpack Packages (MQFP) D Q44.10x10 (JEDEC MS-022AB ISSUE B) 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES SYMBOL -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M 0.008 C A-B S 0o MIN D S b A2 A1 0o-7o L b1 MILLIMETERS MIN MAX NOTES A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 - N 44 44 7 e 0.032 BSC 0.80 BSC Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. BASE METAL WITH PLATING MAX 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 12o-16o MIN 7. "N" is the number of terminal positions. 0.13/0.23 0.005/0.009 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN3082.8