MIC45404YMP-TR - MICROCHIP TECHNOLOGY

 2015 Microchip Technology Inc. DS20005478A-page 1

MIC45404

Features

• Input Voltage Range: 4.5V to 19V

• Output Current: Up to 5A

• 82% Peak Efficiency at 12 VIN, 0.9 VOUT

• Pin-Selectable Output Voltages: 0.7V, 0.8V, 0.9V,

1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V

• ±1% Output Voltage Accuracy

• Supports Safe Pre-Biased Start-up

• Pin-Selectable Current Limit

• Pin-Selectable Switching Frequency

• Internal Soft Start

• Thermal Shutdown

• Hiccup Mode Short-Circuit Protection

• Available in a 54-Lead 6 mm x 10 mm QFN

Package

• Ultra-Low Profile: 2.0 mm Height

• -40°C to +125°C Junction Temperature Range

Applications

• Servers, Data Storage, Routers and Base Stations

• FPGAs, DSP and Low-Voltage ASIC Power

General Description

The MIC45404 device is an ultra-low profile, synchro-

nous step-down regulator module, featuring a unique

2.0 mm height. The module incorporates a DC-to-DC

regulator, bootstrap capacitor, high-frequency input

capacitor and an inductor in a single package. The

module pinout is optimized to simplify the Printed

Circuit Board (PCB) layout process.

This highly integrated solution expedites system

design and improves product time to market. The inter-

nal MOSFETs and inductor are optimized to achieve

high efficiency at low output voltage. Due to the fully

optimized design, MIC45404 can deliver up to 5A

current with a wide input voltage range of 4.5V to 19V.

The MIC45404 is available in a 54-lead 6 mm x

10 mm x 2.0 mm QFN package with a junction operat-

ing temperature range from -40C to +125C, which

makes an excellent solution for systems in which PCB

real-estate and height are important limiting factors,

and air flow is restricted.

Typical Applicat ion

MIC45404 12V 5A DC-to-DC Co nverte r

VIN

OUT

VIN

4.5V to 19V

FREQ

VDDA

VOSET1

GND

VOSET0

COMP

EN/DLY

OUTSNS

MIC45404

VDDA

Power-Good

Enable

VDDA

Output

Voltage

Selection

VDDA

Frequency

Selection

ILIM

VDDA

Current Limit

Selection

VOUT

19V 5A Ultra-Low Profile DC-to-DC Power Module

MIC45404

DS20005478A-page 2  2015 Microchip Technology Inc.

Package Types

Functional Diagram

MIC45404

6 mm x 10 mm QFN*

(Bottom View)

KEEPOUT

GND

BST

VDDA

OUT

GND

KEEPOUT

AGND

VOSET1

OUTSNS

SNS

VOSET0

VDDP

OUT

OUT19

GND

VIN

KEEPOUT

BST 42

ILIM

FREQ

GND

COMP

OUTSNS

KEEPOUT

OUT

6GND_EXT

5GND_EXT

MIC45404YMP

GND_EP

* Includes Exposed Thermal Pad (EP); see Table 3-1.

BST

ILIM

FREQ

VDDA

VOSET1

AGND

VOSET0

COMP

EN/DLY

OUTSNS

VIN

PGND

VDDP

PWM

Regulator

100 nF

47 pF

BST

VOSET1

AGND

VOSET0

GND_EP

OUTSNS

GND

COMP

OUT

ILIM

FREQ

VDDA

EN/DLY

VIN

VDDP

GND_EXT

VDDP

LDO

VIN

 2015 Microchip Technology Inc. DS20005478A-page 3

MIC45404

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maxim um Ratings†

VIN to AGND ................................................................................................................................................ -0.3V to +20V

VDDP

, VDDA to AGND ..................................................................................................................................... -0.3V to +6V

VDDP to VDDA ............................................................................................................................................ -0.3V to +0.3V

VOSETX, FREQ, ILIM, to AGND .................................................................................................................... -0.3V to +6V

BST to LX..................................................................................................................................................... -0.3V to +6V

BST to AGND .............................................................................................................................................. -0.3V to +26V

EN/DLY to AGND...................................................................................................................... -0.3V to VDDA + 0.3V, +6V

PG to AGND .................................................................................................................................................. -0.3V to +6V

COMP, OUTSNS to AGND ....................................................................................................... -0.3V to VDDA + 0.3V, +6V

AGND to GND ............................................................................................................................................ -0.3V to +0.3V

Junction Temperature .......................................................................................................................................... +150°C

Storage Temperature (TS)...................................................................................................................... -65°C to +150°C

Lead Temperature (soldering, 10s) ........................................................................................................................ 260°C

ESD Rating(1)

HBM ........................................................................................................................................................................... 2kV

MM ........................................................................................................................................................................... 150V

CDM....................................................................................................................................................................... 1500V

Note 1: Devices are ESD-sensitive. Handling precautions are recommended. Human body model, 1.5 k in series

with 100 pF.

Operating Rati ngs(1)

Supply Voltage (VIN) ..................................................................................................................................... 4.5V to 19V

Externally Applied Analog and Drivers Supply Voltage (VIN = VDDA = VDDP) .............................................. 4.5V to 5.5V

Enable Voltage (EN/DLY)............................................................................................................................... 0V to VDDA

Power Good (PG) Pull-up Voltage (VPU_PG) ................................................................................................ 0V to 5.5V

Output Current ............................................................................................................................................................. 5A

Junction Temperature (TJ) ..................................................................................................................... -40°C to +125°C

Note 1: The device is not ensured to function outside the operating range.

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in

the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended

periods may affect device reliability.

MIC45404

DS20005478A-page 4  2015 Microchip Technology Inc.

ELECTR ICAL CHARACTERISTICS (1)

Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

Boldface values indicate -40°C  TJ  +125°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions

VIN Supply

Input Range VIN 4.5 —19 V

Disable Current IVINQ —3360 µA EN/DLY = 0V

Operating Current IVINOp —5.358.5 mA EN/DLY > 1.28V,

OUTSNS = 1.15 x VOUT(NOM),

no switching

VDDA 5V Supply

Operating Voltage VDDA 4.8 5.1 5.4 V EN/DLY > 0.58V,

IVDDA = 0 mA to 10 mA

Dropout Operation 3.6 3.75 — V VIN = 4.5V, EN/DLY > 0.58V,

IVDDA = 10 mA

VDDA Undervoltage Lockout

VDDA UVLO Rising UVLO_R 3.1 3.5 3.9 VV

DDA Rising, EN/DLY > 1.28V

VDDA UVLO Falling UVLO_F 2.87 3.2 3.45 VV

DDA Falling, EN/DLY > 1.28V

VDDA UVLO Hysteresis UVLO_H — 300 — mV

EN/DLY Control

LDO Enable Threshold EN_LDO_R — 515 600 mV Turns on VDDA LDO

LDO Disable Threshold EN_LDO_F 450 485 — mV Turns off VDDA LDO

LDO Threshold Hysteresis EN_LDO_H — 30 — mV

EN/DLY Rising Threshold EN_R 1.14 1.21 1.28 V Initiates power stage operation

EN/DLY Falling Threshold EN_F — 1.06 — V Stops power stage operation

EN/DLY Hysteresis EN_H — 150 — mV

EN/DLY Pull-up Current EN_I 123µA

Switching Frequ ency

Programmable

Frequency (High Z)

fSZ 360 400 440 kHz FREQ = High Z (open)

Programmable Frequency 0 fS0 500 565 630 kHz FREQ= Low (GND)

Programmable Frequency 1 fS1 700 790 880 kHz FREQ = High (VDDA)

Overcurrent Protection

HS Current Limit 0 ILIM_HS0 6.0 7.1 8.1 AI

LIM = Low (GND)

HS Current Limit 1 ILIM_HS1 8.1 9.3 10.3 AI

LIM = High (VDDA)

HS Current Limit High Z ILIM_HSZ 9.3 10.5 11.9 AI

LIM = High Z (open)

Top FET Current Limit

Leading-Edge Blanking Time

LEB — 108 — ns

LS Current Limit 0 ILIM_LS0 3.0 4.6 6.3 AI

LIM = Low (GND)

LS Current Limit 1 ILIM_LS1 4.0 6.2 7.9 AI

LIM = High (VDDA)

LS Current Limit High Z ILIM_LSZ 5.0 6.8 8.6 AI

LIM = High Z (Open)

OC Events Count for Hiccup INHICC_DE —15—Clock

Cycles

Number of subsequent cycles

in current limit before entering

hiccup overload protection

Hiccup Wait Time tHICC_WAIT —3xSoft

Start Time

— Duration of the High Z state on

LX before new soft start.

Note 1: Specification for packaged product only.

 2015 Microchip Technology Inc. DS20005478A-page 5

MIC45404

Pulse-Width Modulation (PWM)

Minimum LX On Time TON(MIN) —26—nsT

A = TJ = +25°C

Minimum LX Off time TOFF(MIN) 90 135 190 ns VIN = VDDA = 5V, OUTSNS = 3V,

FREQ = Open (400 kHz setting),

VOSET0 = VOSET1 = 0V

(3.3V setting),

TA = TJ = +25°C

Minimum Duty Cycle DMIN —0—%OUTSNS>1.1xV

OUT(NOM)

Gm Error Amplifier

Error Amplifier

Transconductance

GmEA —1.4—mS

Error Amplifier DC Gain AEA —50000—V/V

Error Amplifier Source/Sink

Current

ISR_SNK -400 — +400 µA TA = TJ = +25°C

COMP Output Swing High COMP_H — 2.5 — V

COMP Output Swing Low COMP_L — 0.8 — V

COMP-to-Inductor Current

Transconductance

GmPS — 12.5 — A/V VOUT = 1.2V, IOUT = 4A

Output Voltage DC Accuracy

Output Voltage Accuracy for

Ranges 1 and 2

OutErr12 -1 —1%4.75V  VIN  19V,

VOUT = 0.7V to 1.8V,

TA = TJ = -40°C to +125°C,

IOUT = 0A

Output Voltage Accuracy for

Range 3

OutErr3 -1.5 —1.5 %4.75V  VIN  19V,

VOUT = 2.49V to 3.3V,

TA = TJ = -40°C to +125°C,

IOUT = 0A

Load Regulation LoadReg — 0.03 — % IOUT = 0A to 5A

Line Regulation LineReg — 0.01 — % 6V < VIN <19V, I

OUT = 2A

Internal Soft Start

Reference Soft Start

Slew Rate

SS_SR — 0.42 — V/ms VOUT = 0.7V, 0.8V, 0.9V,

1.0V, 1.2V

Po we r Good (PG)

PG Low Voltage PG_VOL —0.170.4 VI

PG =4mA

PG Leakage Current PG_ILEAK -1 0.02 1µA PG = 5V

PG Rise Threshold PG_R 90 92 95 %V

OUT Rising

PG Fall Threshold PG_F 87.5 90 92.5 %V

OUT Falling

PG Rise Delay PG_R_DLY — 0.45 — ms VOUT Rising

PG Fall Delay PG_F_DLY — 80 — µs VOUT Falling

ELECTR ICAL CHARACTERISTICS (1) (CONTINUED)

Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

Boldface values indicate -40°C  TJ  +125°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions

Note 1: Specification for packaged product only.

MIC45404

DS20005478A-page 6  2015 Microchip Technology Inc.

Thermal Shutdown

Thermal Shutdown TSHDN —160—°C

Thermal Shutdown

Hysteresis

TSHDN_HYST —25—°C

Efficiency

Efficiency η—82—%V

IN = 12V, VOUT = 0.9V,

IOUT = 2A, fS = fSZ = 400 kHz,

TA = +25°C

ELECTR ICAL CHARACTERISTICS (1) (CONTINUED)

Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

Boldface values indicate -40°C  TJ  +125°C.

Parameter Symbol Min. Typ. Max. Units Test Conditions

Note 1: Specification for packaged product only.

TEMP ERATURE SPECIFICATIONS

Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

Boldface values indicate -40°C  TJ  +125°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature Ranges

Operating Ambient Junction Range TJ-40 — +125 °C

Storage Temperature Range TA-65 — +150 °C

Maximum Junction Temperature TJ-40 — +150 °C

Package Thermal Resistances

Thermal Resistance, 54 Lead,

6 mm x10 mm QFN

JA —20 —°C/WSee “MIC45404 Evaluation

Boar d User’s Guide”

 2015 Microchip Technology Inc. DS20005478A-page 7

MIC45404

2.0 TY PICAL PERFORM ANCE CURVES

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-1: Operating Current (IQ) vs.

Input Voltage.

FIGURE 2-2: VDDA Voltage vs. Input

Voltage.

FIGURE 2-3: Output Current Limit vs.

Input Voltage.

FIGURE 2-4: Enable Threshold vs. Input

Voltage.

FIGURE 2-5: EN/DLY Pull-up Current vs.

Input Voltage.

FIGURE 2-6: Operating Current (IQ) vs.

Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

15.00

17.00

19.00

21.00

23.00

25.00

27.00

29.00

31.00

33.00

35.00

4 6 8 101214161820

IQ (mA)

VIN (V)

f = 565 kHz

VOUT = 1.8V

f = 400 kHz

VOUT = 1.0V

Switching

IOUT = 0A

f = 790 kHz

VOUT = 3.3V

4.2

4.4

4.6

4.8

5.2

4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5

VDDA (V)

VIN (V)

IoutSet 0

IoutSet 0.01

= 0 mA

IVDDA = 10 mA

5.5

6.5

7.5

8.5

4.5 5 5.5 6 8 101214161819

IOUT (A)

VIN(V)

ILIM = GND

ILIM = VDDA

ILIM = high Z

VOUT = 1.2V

f = 400 kHz

0.9

0.95

1.05

1.1

1.15

1.2

1.25

1.3

4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5

Enable (V)

VIN (V)

Enable rising

Enable falling

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Current (µA)

VIN (V)

EN/DLY = 0V

-40-25-105 203550658095110125

IQ (mA)

Temperature (°C)

Switching

VIN = 12V

IOUT = 0A

f = 565 kHz

VOUT = 1.8V

f = 790 kHz

VOUT = 3.3V

f = 400 kHz

VOUT = 1.0V

MIC45404

DS20005478A-page 8  2015 Microchip Technology Inc.

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-7: EA Output Current vs.

Temperature.

FIGURE 2-8: EA Transconductance vs.

Temperature.

FIGURE 2-9: Efficiency vs. Output

Current (VIN =12V).

FIGURE 2-10: Efficiency vs. Output

Current (VIN =5V).

FIGURE 2-11: Output Voltage vs. Output

Current (VOUT =0.9V).

FIGURE 2-12: Output Voltage vs. Output

Current (VOUT =1.0V).

-800

-600

-400

-200

200

400

600

800

-40 -20 0 20 40 60 80 100 120 140

EA Output Current (µA)

Temperature(°C)

VIN = 12V

Sinking

Sourcing

0.6

0.8

1.2

1.4

1.6

1.8

-40-200 20406080100120140

EA Transconductance (mS)

Temperature (°C)

VIN = 12V

VOUT = 1.0V

0.00%

10.00%

20.00%

30.00%

40.00%

50.00%

60.00%

70.00%

80.00%

90.00%

100.00%

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Efficiency (%)

IOUT (A)

0.7V

0.8V

0.9V

1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

0.00%

10.00%

20.00%

30.00%

40.00%

50.00%

60.00%

70.00%

80.00%

90.00%

100.00%

00.511.522.533.544.55

Efficiency (%)

IOUT (A)

0.7V

0.8V

0.9V

1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

0.891

0.893

0.895

0.897

0.899

0.901

0.903

0.905

0.907

0.909

00.511.522.533.544.55

VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

0.990

0.995

1.000

1.005

1.010

00.511.522.533.544.55

VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

 2015 Microchip Technology Inc. DS20005478A-page 9

MIC45404

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-13: Output Voltage vs. Output

Current (VOUT =1.2V).

FIGURE 2-14: Output Voltage vs. Output

Current (VOUT =1.5V).

FIGURE 2-15: Output Voltage vs. Output

Current (VOUT =1.8V).

FIGURE 2-16: Output Voltage vs. Output

Current (VOUT =2.5V).

FIGURE 2-17: Output Voltage vs. Output

Current (VOUT =3.3V).

1.190

1.192

1.194

1.196

1.198

1.200

1.202

1.204

1.206

1.208

1.210

00.511.522.533.544.55

VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

1.490

1.495

1.500

1.505

1.510

00.511.522.533.544.55

VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

1.790

1.795

1.800

1.805

1.810

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

2.480

2.485

2.490

2.495

2.500

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VOUT (V)

IOUTt (A)

VIN = 12V

VIN = 5V

3.290

3.292

3.294

3.296

3.298

3.300

3.302

3.304

3.306

3.308

3.310

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VOUT (V)

IOUT (A)

VIN = 12V

VIN = 5V

MIC45404

DS20005478A-page 10  2015 Microchip Technology Inc.

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-18: VIN Turn-On.

FIGURE 2-19: VIN Turn-Off.

FIGURE 2-20: Enable Turn-On.

FIGURE 2-21: Enable Turn-Off.

FIGURE 2-22:

Enable S tart-up w/Pre-Biased

Output.

FIGURE 2-23: Enable Start-up

w/Pre-Biased Output.

VIN =12V

VOUT = 1.2V

RLOAD =0.3

fSW =400kHz

VIN

(5V/div)

VOUT

(500 mV/div)

(5V/div)

Time (2 ms/div)

VIN

(5V/div)

VOUT

(500 mV/div

(5V/div)

VIN =12V

VOUT = 1.2V

RLOAD =0.6

fSW =400kHz

Time (2 ms/div)

EN/DLY(2V/div

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

ROUT =0.24

fSW = 400 kHz IOUT(2A/div)

Time (1 ms/div)

EN/DLY(2V/div

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

ROUT =0.24

fSW = 400 kHz

IOUT(2A/div)

Time (40 µs/div)

EN/DLY(2V/div

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

VPRE-BIAS =0.6V

fSW =400kHz

Time (1 ms/div)

EN/DLY(2V/div

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

VPRE-BIAS =1.0V

fSW = 400 kHz

Time (1 ms/div)

 2015 Microchip Technology Inc. DS20005478A-page 11

MIC45404

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-24: Power-up into Short Circuit.

FIGURE 2-25: Enable into Short Circuit.

FIGURE 2-26: Output Current Limit

(ILIM =0V).

FIGURE 2-27: Output Current Limit

(ILIM =High Z).

FIGURE 2-28: Hiccup Mode Short Circuit

and Output Recovery.

FIGURE 2-29: Thermal Shutdown and

Thermal Recovery.

VIN(5V/div)

VOUT (500 mV/div)

PG(5V/div)

IOUT(5A/div)

Time (1 ms/div)

EN/DLY(2V/div

VOUT (500 mV/div)

PG(5V/div)

IOUT(5A/div)

Time (1 ms/div)

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

fSW = 400 kHz

ILIM =0V

IOUT(2A/div)

Time (1 ms/div)

VOUT (500 mV/div)

PG(5V/div)

VIN =12V

VOUT = 1.2V

fSW = 400 kHz

ILIM = high Z

IOUT(2A/div)

Time (1 ms/div)

VOUT (500 mV/div)

PG(5V/div)

IOUT(2A/div)

Time (20 ms/div)

IOUT(2A/div)

VOUT (500 mV/div)

PG(5V/div)

Time (200 ms/div)

MIC45404

DS20005478A-page 12  2015 Microchip Technology Inc.

Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.

FIGURE 2-30: Switching Waveforms

(IOUT =0A).

FIGURE 2-31: Switching Waveforms

(IOUT =5A).

FIGURE 2-32: Load Transient Response.

FIGURE 2-33: Line Transient Response.

VIN

AC-Coupled

(20 mV/div)

VOUT

AC-Coupled

(10 mV/div)

SW (5V/div)

Time (1 µs/div)

VIN = 12V

VOUT = 1.2V

IOUT =0A

fSW = 400 kHz

VIN

AC-Coupled

(100 mV/div)

VOUT

AC-Coupled

(10 mV/div)

SW (5V/div)

Time (1 µs/div)

VIN = 12V

VOUT = 1.2V

IOUT =5A

fSW = 400 kHz

IOUT

(2A/div)

VOUT

AC-Coupled

(100 mV/div)

PG (5V/div)

VIN = 12V

VOUT = 1.0V

RLOAD =1 to 0.3

Time (100 µs/div)

VIN

(2V/div)

VOUT

AC-Coupled

(20 mV/div)

PG(5V/div)

Time (1 ms/div)

 2015 Microchip Technology Inc. DS20005478A-page 13

MIC45404

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3 - 1.

3.1 Output Sensing Pins (OUTSNS)

Connect these pins directly to the Buck Converter

output voltage. These pins are the top side terminal of

the internal feedback divider.

3.2 Precision Enable/Turn-On Delay

Input Pin (EN/DLY)

The EN/DLY pin is first compared against a 515 mV

threshold to turn on the on-board LDO regulator. The

EN/DLY pin is then compared against a 1.21V (typical)

threshold to initiate output power delivery. A 150 mV

typical hysteresis prevents chattering when power

delivery is started. A 2 µA (typical) current source pulls

up the EN/DLY pin. Turn-on delay can be achieved by

connecting a capacitor from EN/DLY to ground, while

using an open-drain output to drive the EN/DLY pin.

3.3 MOSFET Drivers Internal

Supply Pin (VDDP)

Internal supply rail for the MOSFET drivers, fed by the

VDDA pin. An internal resistor (10) between the VDDP

and VDDA pins, and an internal decoupling capacitor

are provided in the module in order to implement an RC

filter for switching noise suppression.

3.4 Internal Regulator Output Pin

(VDDA)

Output of the internal linear regulator and internal

supply for analog control. A 1 µF minimum ceramic

capacitor should be connected from this pin to GND; a

2.2 µF nominal value is recommended.

TABLE 3-1: PIN FUNCTION TABLE

MIC45404 Symbol Pin Function

1, 54 OUTSNS Output Sensing Pin

2 EN/DLY Precision Enable/Turn-On Delay Input Pin

DDP MOSFET Drivers Internal Supply Pin

DDA Internal LDO Output and Analog Supply Pin

5, 6 GND_EXT Ground Extension Pins

7, 8 VIN Input Voltage Pins

9, 23, 24, 50, 51 GND Power Ground Pins

11, 12, 13, 14, 15, 16, 17, 18,

19, 20, 21

OUT Output Side Connection Pins

10, 22, 25, 40 KEEPOUT Depopulated Pin Positions

26, 27, 28, 29, 30, 31, 32, 33,

34, 35, 36, 37, 38, 39

LX Switch Node Pins

41, 42 BST Bootstrap Capacitor Pin

43 PG Power Good Output Pin

44 VOSET0 Output Voltage Selection Pins

45 VOSET1

46, 47 NC Not Connected Pins

48 ILIM Current Limit Selection Pin

49 FREQ Switching Frequency Selection Pin

52 AGND Analog Ground Pin

53 COMP Compensation Network Pin

55 GND_EP Ground Exposed Pad.

MIC45404

DS20005478A-page 14  2015 Microchip Technology Inc.

3.5 Ground Extension Pins

(GND_EXT)

These pins are used for the bottom terminal connection

of the internal VIN and VDDP decoupling capacitors.

The GND_EXT pins should be connected to the GND

net, directly at the top layer, using a wide copper

connection.

3.6 Input Voltage Pins (VIN)

Input voltage for the Buck Converter power stage and

input of the internal linear regulator. These pins are the

drain terminal of the internal high-side N-channel

MOSFET. A 10 µF (minimum) ceramic capacitor should

be connected from VIN to GND, as close as possible to

the device.

3.7 Power Ground Pins (GND)

Connect the output capacitors to GND Pins 23 and 24,

as close as possible to the module.

Connect the input capacitors to GND Pin 9, as close as

possible to the module.

3.8 Output-Side Connection Pins

(OUT)

Output side connection of the internal inductor. The

output capacitors should be connected from this pin

group to GND (Pins 23 and 24), as close to the module

as possible.

3.9 Switch Node Pins (LX)

Switch Node: Drain (low-side MOSFET) and source

(high-side MOSFET) connection of the internal power

N-channel FETs. The internal inductor switched side

and the bootstrap capacitor are connected to LX.

Leave this pin floating.

3.10 Bootstrap Capacit or Pin (BST)

Connection to the internal bootstrap capacitor and

high-side power MOSFET drive circuitry. Leave this pin

floating.

3.11 Power Good Output Pin (PG)

When the output voltage is within 92.5% of the nominal

set point, this pin will go from logic low to logic high

through an external pull-up resistor. This pin is the drain

connection of an internal N-channel FET.

3.12 Output Voltage Selection Pins

(VOSET0 and VOSET1)

Three-state pin (low, high and High Z) for output volt-

age programming. Both VOSET0 and VOSET1 define

9 logic values, corresponding to nine output voltage

selections.

3.13 Not Connected Pins (NC)

These pins are not internally connected. Leave them

floating.

3.14 Current Limit Pin (ILIM)

This pin allows the selection of the current limit state:

low, high and High Z.

3.15 Switching Frequency Pin (FREQ)

This pin allows the selection of the frequency state: low,

high and High Z.

3.16 Analog Ground Pin (AGND)

This pin is a quiet ground for the analog circuitry of the

internal regulator and a return terminal for the external

compensation network.

3.17 Compensation Network Pin

(COMP)

Connect a compensation network from this pin to

AGND.

3.18 GND Exposed Pad

Connect to ground plane with thermal vias.

 2015 Microchip Technology Inc. DS20005478A-page 15

MIC45404

4.0 FUNCTIONAL DESCRIPTION

The MIC45404 is a pin-programmable, 5A Valley

Current mode controlled power module, with an input

voltage range from 4.5V to 19V.

The MIC45404 requires a minimal amount of external

components. Only two supply decoupling capacitors

and a compensation network are external. The

flexibility in designing the external compensation

allows the user to optimize the design across the entire

input voltage and selectable output voltages range.

4.1 Theory of Operation

Valley Current mode control is a fixed frequency, lead-

ing-edge modulated Pulse-Width Modulation (PWM)

Current mode control. Differing from the Peak Current

mode, the Valley Current mode clock marks the turn-off

of the high-side switch. Upon this instant, the

MIC45404 low-side switch current level is compared

against the reference current signal from the error

amplifier. When the falling low-side switch current sig-

nal drops below the current reference signal, the

high-side switch is turned on. As a result, the inductor

valley current is regulated to a level dictated by the

output of the error amplifier.

The feedback loop includes an internal programmable

reference and output voltage sensing attenuator, thus

removing the need for external feedback components

and improving regulation accuracy. Output voltage feed-

back is achieved by connecting the OUTSNS pin directly

to the output. The high-performance transconductance

error amplifier drives an external compensation network

at the COMP pin. The COMP pin voltage represents the

reference current signal. This pin voltage is fed to the

Valley Current mode modulator, which also adds slope

compensation to ensure current loop stability.

Internal inductor, power MOSFETs and internal

bootstrap diode complete the power train.

Overcurrent protection and thermal shutdown protect

the MIC45404 from Faults or abnormal operating

conditions.

4.2 Supply Rails (VIN, VDDA, VDDP)

and Internal LDO

VIN pins represent the power train input. These pins are

the drain connection of the internal high-side MOSFET

and should be bypassed to GND, at least with a X5R or

X7R 10 µF ceramic capacitor, placed as close as

possible to the module. Multiple capacitors are

recommended.

An internal LDO provides a clean supply (5.1V typical)

for the analog circuits at the VDDA pin. The internal LDO

is also powered from VIN, as shown in the Functional

Diagram. The internal LDO is enabled when the

voltage at the EN/DLY pin exceeds about 0.51V, and

regulation takes place as soon as enough voltage has

been established between the VIN and VDDA pins. An

internal Undervoltage Lockout (UVLO) circuit monitors

the level of VDDA. The VDDA pin needs external bypass-

ing to GND by means of a 2.2 µF X5R or X7R ceramic

capacitor, placed as close as possible to the module.

VDDP is the power supply rail for the gate drivers and

bootstrap circuit. This pin is bypassed to GND_EXT by

means of an internal high-frequency ceramic capacitor.

For this reason, the GND_EXT pins should be routed

with a low-inductance path to the GND net. An internal

10 resistor is provided between VDDA and VDDP

allowing the implementation of a switching noise atten-

uation RC filter with the minimum amount of external

components. It is possible, although typically not

necessary, to lower the RC time constant by connecting

an external resistor between VDDA and VDDP

If the input rail is within 4.5V to 5.5V, it is possible to

bypass the internal LDO by connecting VIN, VDDA and

VDDP together. Local decoupling of the VDDA pin is still

recommended.

4.3 Pin-Strapping Programmability

(VOSET0, VOSET1, FREQ, ILIM)

The MIC45404 uses pin strapping to set the output volt-

age (VOSET0, VOSET1), switching frequency (FREQ)

and current limit (ILIM). No external passives are needed,

therefore, the external component count is minimized.

Each pin is a three-state input (connect to GND for LOW

logic level, connect to VDDA for HIGH logic level or leave

unconnected for High Z). The logic level of the pins is

read and frozen in the internal configuration logic

immediately after the VDDA rail comes up and becomes

stabilized. After this instant, any change of the input logic

level on the pins will have no effect until the VDDA power

is cycled again. The values corresponding to each

particular pin strapping configuration are detailed in

Section 5.0 “Application Information”.

MIC45404

DS20005478A-page 16  2015 Microchip Technology Inc.

4.4 Enable/Delay (EN/DLY)

The EN/DLY pin is a dual threshold pin that turns the

internal LDO on/off and starts/stops the power delivery

to the output, as shown in Figure 4-1.

FIGURE 4-1: EN/DLY Pin Functionality.

The threshold for LDO enable is 515 mV (typical) with

a hysteresis of approximately 30 mV. This hysteresis is

enough because at the time of LDO activation, there is

still no switching activity.

The threshold for power delivery is a precise 1.21V,

±70 mV. A 150 mV typical hysteresis prevents chattering

due to switching noise and/or slow edges.

A 2 µA typical pull-up current, with ±1 µA accuracy, per-

mits the implementation of a start-up delay by means of

an external capacitor. In this case, it is necessary to use

an open-drain driver to disable the MIC45404 while

maintaining the start-up delay function.

4.5 Power Good (PG)

The PG pin is an open-drain output that requires an

external pull-up resistor to a pull-up voltage (VPU_PG),

lower than 5.5V, for being asserted to a logic HIGH

level. The PG pin is asserted with a typical delay of

0.45 ms when the output voltage (OUTSNS) reaches

92.5% of its target regulation voltage. This pin is

deasserted with a typical delay of 80 µs when the

output voltage falls below 90% of its target regulation

voltage. The PG falling delay acts as a deglitch timer

against very short spikes. The PG output is always

immediately deasserted when the EN/DLY pin is below

the power delivery enable threshold (EN_R/EN_F).

The pull-up resistor should be large enough to limit the

PG pin current to below 2 mA.

4.6 Inductor (LX, OUT) and Bootstrap

(BST) Pins

The internal inductor is connected across the LX and

OUT pins. The high-side MOSFET driver circuit is pow-

ered between BST and LX by means of an internal

capacitor that is replenished from rail VDDP during the

low-side MOSFET on time. The bootstrap diode is

internal.

4.7 Output Sensing (OUTSNS) and

Compensation (COMP) Pins

OUTSNS should be connected exactly to the desired

Point-of-Load (POL) regulation, avoiding parasitic

resistive drops. The impedance seen into the OUTSNS

pin is high (tens of k or more, depending on the

selected output voltage value), therefore, its loading

effect is typically negligible. OUTSNS is also used by

the slope compensation generator.

The COMP pin is the connection for the external com-

pensation network. COMP is driven by the output of the

transconductance error amplifier. Care must be taken

to return the compensation network ground directly to

AGND.

4.8 Soft Start

The MIC45404 internal reference is ramped up at a

0.42 V/ms rate. Note that this is the internal reference

soft start slew rate and that the actual slew rate seen at

the output should take into account the internal divider

attenuation, as detailed in the Section 5.0 “Application

Information”.

4.9 Switching Frequency (FREQ)

The MIC45404 features three different selectable

switching frequencies (400 kHz, 565 kHz and

790 kHz). Frequency selection is tied with a specific

output voltage selection, as described in Section 5.5

“Permissible MIC45404 Settings Combinations”.

4.10 Pre-Biased Output Start-up

The MIC45404 is designed to achieve safe start-up into

a pre-biased output without discharging the output

capacitors.

4.11 Thermal Shutdown

The MIC45404 has a thermal shutdown protection that

prevents operation at excessive temperature. The

thermal shutdown threshold is typically set at +160°C,

with a hysteresis of +25°C.

EN/DLY Enable Power

Comparator

EN_I

2 µA

AGND

EN_R

1.21V

VIN

Enable

Power

Delivery

150 mV

EN_LDO_R

515 mV

Enable LDO

Comparator

 2015 Microchip Technology Inc. DS20005478A-page 17

MIC45404

4.12 Overcurrent Protection (ILIM) and

Hiccup Mode Short-Circuit

Protection

The MIC45404 features instantaneous cycle-by-cycle

current limit with current sensing, both on the low-side

and high-side switches. It also offers a Hiccup mode for

prolonged overloads or short-circuit conditions.

The low-side cycle-by-cycle protection detects the cur-

rent level of the inductor current during the low-side

MOSFET on time. The high-side MOSFET turn-on is

inhibited as long as the low-side MOSFET current limit is

above the overcurrent threshold level. The inductor cur-

rent will continue decaying until the current falls below

the threshold, where the high-side MOSFET will be

enabled again, according to the duty cycle requirement

from the PWM modulator.

The low-side current limit has three different program-

mable levels (for 3A, 4A and 5A loads) in order to fit

different application requirements. Since the low-side

current limit acts on the valley current, the DC output

current level (IOUT), where the low-side cycle-by-cycle

current limit is engaged, will be higher than the current

limit value by an amount equal to ILPP/2, where ILPP

is the peak-to-peak inductor ripple current.

The high-side current limit is approximately

1.4-1.5 times greater than the low-side current limit

(typical values). The high-side cycle-by-cycle current

limit immediately truncates the high-side on time

without waiting for the off clocking event.

A Leading-Edge Blanking (LEB) timer (108 ns, typical)

is provided on the high-side cycle-by-cycle current limit

to mask the switching noise and to prevent falsely

triggering the protection. The high-side cycle-by-cycle

current limit action cannot take place before the LEB

timer expires.

Hiccup mode protection reduces power dissipation in

permanent short-circuit conditions. On each clock

cycle, where a low-side cycle-by-cycle current limit

event is detected, a 4-bit up/down counter is incre-

mented. On each clock cycle without a concurrent

low-side current limit event, the counter is decremented

or left at zero. The counter cannot wraparound below

‘0000’ and above ‘1111’. High-side current limit events

do not increment the counter. Only detections from

low-side current limit events trigger the counter.

If the counter reaches ‘1111’ (or 15 events), the high

and low-side MOSFETs become tri-stated, and power

delivery to the output is inhibited for the duration of

three times the soft start time. This digital integration

mechanism provides immunity to momentary overload-

ing of the output. After the wait time, the MIC45404

retries entering operation and initiates a new soft start

sequence.

MIC45404

DS20005478A-page 18  2015 Microchip Technology Inc.

Figure 4-2 illustrates the Hiccup mode short-circuit pro-

tection logic flow. Note that Hiccup mode short-circuit

protection is active at all times, including the soft start

ramp.

FIGURE 4-2: Hiccup Mode Short-Circuit Protection Logic.

START

CLEAR

LS OC EVENTS

COUNTER

CLOCK PULSE

(MARKING HS

TURN-OFF,

LS TURN-ON) IDLE LOOP

IN NORMAL

OPERATION

LS OC EVENT

DETECTED?

EVENT

COUNTER = 0

DECREMENT

EVENT

COUNTER

EVENT COUNTER

FULL?

INCREMENT

EVENT

COUNTER

INITIATE HICCUP

SEQUENCE

STOP SWITCHING

HS AND LS

CYCLE THREE TIMES

INTERNAL SOFT START

CAPACITOR

CLEAR

LS OC EVENTS

COUNTER

INITIATE SOFT START

ENABLE SWITCHING

YES

 2015 Microchip Technology Inc. DS20005478A-page 19

MIC45404

5.0 APPLICATION INFORMATION

5.1 Programming Start-up Delay and

External UVLO

The EN/DLY pin allows programming an external

start-up delay. In this case, the driver for the EN/DLY

pin should be an open-drain/open-collector type, as

shown in Figure 5-1.

FIGURE 5-1: Programmable Start-up Delay Function.

The start-up delay is the delay time from the off falling

edge to the assertion of the enable power delivery

signal. It can be calculated as shown in Equation 5-1:

EQUATION 5-1:

The EN/DLY pin can also be used to program a UVLO

threshold for power delivery by means of an external

resistor divider, as described in Figure 5-2.

FIGURE 5-2: Programmable External UVLO Function.

EN/DLY Enable Power

Comparator

EN_I

2 µA

AGND

EN_R

1.21V

VIN

Enable

Power

Delivery

150 mV

EN_LDO_R

515 mV

Enable LDO

Comparator

CDLY

Off

tSU_DLY EN_R CDLY



EN_I

-----------------------------------=

Where:

EN_R = 1.21V

EN_I = 2 µA

CDLY = Delay programming external capacitor

EN/DLY Enable Power

Comparator

EN_I

2 µA

AGND

EN_R

1.21V

VIN

Enable

Power

Delivery

150 mV

EN_LDO_R

515 mV

Enable LDO

Comparator

MIC45404

DS20005478A-page 20  2015 Microchip Technology Inc.

The programmed VIN UVLO threshold, VIN_RISE, is

given by:

EQUATION 5-2:

To desensitize the VIN UVLO threshold against varia-

tions of the pull-up current, EN_I, it is recommended to

run the R1–R

2 voltage divider at a significantly higher

current level than the EN_I current.

The corresponding VIN UVLO hysteresis, VIN_HYS, is

calculated as follows:

EQUATION 5-3:

Similar calculations also apply to the internal LDO

activation threshold.

5.2 Setting the Switching Frequency

The MIC45404 switching frequency can be

programmed using FREQ, as shown in Table 5-1.

The switching frequency setting is not arbitrary, but it

needs to be adjusted according to the particular output

voltage selection due to peak-to-peak inductor

ripple requirements. This is illustrated in Section 5.5

“Permissible MIC45404 Settings Combinations”.

5.3 Setting the O utput Voltage

The MIC45404 output voltage can be programmed by

setting pins, VOSET0 and VOSET1, as shown in

Table 5-2.

To achieve accurate output voltage regulation, the

OUTSNS pin (internal feedback divider top terminal)

should be Kelvin-connected as close as possible to the

point of regulation top terminal. Since both the internal

reference and the internal feedback divider’s bottom

terminal refer to AGND, it is important to minimize

voltage drops between the AGND and the point of

regulation return terminal.

5.4 Setting the Current Limit

The MIC45404’s valley-mode current limit on the

low-side MOSFET can be programmed by means of

ILIM as shown in Ta b l e 5 - 3 .

Note that the programmed current limit values act as

pulse-by-pulse, current limit thresholds on the valley

inductor current. If the inductor current has not decayed

below the threshold at the time the PWM requires a new

on time, the high-side MOSFET turn-on is either delayed,

until the valley current recovers below the threshold, or

skipped. Each time the high-side MOSFET turn-on is

skipped, a 4-bit up-down counter is incremented. When

the counter reaches the configuration ‘1111’, a hiccup

sequence is invoked in order to reduce power dissipation

under prolonged short-circuit conditions.

The highest current limit setting (6.8A) is intended to

comfortably accommodate a 5A application. Ensure

that the value of the operating junction temperature

does not exceed the maximum rating in high output

power applications.

TABLE 5-1: SWITCHING FREQUENCY

SETTINGS

FREQ Pin Setting Frequency

High Z (open) 400 kHz

0 (GND) 565 kHz

1 (VDDA) 790 kHz

VIN_RISE EN_R 1 R2

------+





EN_I R2



–



Where:

EN_R = 1.21V

EN_I = 2 µA

R1 and R2= External resistors

VIN_HYS 150 mV 1 R2

------+







TABLE 5-2: OUTPUT VOLTAGE SETTINGS

VOSET1 VOSET0 Output Voltage

0 (GND) 0 (GND) 3.3V

0 (GND) 1 (VDDA) 2.5V (2.49V)

1 (VDDA)0 (GND) 1.8V

1 (VDDA)1 (VDDA)1.5V

0 (GND) High Z (open) 1.2V

High Z (open) 0 (GND) 1.0V

1 (VDDA) High Z (open) 0.9V

High Z (open) 1 (VDDA)0.8V

High Z (open) High Z (open) 0.7V

TABLE 5-3: CURRENT LIMIT SETTINGS

ILIM V alley Current Limit

(Typical V alue) Rated Output

Current

0 (GND) 4.6 A 3A

1 (VDDA) 6.2 A 4A

High Z (open) 6.8 A 5A

 2015 Microchip Technology Inc. DS20005478A-page 21

MIC45404

5.5 Permissible MIC45404 Settings

Combinations

The MIC45404 allowable settings are constrained by

the values in Tab le 5-4 .

5.6 Output Capacitor Selection

Two main requirements determine the size and

characteristics of the output capacitor, CO:

• Steady-state ripple

• Maximum voltage deviation during load transient

For steady-state ripple calculation, both the ESR and

the capacitive ripple contribute to the total ripple ampli-

tude. The MIC45404 utilizes a low loss inductor, whose

nominal value is 1.2 µH. From the switching frequency,

input voltage, output voltage setting and load current,

the peak-to-peak inductor current ripple and the peak

inductor current can be calculated as:

EQUATION 5-4:

EQUATION 5-5:

The capacitive ripple, Vr,C, and the ESR ripple,

Vr,ESR, are given by:

EQUATION 5-6:

EQUATION 5-7:

The total peak-to-peak output ripple is then

conservatively estimated as:

EQUATION 5-8:

The output capacitor value and ESR should be chosen

such that VR is within specifications. Capacitor toler-

ance should be considered for worst-case calculations.

In case of ceramic output capacitors, factor into

account the decrease of effective capacitance versus

applied DC bias.

The worst-case load transient for output capacitor cal-

culation is an instantaneous 100% to 0% load release

when the inductor current is at its peak value. In this

case, all the energy stored in the inductor is absorbed

by the output capacitor, while the converter stops

switching and keeps the low-side FET on.

The peak output voltage overshoot (VO) happens

when the inductor current has decayed to zero. This

can be calculated with Equation 5-9:

EQUATION 5-9:

Equation 5-10 calculates the minimum output

capacitance value (CO(MIN)) needed to limit the output

overshoot below VO.

EQUATION 5-10:

The result from the minimum output capacitance value

for load transient is the most stringent requirement

found for capacitor value in most applications. Low

Equivalent Series Resistance (ESR) ceramic output

capacitors, with X5R or X7R temperature ratings, are

recommended.

For low output voltage applications with demanding

load transient requirements, using a combination of

polarized and ceramic output capacitors may be the

most convenient option for smallest solution size.

TABLE 5-4: PERMISSIBLE MIC45404

SETTINGS COMBINATIONS

Output Voltage Frequency

3.3V 790 kHz

2.5V (2.49V)

1.8V 565 kHz

1.5V

1.2V 400 kHz

1.0V

0.9V

0.8V

0.7V



IL_PP VO

1VO

VIN

--------–

fSL



------------------









IL,PEAK IO



IL_PP

-----------------+=



VR,C



IL_PP



SCO



---------------------------=



VR,ESR ESR



IL_PP





VR,C



VR,ESR

+



VOV2

------- I L,PEAK



–=

CO MIN



L,PEAK



VOVO

+

2V2

–

------------------------------------------------=

MIC45404

DS20005478A-page 22  2015 Microchip Technology Inc.

5.7 Input Capacitor Selection

Two main requirements determine the size and

characteristics of the input capacitor:

• Steady-State Ripple

• RMS Current

The Buck Converter input current is a pulse train with

very fast rising and falling times, so low-ESR ceramic

capacitors are recommended for input filtering because

of their good high-frequency characteristics.

By assuming an ideal input filter (which can be assimi-

lated to a DC input current feeding the filtered buck

power stage) and by neglecting the contribution of the

input capacitor ESR to the input ripple (which is typically

possible for ceramic input capacitors), the minimum

capacitance value, CIN(MIN), needed for a given input

peak-to-peak ripple voltage, Vr, IN, can be estimated as

shown in Equation 5-11:

EQUATION 5-11:

The RMS current, IIN,RMS, of the input capacitor is

estimated as in Equation 5-12:

EQUATION 5-12:

Note that, for a given output current, IO, worst-case

values are obtained at D = 0.5.

Multiple input capacitors can be used to reduce input

ripple amplitude and/or individual capacitor RMS

current.

5.8 Compensation Design

As a simple first-order approximation, the Valley Current

mode controlled buck power stage can be modeled as a

voltage controlled current source, feeding the output

capacitor and load. The inductor current state variable is

removed and the power stage transfer function from

COMP to the inductor current is modeled as a transcon-

ductance (GmPS). The simplified model of the control

loop is shown in Figure 5-3. The power stage trans-

conductance, GmPS, shows some dependence on

current levels and it is also somewhat affected by

process variations, therefore, some design margin is

recommended against the typical value, GmPS = 12.5A/V

(see Section 1.0 “Electrical Characteristics”).

FIGURE 5-3: Simplified Small Signal

Model of the Voltage Regulation Loop.

This simplified approach disregards all issues related

to the inner current loop, like its stability and bandwidth.

This approximation is good enough for most operating

scenarios, where the voltage loop bandwidth is not

pushed to aggressively high frequencies.

Based on the model shown in Figure 5-3, the

control-to-output transfer function is:

EQUATION 5-13:

The MIC45404 module uses a transconductance

(GmEA = 1.4 mA/V) error amplifier. Frequency compen-

sation is implemented with a Type-II network (RC1, CC1

and CC2) connected from the COMP to AGND. The

compensator transfer function consists of an integrator

for zero DC voltage regulation error, a zero to boost the

phase margin of the overall loop gain around the

crossover frequency and an additional pole that can

be used to cancel the output capacitor ESR zero, or to

further attenuate switching frequency ripple. In both

cases, the additional pole makes the regulation loop

less susceptible to switching frequency noise. The

additional pole is created by capacitor CC2 (internally

provided, CC2 value is 47 pF). Equation 5-14 details the

compensator transfer function, HC(S) (from OUTSNS to

COMP).

CIN MIN

IOD1D–





Vr,IN f



----------------------------------------=

Where:

D is the duty cycle at the given operating point.

IIN,RMS IOD1D–



GmPS

Gm Error

Amplifier

OUTSNS

COMP

REFDAC

VO Range CC2

CC1

RC1

CoRL

ESR

VIN

GmEA

GCO S

VOS

VCS

------------- GmPS RL

2fZ



-----------------+





2fP



-----------------+





--------------------------------==

Where fZ and fP = the frequencies associated with

the output capacitor ESR zero and with the load

pole, respectively:

fZ1

2COESR

-------------------------------------=

fP1

2COESR RL

+

-------------------------------------------------------=

 2015 Microchip Technology Inc. DS20005478A-page 23

MIC45404

EQUATION 5-14:

The overall voltage loop gain, TV(S), is the product of

the control-to-output and the compensator transfer

functions:

EQUATION 5-15:

The value of the attenuation ratio, R1/(R1 + R2),

depends on the output voltage selection and can be

retrieved as illustrated in Tab l e 5 -5:

The compensation design process is as follows:

1. Set the TV(s) loop gain crossover frequency, fXO,

in the range of fS/20 to fS/10. Lower values of

fXO allow a more predictable and robust phase

margin. Higher values of fXO would involve addi-

tional considerations about the current loop

bandwidth in order to achieve a robust phase

margin. Taking a more conservative approach is

highly recommended.

EQUATION 5-16:

2. Select RC1 to achieve the target crossover

frequency, fXO, of the overall voltage loop. This

typically happens where the power stage

transfer function, GCO(S), is rolling off at

-20 dB/decade. The compensator transfer func-

tion, HC(S), is in the so-called midband gain

region, where CC1 can be considered a DC

blocking short circuit, while CC2 can still be

considered as an open circuit, as calculated in

Equation 5-17:

EQUATION 5-17:

3. Select capacitor CC1 to place the compensator

zero at the load pole. The load pole moves

around with load variations, so to calculate the

load pole use as a load resistance RL, the value

determined by the nominal output current, IO, of

the application, as shown in Equation 5-18 and

Equation 5-19:

EQUATION 5-18:

EQUATION 5-19:

4. Knowing that an internal CC2 capacitor of 47 pF

is provided already, find out if any additional

capacitance is needed to augment the overall

value of the capacitor, CC2.

The CC2 (total value) is intended for placing the com-

pensator pole at the frequency of the output capacitor

ESR zero and/or achieve additional switching

ripple/noise attenuation.

If the output capacitor is a polarized one, its ESR zero

will typically occur at low enough frequencies to cause

the loop gain to flatten out and not roll off at a

-20 dB/decade slope, around or just after the crossover

frequency, fXO. This causes undesirable scarce

compensation design robustness and switching noise

susceptibility. The compensator pole is then used to

cancel the output capacitor ESR zero and achieve a

well-behaved roll-off of the loop gain above the

crossover frequency.

If the output capacitors are only ceramic, then the ESR

zeros frequencies could be very high. In many cases,

the frequencies could even be above the switching

frequency itself. Loop gain roll-off at -20 dB/decade is

ensured well beyond the crossover frequency, but even

in this case, it is good practice to still make use of the

compensator pole to further attenuate switching noise,

while conserving phase margin at the crossover

frequency.

TABLE 5-5: INTERNAL FEEDBACK

DIVIDER ATTENUATION

VALUES

VO Range R1/(R1 + R2) A

(A=1+R2/R1)

0.7V-1.2V 1 1

1.5V-1.8V 0.5 2

2.5V(2.49V)-3.3V 0.333 3

HCS R1

R1 R2+

---------------------Gm

EA 1

C1 CC2

+



--------------------------------------------



–=

1SR

C1 CC1



+

1SR

C1 CC1 CC2



CC1 CC2

---------------------------







--------------------------------------------------------------------

TVS GCO S HCS



------f

XO fS

------



RC1 R1 R2+

---------------------









fXO



GmEA GmPS



------------------------------------



RLVO

-------=

CC1COESR RL

+

RC1

------------------------------------------=

MIC45404

DS20005478A-page 24  2015 Microchip Technology Inc.

For example, setting the compensator pole at 5 fXO will

limit its associated phase loss at the crossover

frequency to about 11°. Placement at even higher

frequencies, N × fXO (N > 5), will reduce phase loss

even further at the expense of less noise/ripple attenu-

ation at the switching frequency. Some attenuation of

the switching frequency noise/ripple is achieved as

long as N × fXO <f

For the polarized output capacitor, compensator pole

placement at the ESR zero frequency is achieved, as

shown in Equation 5-20:

EQUATION 5-20:

For the ceramic output capacitor, compensator pole

placement at N × fXO (N 5, N × fXO < fS) is achieved,

as detailed in Equation 5-21:

EQUATION 5-21:

The MIC45404 already provides an internal CC2 capac-

itor of 47 pF. Therefore, the external capacitance,

CC2_EXT

, that should be added is given by

Equation 5-22:

EQUATION 5-22:

If the result, CC2 – 47 pF, yields to zero or to a negative

number, no additional external capacitance is needed

for CC2.

5.9 Output Voltage Soft Start Rate

The MIC45404 features an internal analog soft start,

such that the output voltage can be smoothly increased

to the target regulation voltage. The soft start rate given

in Section 1.0 “Electrical Characteristics” is referred

to the error amplifier reference, and therefore, the

effective soft start rate value, seen at the output of the

module, has to be scaled according to the internal feed-

back divider attenuation values listed in Table 5- 5 . To

calculate the effective output voltage soft start slew

rate, SS_SROUT

, based on the particular output voltage

setting and the reference soft start slew rate, SS_SR,

use the following formula:

EQUATION 5-23:

For the value of A, see the right column of Table 5- 5.

CC2 1

RC1

COESR



------------------------ 1

CC1

----------–

-----------------------------------------=

CC21



RC1



fXO 1

CC1

----------–



----------------------------------------------------------------=

CC2_EXT max CC2 47 pF, 0 pF–=

SS_SROUT A SS_SR



Where:

A = Amplification

 2015 Microchip Technology Inc. DS20005478A-page 25

MIC45404

6.0 PACKAGING INFORMATION

MIC45404

DS20005478A-page 26  2015 Microchip Technology Inc.

 2015 Microchip Technology Inc. DS20005478A-page 27

MIC45404

APPENDIX A: RE VISION HISTORY

Revision A (December 2015)

• Original release of this document.

MIC45404

DS20005478A-page 28  2015 Microchip Technology Inc.

NOTES:

 2015 Microchip Technology Inc. DS20005478A-page 29

MIC45404

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

Device: MIC45404: Ultra-low profile, synchronous step-down

regulator module

Lead Finish: Y = Pb-Free with Industrial Temperature Grade

Package Code MP = Module Package, thickness ≥ 2.0 mm

Tape and Reel

Option: TR = Tape and Reel(1)

Examples:

a) MIC45404YMP-TR: Pb-Free, 54 Lead

6 x 10 x 2 mm QFN Package,

Tape and Reel.

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identi-

fier is used for ordering purposes and is not

printed on the device package. Check with

your Microchip Sales Office for package

availability with the Tape and Reel option.

-XX(1)

Tape an d Reel

Option

XXX

Lead Finis h Package Code

MIC45404

DS20005478A-page 30  2015 Microchip Technology Inc.

NOTES:

 2015 Microchip Technology Inc. DS20005478A-page 31

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ISBN: 978-1-5224-0125-4

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intended manner and under normal conditions.

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• Microchip is willing to work with the customer who is concerned about the integrity of their code.

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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

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