ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to hel p you e val uate this product. A MD reserves the right to change or discontin ue work on this proposed
product without notice.
Publicati on# 22140 Rev: AAmendment/0
Issue Date: Apr il 1998
Am29LV010B
1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— Full v olt age r ange: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■Manufactured on 0.35 µm process technology
■High performan c e
— Full vo ltage range: ac cess times as f ast as 55 ns
— Regulated voltage range: access times as fast
as 45 ns
■Ultra low po wer consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■Flexible sector arch itecture
— Eight 16 Kbyte
— Supports full chip erase
— Sector Protection features:
Hardware method of lockin g a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
■Unlock Bypas s Mo de Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■Embe dded Algorit hms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
■Minimum 1,000,000 write cycle guarantee per
sector
■Package option
— 32-pin TSOP
— 32-pin PLCC
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■Erase Suspend/Erase Resume
— Supports reading data from or programming
data to a sector that is not being erased
Am29LV010B 2
ADVANCE INFORMATION
GENERAL DESCRIPTION
The Am29LV010B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV010B has a uniform sector architecture.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7–
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in standard EPROM
programmers.
The standard Am29LV010B offers access times of 45,
55, 70, and 120 ns (90 and 100 ns parts are also a v ail-
able), allowing high speed microprocessors to operate
without wait states. To eliminate bus contention, the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) co ntrols.
The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM dev ices.
Dev ice programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprogr ams the arra y (i f it is not already prog rammed)
bef ore ex ecuting the er ase operation. During er ase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry se ctors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True backgro und eras e can thus be achie ved.
The de vice off ers tw o power-saving features . When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also plac e the de v ice into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases a ll bi ts w ithi n a
sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
3 Am29LV010B
ADVANCE INFORMATION
PRODUCT SELECTOR GUIDE
Note: S ee “AC Character ist ics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV010B
Speed Options Regulated Voltage Range: VCC =3.0–3.6 V -45R
Full Voltage Range: VCC = 2.7–3.6 V -55 -70 -120
Max access time, ns (tACC)45 55 70 120
Max CE# access time, ns (tCE)45 55 70 120
Max OE# access time, ns (tOE)30 30 35 50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
CE#
OE#
STB
STB
DQ0
–
DQ7
Sector Swi tche s
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A16
22140A-1
Am29LV010B 4
ADVANCE INFORMATION
CONNECTION DIAGRAMS
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A11
A4
A9
A8
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
A6
A5
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
OE#
A3
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
32-Pin Reverse TSOP
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
NC
WE#
VCC
NC
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32-Pin Standard TSOP
22140A-2
DQ6
NC
DQ5
DQ4
DQ3
13130234
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
VCC
WE#
NC
DQ1
DQ2
VSS
PLCC
5 Am29LV010B
ADVANCE INFORMATION
PIN CONFIGURATION
A0–A16 = 17 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE# = Chip enable
OE# = Output enable
WE# = Write enable
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and vo ltage s upply toler anc es)
VSS = De vice ground
NC = Pin not connected internally
LOGIC SYMBOL
22140A-3
17 8
DQ0–DQ7
A0–A16
CE#
OE#
WE#
Am29LV010B 6
ADVANCE INFORMATION
ORDERING INFORMATION
Standard Pro ducts
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm a vailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29LV010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
CE-45RAm29LV010B T
OPTION AL PROCE SSI NG
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPER ATURE RANG E
C=Commercial (0°C to +70°C)
I = Industrial (–4 0°C to +85 °C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OP TIO N
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
Valid Combinations
Am29LV 01 0B -45 R EC, FC, JC
Am29LV010B-55 EC, EI, EE,
FC, FI, FE,
JC, JI, JE
Am29LV010B-70
Am29LV010B-120
7 Am29LV010B
ADVANCE INFORMATION
REVISION SUMMARY
Revision A
Split the Am29LV001B/Am29LV010B data sheet into
separate documents. The Am29LV001B data sheet
retains publication number 21557B and later; the
Am29LV010B data sheet has been reas signed pub lica-
tion number 22140.
Valid Combinations
Changes since publication number 21557A was
released: deleted the “R” designation from the 55 ns
option. Corrected the part numbers.
Trademarks
Copyright © 1998 Advanced M icro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademar ks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
