MC74HC165ADTR2G - ON Semiconductor

July, 2012 − Rev. 7

1Publication Order Number:

MC74HC165A/D

MC74HC165A

8-Bit Serial or

Parallel-Input/

Serial-Output Shift Register

High−Performance Silicon−Gate CMOS

The MC74HC165A is identical in pinout to the LS165. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device is an 8−bit shift register with complementary outputs

from the last stage. Data may be loaded into the register either in

parallel or in serial form. When the Serial Shift/Parallel Load input is

low, the data is loaded asynchronously in parallel. When the Serial

Shift/Parallel Load input is high, the data is loaded serially on the

rising edge of either Clock or Clock Inhibit (see the Function Table).

The 2−input NOR clock may be used either by combining two

independent clock sources or by designating one of the clock inputs to

act as a clock inhibit.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

•Chip Complexity: 286 FETs or 71.5 Equivalent Gates

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

1

16 PDIP−16

N SUFFIX

CASE 648

1

16

1

16

1

16

MC74HC165AN

AWLYYWWG

1

16

HC165AG

AWLYWW

HC

165A

ALYWG

G

1

16

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HC165A

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2

PIN 16 = VCC

PIN 8 = GND

11

12

13

14

3

4

5

6

10

A

B

C

D

E

F

G

H

SA

PARALLEL

DATA

INPUTS

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

1

2

15

CLOCK

CLOCK INHIBIT

9

7

QH

SERIAL

DATA

OUTPUTS

Figure 1. Pin Assignment

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

D

CLOCK INHIBIT

VCC

QH

SA

A

F

E

CLOCK

SERIAL SHIFT/

PARALLEL LOAD

GND

QH

H

G

Figure 2. Logic Diagram

FUNCTION TABLE

Inputs Internal Stages Output

Operation

Serial Shift/

Parallel Load Clock

Clock

Inhibit SAA − H QAQBQH

L X X X a … h a b h Asynchronous Parallel Load

H

L

H

X

L

H

QAn

QGn

QGn Serial Shift via Clock

H

L

H

X

L

H

QAn

QGn

QGn Serial Shift via Clock Inhibit

H

X

H

X

XNo Change Inhibited Clock

H L L X X No Change No Clock

X = don’t care QAn − QGn = Data shifted from the preceding stage

ORDERING INFORMATION

Device Package Shipping†

MC74HC165ANG PDIP−16

(Pb−Free)

500 Units / Rail

MC74HC165ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC165ADR2G SOIC−16

(Pb−Free)

2500 Units / Reel

MC74HC165ADTR2G TSSOP−16

(Pb−Free)

2500 Units / Reel

NLV74HC165ADR2G* SOIC−16

(Pb−Free)

2500 Units / Reel

NLV74HC165ADTR2G* TSSOP−16

(Pb−Free)

2500 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable.

MC74HC165A

http://onsemi.com

3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎÎÎ

260

ÎÎÎ

_C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to

GND)

ÎÎÎ

0

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

0

ÎÎÎ

1000

600

500

400

ÎÎÎ

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎÎ

1.9

4.4

5.9

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎ

3.0

4.5

6.0

ÎÎÎÎÎ

2.48

3.98

5.48

ÎÎÎÎ

2.34

3.84

5.34

ÎÎÎÎÎ

2.20

3.70

5.20

ÎÎ

V

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC165A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎ

Unit

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

ÎÎÎ

3.0

4.5

6.0

ÎÎÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎÎ

0.40

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎ

Maximum Input Leakage

Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎ

6.0

ÎÎÎÎÎ

4

ÎÎÎÎ

40

ÎÎÎÎÎ

160

ÎÎ

mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

6

18

30

35

ÎÎÎÎ

4.8

17

24

28

ÎÎÎÎÎ

4

15

20

24

ÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH

(Figures 1 and 8)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

150

52

30

26

ÎÎÎÎ

190

63

38

33

ÎÎÎÎÎ

225

65

45

38

ÎÎ

ns

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH

(Figures 2 and 8)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

175

58

35

30

ÎÎÎÎ

220

70

44

37

ÎÎÎÎÎ

265

72

53

45

ÎÎ

ns

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input H to QH or QH

(Figures 3 and 8)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

150

52

30

26

ÎÎÎÎ

190

63

38

33

ÎÎÎÎÎ

225

65

45

38

ÎÎ

ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

27

15

13

ÎÎÎÎ

95

32

19

16

ÎÎÎÎÎ

110

36

22

19

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

−

ÎÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎÎ

10

ÎÎ

pF

CPD Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

pF

40

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

MC74HC165A

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5

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load

(Figure 4)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

30

15

13

ÎÎÎÎ

95

40

19

16

ÎÎÎÎ

110

55

22

19

ÎÎ

ns

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)

(Figure 5)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

30

15

13

ÎÎÎÎ

95

40

19

16

ÎÎÎÎ

110

55

22

19

ÎÎ

ns

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)

(Figure 6)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

30

15

13

ÎÎÎÎ

95

40

19

16

ÎÎÎÎ

110

55

22

19

ÎÎ

ns

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Clock to Clock Inhibit

(Figure 7)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

30

15

13

ÎÎÎÎ

95

40

19

16

ÎÎÎÎ

110

55

22

19

ÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs

(Figure 4)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA

(Figure 5)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load

(Figure 6)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎÎÎ

5

ÎÎ

ns

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Clock to Clock Inhibit

(Figure 7)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

75

30

15

13

ÎÎÎÎ

95

40

19

16

ÎÎÎÎ

110

55

22

19

ÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock (or Clock Inhibit)

(Figure 1)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

70

27

15

13

ÎÎÎÎ

90

32

19

16

ÎÎÎÎ

100

36

22

19

ÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse width, Serial Shift/Parallel Load

(Figure 2)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

70

27

15

13

ÎÎÎÎ

90

32

19

16

ÎÎÎÎ

100

36

22

19

ÎÎ

ns

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

1000

800

500

400

ÎÎÎÎ

1000

800

500

400

ÎÎÎÎ

1000

800

500

400

ÎÎ

ns

MC74HC165A

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6

PIN DESCRIPTIONS

INPUTS

A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

Parallel Data inputs. Data on these inputs are

asynchronously entered in parallel into the internal

flip−flops when the Serial Shift/Parallel Load input is low.

SA (Pin 10)

Serial Data input. When the Serial Shift/Parallel Load

input is high, data on this pin is serially entered into the first

stage of the shift register with the rising edge of the Clock.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 1)

Data−entry control input. When a high level is applied to

this pin, data at the Serial Data input (SA) are shifted into the

register with the rising edge of the Clock. When a low level

is applied to this pin, data at the Parallel Data inputs are

asynchronously loaded into each of the eight internal stages.

Clock, Clock Inhibit (Pins 2, 15)

Clock inputs. These two clock inputs function identically.

Either may be used as an active−high clock inhibit.

However, to avoid double clocking, the inhibit input should

go high only while the clock input is high.

The shift register is completely static, allowing Clock

rates down to DC in a continuous or intermittent mode.

OUTPUTS

QH, QH (Pins 9, 7)

Complementary Shift Register outputs. These pins are the

noninverted and inverted outputs of the eighth stage of the

shift register.

MC74HC165A

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7

SWITCHING WAVEFORMS

trtf

VCC

GND

90%

50%

10%

tPLH tPHL

CLOCK

OR CLOCK INHIBIT

90%

50%

10%

tTLH tTHL

QH OR QH

SERIAL SHIFT/

PARALLEL LOAD

QH OR QH

50%

tPLH

50%

VCC

GND

tPHL

50%

trtf

INPUT H 90%

50%

10%

90%

50%

10%

VCC

GND

tPHL

tTHL

tTLH

tPLH

QH OR QH

50%

VCC

GND

th

VCC

GND

ASYNCHRONOUS PARALLEL

LOAD

(LEVEL SENSITIVE)

SERIAL SHIFT/

PARALLEL LOAD

INPUTS A-H

INPUT SA50%

50%

CLOCK

OR CLOCK INHIBIT

VCC

GND

VCC

GND

SERIAL SHIFT/

PARALLEL LOAD

CLOCK

OR CLOCK INHIBIT

50%

tsu

VCC

GND

VCC

GND

CLOCK 2 INHIBITED

CLOCK INHIBIT

CLOCK

50%

tsu trec

VCC

GND

VCC

GND *Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

tw

1/fmax

tw

VALID

tsu

VALID

tsu th

th

Figure 3. Serial−Shirt Mode Figure 4. Parallel−Load Mode

Figure 5. Parallel−Load Mode Figure 6. Parallel−Load Mode

Figure 7. Serial−Shift Mode Figure 8. Serial−Shift Mode

Figure 9. Serial−Shift, Clock−Inhibit Mode Figure 10. Test Circuit

MC74HC165A

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8

ABC FGH

11 12 13 4 5 6

9QH

7QH

SERIAL SHIFT/

PARALLEL LOAD 1

SERIAL DATA

INPUT SA

10

CLOCK 2

CLOCK

INHIBIT

15

EXPANDED LOGIC DIAGRAM

CLOCK

CLOCK INHIBIT

SA

SERIAL SHIFT/

PARALLEL LOAD

A

B

C

D

E

F

G

H

QH

H

L

H

L

H

L

H

HH

LL

L

H

L

H

L

H

L

PARALLEL LOAD

PARALLEL

DATA

INPUTS

TIMING DIAGRAM

DQ

A

CC

DQ

B

CC

DQ

C

CC

DQ

F

CC

DQ

G

CC

DQ

H

CC

CLOCK

INHIBIT

MODE

SERIAL-SHIFT MODE

MC74HC165A

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9

PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC74HC165A

http://onsemi.com

10

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

MC74HC165A

http://onsemi.com

11

PACKAGE DIMENSIONS

TSSOP−16

CASE 948F

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74HC165A

http://onsemi.com

12

PACKAGE DIMENSIONS

SOEIAJ−16

CASE 966

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

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