MC74HC165A 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 N SUFFIX CASE 648 16 1 1 16 SOIC-16 D SUFFIX CASE 751B 16 1 * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: 286 FETs or 71.5 Equivalent Gates These Devices are Pb-Free, Halogen Free and are RoHS Compliant NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable HC165AG AWLYWW 1 Features * * * * * * MC74HC165AN AWLYYWWG 16 HC 165A ALYWG G TSSOP-16 DT SUFFIX CASE 948F 16 1 1 A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. (c) Semiconductor Components Industries, LLC, 2012 July, 2012 - Rev. 7 1 Publication Order Number: MC74HC165A/D MC74HC165A A B SERIAL SHIFT/ PARALLEL LOAD CLOCK 1 2 15 CLOCK INHIBIT E 3 14 D F 4 13 C G 5 12 B H 6 11 A QH 7 10 SA GND 8 9 QH 16 VCC PARALLEL DATA INPUTS 11 12 13 9 D 14 E 3 7 C QH QH SERIAL DATA OUTPUTS F 4 G 5 H 6 SERIAL SA 10 DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 Figure 1. Pin Assignment CLOCK INHIBIT PIN 16 = VCC PIN 8 = GND 15 Figure 2. Logic Diagram FUNCTION TABLE Inputs Serial Shift/ Parallel Load L Internal Stages Output Clock Clock Inhibit SA A-H QA QB QH X X X a...h a b h L L L H X X L H QAn QAn QGn QGn Serial Shift via Clock L H X X L H QAn QAn QGn QGn Serial Shift via Clock Inhibit X X X X No Change Inhibited Clock X X No Change No Clock H H H H L L H H X H H X L L H X = don't care Operation Asynchronous Parallel Load QAn - QGn = Data shifted from the preceding stage ORDERING INFORMATION Package Shipping MC74HC165ANG PDIP-16 (Pb-Free) 500 Units / Rail MC74HC165ADG SOIC-16 (Pb-Free) 48 Units / Rail MC74HC165ADR2G SOIC-16 (Pb-Free) 2500 Units / Reel MC74HC165ADTR2G TSSOP-16 (Pb-Free) 2500 Units / Reel NLV74HC165ADR2G* SOIC-16 (Pb-Free) 2500 Units / Reel NLV74HC165ADTR2G* TSSOP-16 (Pb-Free) 2500 Units / Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC74HC165A IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) Plastic DIP SOIC Package TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII III IIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 600 500 400 ns DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V Guaranteed Limit - 55 to 25_C v 85_C v 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 0.5 0.9 1.35 1.80 V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 V Symbol Parameter Test Conditions Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA http://onsemi.com 3 MC74HC165A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIII IIIIIIII IIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIII II IIIIIIIII III IIIII IIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIII IIIIIIII IIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIII IIIIIIIII IIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VOL Parameter Test Conditions Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA Guaranteed Limit VCC V - 55 to 25_C v 85_C v 125_C Unit 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V - 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) 2.0 3.0 4.5 6.0 6 18 30 35 4.8 17 24 28 4 15 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH (Figures 2 and 8) 2.0 3.0 4.5 6.0 175 58 35 30 220 70 44 37 265 72 53 45 ns tPLH, tPHL Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) 2.0 3.0 4.5 6.0 150 52 30 26 190 63 38 33 225 65 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 8) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns - 10 10 10 pF Cin Maximum Input Capacitance Typical @ 25C, VCC = 5.0 V CPD 40 Power Dissipation Capacitance (Per Package)* * Used to determine the no-load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . http://onsemi.com 4 pF MC74HC165A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIII IIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIII III IIIII IIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII TIMING REQUIREMENTS (Input tr = tf = 6 ns) VCC V Guaranteed Limit - 55 to 25_C v 85_C v 125_C Unit tsu Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tsu Minimum Setup Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns th Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns th Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) 2.0 3.0 4.5 6.0 5 5 5 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Clock to Clock Inhibit (Figure 7) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tw Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns tw Minimum Pulse width, Serial Shift/Parallel Load (Figure 2) 2.0 3.0 4.5 6.0 70 27 15 13 90 32 19 16 100 36 22 19 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Symbol tr, tf Parameter http://onsemi.com 5 MC74HC165A PIN DESCRIPTIONS INPUTS is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip-flops when the Serial Shift/Parallel Load input is low. Clock, Clock Inhibit (Pins 2, 15) Clock inputs. These two clock inputs function identically. Either may be used as an active-high clock inhibit. However, to avoid double clocking, the inhibit input should go high only while the clock input is high. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. SA (Pin 10) Serial Data input. When the Serial Shift/Parallel Load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the Clock. OUTPUTS CONTROL INPUTS QH, QH (Pins 9, 7) Serial Shift/Parallel Load (Pin 1) Complementary Shift Register outputs. These pins are the noninverted and inverted outputs of the eighth stage of the shift register. Data-entry control input. When a high level is applied to this pin, data at the Serial Data input (SA) are shifted into the register with the rising edge of the Clock. When a low level http://onsemi.com 6 MC74HC165A SWITCHING WAVEFORMS tr CLOCK OR CLOCK INHIBIT tf VCC 90% 50% 10% tw GND SERIAL SHIFT/ PARALLEL LOAD tw 1/fmax 90% 50% 10% QH OR QH GND QH OR QH tTLH 50% tPLH tPHL tPLH VCC 50% tPHL 50% tTHL Figure 3. Serial-Shirt Mode Figure 4. Parallel-Load Mode VALID tr VCC tf 90% 50% 10% INPUT H INPUTS A-H VCC 50% GND GND tsu tPHL tPLH 90% 50% 10% QH OR QH th VCC SERIAL SHIFT/ PARALLEL LOAD tTLH GND tTHL ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE) Figure 5. Parallel-Load Mode Figure 6. Parallel-Load Mode VALID SERIAL SHIFT/ PARALLEL LOAD VCC INPUT SA 50% VCC 50% GND GND tsu tsu th VCC CLOCK OR CLOCK INHIBIT VCC CLOCK OR CLOCK INHIBIT 50% th 50% GND GND Figure 7. Serial-Shift Mode Figure 8. Serial-Shift Mode TEST POINT CLOCK 2 INHIBITED CLOCK INHIBIT OUTPUT VCC DEVICE UNDER TEST 50% GND tsu CLOCK CL* trec VCC 50% *Includes all probe and jig capacitance GND Figure 9. Serial-Shift, Clock-Inhibit Mode Figure 10. Test Circuit http://onsemi.com 7 MC74HC165A EXPANDED LOGIC DIAGRAM A B 11 C 12 F 13 G 4 H 5 6 SERIAL SHIFT/ 1 PARALLEL LOAD 9 Q H SERIAL DATA 10 INPUT SA D QA D QB D QC D QF D QG D QH C C C C C C C C C C C C CLOCK 2 CLOCK 15 INHIBIT TIMING DIAGRAM CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A H B L C H D L E H F L G H H H PARALLEL DATA INPUTS QH QH H H L H L H L H L L H L H L H L CLOCK INHIBIT MODE SERIAL-SHIFT MODE PARALLEL LOAD http://onsemi.com 8 7 Q H MC74HC165A PACKAGE DIMENSIONS PDIP-16 CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 9 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC74HC165A PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 10 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HC165A PACKAGE DIMENSIONS TSSOP-16 CASE 948F ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S K1 2X L/2 16 9 B -U- L SECTION N-N J PIN 1 IDENT. N 8 1 EEE CCC CCC EEE J1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 11 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC165A PACKAGE DIMENSIONS SOEIAJ-16 CASE 966 ISSUE A 16 LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC74HC165AD