© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 5
1Publication Order Number:
NCP1034/D
NCP1034
100V Synchronous PWM
Buck Controller
Description
The NCP1034 is a high voltage PWM controller designed for high
performance synchronous Buck DC/DC applications with input
voltages up to 100 V. The NCP1034 drives a pair of external
N−MOSFETs. The switching frequency is programmable from
25 kHz up to 500 kHz allowing the flexibility to tune for efficiency
and size. A synchronization feature allows the switching frequency to
be set by an external source or output a synchronization signal to
multiple NCP1034 controllers. The output voltage can be precisely
regulated using the internally trimmed 1.25 V reference voltage for
low voltage applications. Protection features include user
programmable undervoltage lockout and hiccup current limit.
Features
•High Voltage Operating up to 100 V
•Programmable Switching Frequency up to 500 kHz
•2 A Output Drive Capability
•Precision Reference Voltage (1.25 V)
•Programmable Soft−Start with Prebiased Load Capability
•Programmable Overcurrent Protection
•Programmable Undervoltage Protection
•Hiccup Current Limit Using MOSFET RDS(on) Sensing
•External Frequency Synchronization
•16 Pin SOIC Package
•This is a Pb−Free Device
Applications
•48 V Non−Isolated DC−DC Converter
•Embedded Telecom Systems
•Networking and Computing Voltage Regulator
•Distributed Point of Load Power Architectures
•General High Voltage DC−DC Converters
Figure 1. Typical Application Circuit
12
5
15
4
16
1
14
10
11
13
7
6
2
3
R7
11k
R6
20k
C5
220n
R5
3k9
VCC
SYNC
RT
UVLO
OCSET
GND
HDRV
VS
OCIN
LDRV
PGND
FB
COMP
SS/SD
C2
100n
C3
100n
D1
1N4148 C4
100n
R4
110k
VCC: 12 V
IC1
NCP1034
89
DRVVCC VB
R3
4k7 C7
330p
C6
12n
R8
10k
VIN: 48 V
C1A
2u2
C9
47
C9B
47
Q1
NTD3055
Q2
NTD24N06
L1
13
R2
5k6
R1
16k9
R9
1k2
VOUT
5 V @ 5 A, 200 kHz
C8
1n8
R10
10k
GND GND GND GND GND
GND
GND GND
GND
GND
C1B
2u2
C9C
47
1
2
3
4
5
6
7
8
16
12
11
10
9
(Top View)
SYNC
OCset
FB
Comp
SS/SD
PGND
LDRV
DRVCC
UVLO
VCC
VS
VB
HDRV
13 OCIN
15
14
RT
GND
SOIC−16
D SUFFIX
CASE 751B NCP1034D
AWLYWWG
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
MARKING
DIAGRAM
PIN CONNECTIONS
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See detailed ordering and shipping information in the package
dimensions section on page 22 of this data sheet.
ORDERING INFORMATION
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Figure 2. Internal Block Diagram
Bias
Generator
POR
1.25V = Vref
VCC
GND
5V = VBIAS
Oscillator
SYNC
Rt
Ct
Rt
Vcc UVLO
S
RReset Dom
Q
High
Voltage
Level
Shift
Circuit
UV
Detect
S
R
UV
Q
Vb
HDrv
Vs
DrvVCC
LDrv
PGND
Clk
D
POR
0.3V0.3V
SS/SD
Comp
Fb
1.25V
25k
POR
VBIAS
20uA
1uA
64uA Max
OCP
VBIAS
OCin
Active
Clamp
VBIAS
Error Amp
Error
Comparator UV
Detect
Delay
LS
AC ON
OCset AC ON
Negative
Output
S
R
Q
OCP
OCP Reset
SS/SD
0.25V
Vref
UVLO
Vref
Iocset
0.0410x Iocset
AC ON
FAULT
FAULT
Q
PWM
FAULT
MKO
350ns
PWM
LowUVLO
Positive
Current
OCP
LowUVLO
R
OCP
0.225x Iocset
Positive Current
SS/SD
TONMIN
Limit
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PIN FUNCTION DESCRIPTION
PIN PIN NAME DESCRIPTION
1 OCset Current limit set point. A resistor from this pin to GND will set the positive and negative current limit threshold
2 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor
divider to set the output voltage and provide feedback to the error amplifier.
3 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground
to provide loop compensation.
4 SS/SD Soft−Start / Shutdown. This pin provides user programmable soft−start function. External capacitor connected
from this pin to ground sets the startup time of the output voltage. The converter can be shutdown by pulling this
pin below 0.3 V.
5 SYNC The internal oscillator can be synchronized to an external clock via this pin and other IC’s can be synchronized
via this pin to internal oscillator. If it is not used this pin should be connected via 10 k resistor to ground.
6 PGND Power Ground. This pin serves as a separate ground for the MOSFET driver and should be connected to the
system’s power ground plane.
7 LDRV Output driver for low side MOSFET.
8 DRVVCC This pin provides biasing for the internal low side driver. A minimum of 0.1 F, high frequency capacitor must be
connected from this pin to power ground.
9 VB This pin powers the high side driver and must be connected to a voltage higher than input voltage. A minimum of
0.1 F, high frequency capacitor must be connected from this pin to switch node.
10 HDRV Output driver for high side MOSFET
11 VSSwitch Node. This pin is connected to the source of the upper MOSFET and the drain of the lower MOSFET.
This pin is return path for the upper gate driver.
12 VCC This pin provides power for the internal blocks of the IC. A minimum of 0.1 F, high frequency capacitor must be
connected from this pin to ground.
13 OCIN Overcurrent sensing input. A serial resistor from this pin to drain of low MOSFET must be used to limit the
current into this pin.
14 GND Signal ground for internal reference and control circuitry.
15 RTConnecting a resistor from this pin to ground sets the oscillator frequency.
16 UVLO An external voltage divider is used to set the undervoltage threshold levels.
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Min Max Unit
FB, VUVLO, RT
, OCset −0.3 10 V
COMP, SS/SD, SYNC, OCIN −0.3 5 V
PGND NA NA V
LDRV −0.3 VCC + 0.3 V
DRVVCC, VCC −0.3 20 V
VB VSVS + 20 V
HDRV VS − 0.3 VB + 0.3 V
VS−1.0 150 V
GND NA NA V
OCin Input Current 20 mA
All voltages referenced to GND
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient RJA 130 °C/W
Operating Ambient Temperature Range TA−40 to 125 °C
Storage Temperature Range TSTG −55 to 150 °C
Junction Operating Temperature TJ−40 to 150 °C
ESD Withstand Voltage (Note 1)
Human Body Model
Machine Model
VESD 2.0
200
kV
Latchup Capability per Jedec JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Excluding pins Vb, VS and HDRV.
TYPICAL ELECTRICAL PARAMETERS
RECOMMENDED OPERATING CONDITIONS
Symbol Definition Min Max Unit
VIN Converting Voltage 100 V
VCC Supply Voltage 10 18 V
DRVCC Supply Voltage 10 18 V
VB to VSSupply Voltage 10 18 V
FSW Operating Frequency 25 500 kHz
TJJunction Temperature −40 125 °C
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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V,
DRVVCC = VB = 12 V, −40°C < TJ < 125°C)
Parameter Symbol Test Condition Min Typ Max Unit
REFERENCE VOLTAGE
Feedback Voltage VFB 1.25 V
Accuracy −40°C < TJ < 125°C−1.5 +1.5 %
FB Voltage Line Regulation LREG 10 V < VCC < 18 V (Note 3) 2.0 mV
SUPPLY CURRENT
VCC Supply Current (Stat) ICC(Static) SS = 0 V, No Switching, RT = 10 k,
ROCSET = 10 k
2.0 3.0 mA
DRVVCC Supply Current (Stat) IC(Static) SS = 0 V, No Switching 0.1 0.3 mA
VB Supply Current (Stat) IB(Static) SS = 0 V, No Switching 0.1 0.3 mA
UNDERVOLTAGE LOCKOUT
VCC−Start−Threshold VCC_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V
VCC−Stop−Threshold VCC_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V
VCC−Hysteresis Supply Ramping Up and Down 0.7 V
DRVCC−Start−Threshold DRVCC_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V
DRVCC−Stop−Threshold DRVCC_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V
DRVCC−Hysteresis Supply Ramping Up and Down 0.7 V
VB−Start−Threshold VB_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V
VB−Stop−Threshold VB_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V
VB−Hysteresis Supply Ramping Up and Down 0.7 V
Undervoltage Threshold Value UUVLO (Rising) 1.19 1.25 1.31 V
Undervoltage Threshold Value UUVLO (Falling) 1.10 1.15 1.20 V
OSCILLATOR
Frequency FSRT = 20 k
RT = 10 k
170
320
200
375
230
430
kHz
Ramp Amplitude Vramp (Note 3) 2.0 V
Min Duty Cycle Dmin FB = 2 V 0 %
Min Pulse Width Dmin(ctrl) FS = 200 kHz, (Note 3) 200 ns
Max Duty Cycle Dmax FS = 400 kHz, FB = 1.2 V 80 %
SYNC Frequency Range SYNC(FS)20% Above Free Running
Frequency
500 kHz
SYNC Pulse Duration SYNC(pulse) 200 ns
SYNC High Level SYNC(H) 2.0 V
SYNC Low Level SYNC(L) 0.8 V
SYNC Input Threshold SYNC(Thre) 1.6 V
SYNC Input Hysteresis SYNC(Hyst) 300 mV
SYNC Input Impedance SYNC(ZIN) (Note 3) 16 k
SYNC Output Impedance SYNC(OUT) (Note 3) 2.5 k
SYNC Output Pulse Width SYNC(Pulse Width) FS = 500 kHz, (Note 3) 300 ns
ERROR AMPLIFIER
Input Bias Current IFB SS = 3 V, FB = 1 V −0.1 −0.4 A
2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
3. Guaranteed by design but not tested in production.
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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V,
DRVVCC = VB = 12 V, −40°C < TJ < 125°C)
Parameter UnitMaxTypMinTest ConditionSymbol
ERROR AMPLIFIER
Source/Sink Current I(Source/Sink) 50 100 120 A
Bandwidth (Note 3) 4.0 10 MHz
DC gain (Note 3) 55 dB
Transconductance gm(Note 3) 1500 3150 4000 mho
SOFT−START/SD
Soft−Start Current ISS SS = 0 V 15 20 25 A
Shutdown Output Threshold SD0.3 0.4 V
OVERCURRENT PROTECTION
OCSET Voltage VOCSET 1.25 V
Hiccup Current IHiccup (Note 3) 1.0 A
Hiccup Duty Cycle Hiccup(duty) IHiccup/ISS, (Note 3) 5.0 %
OUTPUT DRIVERS
LO, Drive Rise Time tr(Lo) CL = 1.5 nF (See Figure 3) 17 ns
HI Drive Rise Time tr(Hi) CL = 1.5 nF (See Figure 3) 17 ns
LO Drive Fall Time tf(Lo) CL = 1.5 nF (See Figure 3) 10 ns
HI Drive Fall Time tf(Hi) CL = 1.5 nF (See Figure 3) 10 ns
Dead Band Time tdead (See Figure 3) 30 60 120 ns
LO Output High Short Circuit
Pulsed Current
tLDRVhigh VLDRV = 0 V, PW v 10 s,
TJ = 25°C (Note 3)
1.4 A
HI Output High Short Circuit
Pulsed Current
tHDRVhigh VHDRV = 0 V, PW v 10 s,
TJ = 25°C (Note 3)
2.2 A
LO Output Low Short Circuit
Pulsed Current
tLDRVhigh VLDRV = DRVVCC, PW v 10 s,
TJ = 25°C (Note 3)
1.4 A
HI Output Low Short Circuit
Pulsed Current
tHDRVhigh VHDRV = VB, PW v 10 s,
TJ = 25°C (Note 3)
2.2 A
LO Output Resistor, Source RLOH Typical Value @ 25°C, (Note 3) 7 12
LO Output Resistor, Sink RLOL Typical Value @ 25°C, (Note 3) 2 8
HI Output Resistor, Source RHIH Typical Value @ 25°C, (Note 3) 7 12
HI Output Resistor, Sink RHIL Typical Value @ 25°C, (Note 3) 2 8
2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
3. Guaranteed by design but not tested in production.
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Figure 3. Definition of Rise−Fall Time and Deadband Time
trtf
trtf
9 V
2 V
9 V
2 V
High−Side
Driver
(HDrv)
Low−Side
Driver
(LDrv)
Deadband
H to L
Deadband
L to H
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TYPICAL OPERATING CHARACTERISTICS
1.2
1.22
1.24
1.26
1.28
1.3
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 4. VFB
VB (V)
8.0
8.2
8.4
8.6
8.8
9.0
9.2
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 5. UVLOVB
UVLOVB (V)
Rising
Falling
1.1
1.15
1.2
1.25
1.3
1.35
1.4
−40 −20 0 20 40 60 80 100 120
UVLOVCC (V)
TEMPERATURE (°C)
Figure 6. UVLOVCC
Rising
Falling
7.9
8.0
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 7. UVLODRVVCC
UVLODRVVCC (V)
Rising
Falling
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
9.0
9.1
9.2
−40 −20 0 20 40 60 80 100 120
UVLO (V)
TEMPERATURE (°C)
Figure 8. UVLO
Rising
Falling
1.8
1.9
2.0
2.1
2.2
2.3
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 9. ICC (Stat)
ICC (stat) (mA)
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180
185
190
195
200
205
210
215
220
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 10. Switching Frequency @ RT = 20 kW
fSW (kHz)
70
72
74
76
78
80
82
84
86
88
90
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 11. Maximum Duty Cycle @ f = 400 kHz
Dmax (%)
170
175
180
185
190
195
200
205
210
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 12. Minimum on Time
tonmin (ns)
1500
2000
2500
3000
3500
4000
4500
−40 −20 0 20 40 60 80 100 120
gm (mho)
TEMPERATURE (°C)
Figure 13. Error Amplifier Transconductance
40
45
50
55
60
65
70
75
80
85
90
−40 −20 0 20 40 60 80 100 120
Low to High
High to Low
TEMPERATURE (°C)
Figure 14. Deadtime
t (ns)
4
5
6
7
8
9
10
11
12
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 15. Driver Pullup Resistance
R ()
DRVVCC = VB = 10 V
12 V
18 V
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1.0
1.5
2.0
2.5
3.0
3.5
4.0
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 16. Driver Pulldown Resistance
R ()
DRVVCC = VB = 10 V
12 V
18 V
−0.3
−0.29
−0.28
−0.27
−0.26
−0.25
−0.24
−0.23
−0.22
−0.21
−0.2
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 17. OCP @ R8 = 10 kW, ROCIN = 10 kW
VDSLOWFET (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
−40 −20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 18. POSOCP @ R8 = 10 kW,
ROCIN = 10 kW
VDSLOWFET (V)
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Undervoltage Lock−out
There are four undervoltage lock−out circuits. Two of
them protect external high−side and low−side drivers, the
third ensures that the IC does not start until VCC is under a
set threshold. The last one can be programmed by the user.
It has a rising threshold at 1.25 V and a falling threshold at
1.15 V, and the user can define the undervoltage level by an
external resistor divider. If the voltage is not over the
threshold value, the device stops operating. The high−side
driver UVLO only stops switching the high−side MOSFET
Programmed falling and rising UVLO voltage can be
calculated by Equations 1 and 2:
VUVLO,falling +1.15 @ǒ1)R4
R5Ǔ(eq. 1)
and
VUVLO,rising +1.25 @ǒ1)R4
R5Ǔ(eq. 2)
Shutdown
The output voltage can be disabled by pulling the
SS/SD pin below 0.3 V. A small transistor can be used to pull
it down as shown in Figure 19. During this time, both
external MOSFETs are turned off. After the SS/SD pin is
released, the IC starts its operation with a soft−start
sequence.
Figure 19. Shutdown Interface
SS/SDSS/SD
Operating Frequency Selection
The operating frequency is set by an external resistor
connected from the Rt Pin to ground. The value of this
resistor can be selected from Figure 20, which shows
switching frequency versus the timing resistor value.
Figure 20. Frequency Dependence of Rt Value
0
50
100
150
200
250
300
350
400
450
500
0 50 100 150 200 25
0
Rt (k)
f (kHz)
Frequency Synchronization
The NCP1034 can be synchronized to an external clock
signal. The input synchronization signal should be a TTL
logic level. The oscillator is synchronized to the rising edge
of the synchronizing signal. When synchronization is used,
the free running frequency must be set by the timing resistor
to a frequency at least 80% of the external synchronization
frequency (Example: RT = 20 k / 200 kHz and external
TTL = 220 kHz).
The NCP1034 can also output synchronization pulses on
the SYNC pin. Pulses are generated when the internal
oscillator ramp reaches the high threshold voltage. The
frequency of these pulses is set by an external RT resistor. Up
to five NCP1034 controllers can be connected directly to the
SYNC pin, all of which are synchronized to the controller
with the highest frequency. The lowest frequency must be at
least 80% of the highest one.
The equivalent internal circuit of the Sync pin is shown in
Figure 21.
Figure 21. Equivalent Connection of the Sync Pin
Oscillator
SYNC
RtRt
Ct
VBIAS
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Figure 22 shows the part with no synchronization. In this
circuit the internal clock is fixed by the external timing
resistor RT. The SYNC pin can be tied to GND through a
series resistor to prevent false triggering in a noisy
environment.
Figure 22. Fixed Frequency
SYNC
NCP1034
FSW = 200 kHz
RT
10 k
(optional)
20 k
Figure 23 shows the part synchronized to an external
clock through the SYNC pin. The synchronization
frequency can be up to 20% greater then the programmed
fixed frequency (Example: RT = 20 k / 200 kHz and the
SYNC input frequency can range from 200−220 kHz). The
clock frequency at the SYNC pin replaces the master clock
generated by the internal oscillator circuit. Pulling the
SYNC pin low programs the part to run freely at the
frequency programmed by RT. When pulling the SYNC pin
low a 4.7 kΩ resistor should be used.
Figure 23. External Synchronization
SYNC
NCP1034
FSW = 220 kHz
RT
4.7 k
(optional)
20 k
Input: = 220 kHz
TTL
Logic
Figure 24 shows the part operating in the master slave
synchronization configuration. In this configuration all
three parts are connected together through the SYNC pin in
order to synchronize the system switching frequency. The
RT timing resistor can be the same value for all three parts
(RT = 20 k / 20 k / 20 k) which would make the highest
frequency part the master, or to guarantee one part is the
master the timing resistor can be slightly lower in value. (RT
= 20 k / 22 k / 22 k)
Figure 24. Master Slave Synchronization
SYNC
NCP1034
(Master #1)
FSW = 200 kHz
RT
20 k
SYNC
NCP1034
(Slave #1)
FSW = 180 kHz
RT
22 k
SYNC
NCP1034
(Slave #2)
FSW = 180 kHz
RT
22 k
Synchronized System
Frequency = 200 kHz
Output Voltage
Output voltage can be set by an external resistor divider
according to this Equation 3:
VOUT +Vref @ǒ1)R1
R2Ǔ(eq. 3)
Where Vref is the internal reference voltage 1.25 V. Absolute
values of resistors R1 and R2 depend on compensation
network type. See compensation paragraph for details.
Inductor Selection
The inductor selection is based on the output power,
frequency, input and output voltage and efficiency
requirements. High inductor values cause low current
ripple, slower transient response, higher efficiency and
increased size. Inductor design can be reduced to desire
maximum current ripple in the inductor. It is good to have
current ripple (ILmax) between 20% and 50% of the output
current.
For buck converter, the inductor should be chosen
according to Equation 4.
L+ǒVOUT
f@ILmaxǓǒ1*
VOUT
VINmaxǓ(eq. 4)
Output Capacitor Selection
The output voltage ripple and transient requirements
determine the output capacitor type and value. The
important parameter for the selection of the output capacitor
is equivalent serial resistance (ESR). If the capacitor has low
ESR, it often has sufficient capacity for filtering as well as
an adequate RMS current rating.
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The value of the output capacitor should be calculated
using the following equation:
COUT w
IL
8@f@ǒVOUT *IL@ESRǓ(eq. 5)
For higher switching frequency, it is suitable to use
multi−layer ceramic capacitor (MLCC) with very low ESR.
The advantages are small size, low output voltage ripple and
fast transient response. The disadvantage of MLCC type is
the requirement to use a Type III compensation network.
Input Capacitor Selection
The input capacitor is used to supply current pulses while
high−side MOSFET is on. When the MOSFET is off, the
input capacitor is being charged. The value of this capacitor
can be selected with Equation 6:
CIN w
IOUT @
VOUT
VIN
@ǒ1*VOUT
VIN Ǔ
f@VIN
(eq. 6)
Where VIN is the input voltage ripple and the
recommended value is about 2% − 5% of VIN. The input
capacitor must be large enough to handle the input ripple
current. Its value should be calculated using Equation 7:
IRMS +IOUT @
VOUT @ǒ1*VOUT
VIN Ǔ
VIN
Ǹ(eq. 7)
Power MOSFET Selection
The NCP1034 uses two N−channel MOSFET’s. They can
be primary selected by RDS(on), maximum drain−to−source
voltage and gate charge. RDS(on) impacts conductive losses
and gate charge impacts switching losses. The low side
MOSFET is selected primarily for conduction losses, and
the high−side MOSFET is selected to reduce switching
losses especially when the output voltage is less than 30% of
the input voltages. The drain−to−source breakdown voltage
must be higher than the maximum input voltage. Conductive
power losses can be calculated using the Equations 8 and 9:
PCOND*HIGHFET +I2
OUT @RDS(on) @
VOUT
VIN
(eq. 8)
PCOND*LOWFET +I2
OUT @RDS(on) @ǒ1*
VOUT
VIN Ǔ(eq. 9)
Switching losses are depended on drain−to−source
voltage at turn−off state, output current and switch−on and
switch−off time as is shown by Equation 10.
PSW +
VDS(off)
2@ǒtON )tOFFǓ@f@IOUT (eq. 10)
tON and tOFF times are dependent on the transistor gate.
The MOSFET output capacitance loss is caused by the
charging and discharging during the switching process and
can be computed using Equation 11.
PCOSS +
COSS @VIN 2@f
2
(eq. 11)
Where COSS = CDS + CGS.
Significant power dissipation is caused by the reverse
recovery charge in the low−side MOSFET body diode,
which conducts at dead time. This charge is needed to close
the diode. The current from the input power supply flows
through the high−side MOSFET to the low−side MOSFET
body diode. This power dissipation can be calculated using
Equation 12.
PQRR +QRR @VIN @f(eq. 12)
QRR is the diode recovery charge as given in the
manufacturer’s datasheet. For some types of MOSFETs, this
dissipation may be dominant at high input voltages. It is
necessary to take care when selecting a MOSFET. An
external Schottky diode across the low−side MOSFET can
be used to eliminate the reverse recovery charge power loss.
The Schottky diode’s forward voltage should be lower than
that of the body diode, and reverse recovery time (trr) should
be lower then that of the body diode. The Schottky diode’s
capacitance loss can be calculated as shown in Equation .
PC(Schottky) +
CSchottky @VIN 2@f
2
(eq. 13)
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Figure 25. MOSFETs Timing Diagram
High−Side
Logic Signal
Low−Side
Logic Signal
High−Side
MOSFET
Low−Side
MOSFET
RDSmax
RDS(on)min
RDSmax
RDS(on)min
tdead tdead
tf
td(on)
trtd(off)
trtf
td(on) td(off)
MOSFETs delays, turn−on and turn−off times must be
short enough to prevent cross conduction. If not, there will
be cross conduction from the input through both MOSFETs
to ground. Due to this fact, the following conditions must be
true:
td(on)high )tdead utd(off)low )tflow (eq. 14)
td(on)low )tdead utd(off)high )tfhigh
Where tdead is the controller dead band time, td(on), tr, td(off)
and tf are MOSFETs parameters. These parameters can be
found in the datasheet for specific conditions.
Bootstrap Circuit
This circuit is used to obtain a voltage higher than the
input voltage in order to switch−on high side N MOSFET.
The bootstrap capacitor is charged from the IC’s supply
voltage through D1, when the low side MOSFET is
switched−on up to the IC’s supply voltage. It must have
enough capacity to supply power for the high−side circuit
when the high−side MOSFET is being switched on. The
minimum value recommended for the bootstrap capacitor is
100 nF. Diode D1 has to be designed to withstand a reverse
voltage given by the following equation:
D1VRmin +VIN *VCC (eq. 15)
Soft−Start
The soft−start time is set by capacitor connected between
SS/SD Pin and ground. This function is used for controlling
the output voltage slope and limiting startup currents. The
start−up sequence initiates when Power On Ready (POR)
internal signal rises to logic high level. That means the
supply voltage, low side drive supply voltage and external
UVLO are over the set thresholds. The soft−start capacitor
is charged by 20 A current source. If POR is low, the SS/SD
Pin is internally pulled to GND, which means that the
NCP1034 is in a shutdown state. The SS/SD Pin voltage
(0 V to 2.6 V) controls internal current source (64 A to
0 A) with negative linear characteristic. This current
source injects current into the resistor (25 k) connected
between the Fb pin and negative input of the error amplifier
and into the external feedback resistor network. Voltage
drop on these resistors is over 1.6 V, which is enough to force
the error amplifier into negative saturation state and to block
switching.
When the soft−start pin reaches around 1.2 V (exact value
depends on feedback and compensation network and on
soft−start capacitor; a larger soft−start capacitor and a lower
compensation capacity decrease this level) the IC starts
switching. The impact of controlled current source
decreases and the output voltage starts to rise. When the
soft−start capacitor voltage reaches 2.6 V, the output voltage
is at nominal value.
The soft−start time must be at least 10 times longer than
the time needed to charge the compensation network from
the output of the error amplifier. If the soft−start time is not
long enough, the soft−start sequence would be faster than the
charging compensation network and the IC would start
without slowly increasing the output voltage. The soft−start
capacitance can be calculated using Equation 16.
CSS +15 @10−6@TSS (eq. 16)
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Figure 26. Soft−Start
5V
~2.6V
~1.2V
0V
SS
POR
VOUT
64A
IFB
>1.6V
FB
Voltage
1.25V
1.25V
0V
Start to Prebiased Output
The NCP1034 is able to startup into a prebiased output
capacitor. The low−side MOSFET does not turn on before
high−side MOSFET gets the first turn−on pulse. During this
time, the energy is not discharged by the low−side MOSFET
until the soft−start sequence crosses the programmed output
voltage.
Figure 27. Startup to Prebiased Output
~1.2V
~2.6V
LDRV
HDRV
VOUT
~5V
SS
Overcurrent Protection
The voltage drop across the low side MOSFET RDS(on) is
connected through resistor R8 and into the IC though pin 13
OCin. Within the IC, this value is compared with the value
programmed by resistor R7 to set the overcurrent limit. The
programmed current limit is set by selecting the value of R7,
which is connected between pin 1 OCset and GND. If the
voltage drop is larger than the set value, the NCP1034 goes
into hiccup mode. During this time, both external MOSFETs
are turned off and the soft start capacitor is discharged with
a current equal to 5% of the charging current. The capacitor
continues to discharge until the voltage reaches 0.25 V, and
then the IC initiates a standard soft start sequence.
The recommended value for the protection resistor R8 is
10 k. The R7 resistance value can be calculated using
Equation 17:
R7+R8
3.56 @RDS(on) @Ipk
(eq. 17)
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Figure 28. Overcurrent Protection (Hi−Cup Mode)
SS ~1.2V
5V 0.3V ~1.2V
~1.9V 0.3V
~1.2V
~1.9V0.3V
~1.2V
~2.6V
5V
VOUT
IOUT
ROUT
~2.6V
The NCP1034 provides protection of the low−side
MOSFET against positive overcurrent (from output to this
MOSFET). Its value can be calculated using Equation 18:
IPos +5125 *0.184 @R8
R7 @RDS(on)
(eq. 18)
Compensation Circuit
The NCP1034 is a voltage mode buck convertor with a
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°).
The transfer function of the power stage (the output LC
filter) is a double pole system. The resonance frequency of
this filter is expressed as follows:
fP0 +1
2@@L@COUT
Ǹ(eq. 19)
One zero of this LC filter is given by the output capacitance
and output capacitor ESR. Its value can be calculated by
using the following equation:
fZ0 +1
2@@COUT @ESR (eq. 20)
The next parameter that must be chosen is the zero
crossover frequency f0. It can be chosen to be 1/10 − 1/5 of
the switching frequency. These three parameters show the
necessary type of compensation that can be selected from
Table 1.
Table 1. COMPENSATION TYPES
Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type
fP0 < fZ0< f0 < fS/2 Type II (PI) Electrolytic, Tantalum
fP0 < f0< fZ0 < fS/2 Type III (PID) Method I Tantalum, Ceramic
fP0 < f0 < fS/2 < fZ0 Type III (PID) Method II Ceramic
Compensation Type II (PI)
This compensation is suitable for low−cost electrolytic
capacitor. The zero created by the capacitor’s ESR is a few
kHz and the zero crossover frequency is chosen to be 1/10
of the switching frequency. Components of the PI
compensation (Figure 29) network can be specified by the
following equations:
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Figure 29. PI compensation (II Type)
+
−
OTA
R2
R1
Vref
VOUT
RC1
CC1
CC2*
*Optional
RC1 +
2@@f0@L@VRAMP @VOUT
ESR @VIN @Vref @gm
(eq. 21)
CC1 +1
0.75 @2@@fP0 @RC1
CC2 +1
@RC1 @fS
R1 +
VOUT *Vref
Vref
@R2
VRAMP is the peak−to−peak voltage of the oscillator ramp
and gm is the transconductance error amplifier gain.
Capacitor CC2 is optional.
Compensation Type III (PID)
Tantalum and ceramics capacitors have lower ESR than
electrolytic, so the zero of the output LC filter goes to a
higher frequency above the zero crossover frequency. This
situation needs to be compensated by the PID compensation
network that is show in Figure 30.
+
−
R1
R2 VREF
OTA
RC1 CC1
CC2
VOUT
RFB1
CFB1
Figure 30. PID Compensation (III Type)
There are two methods to select the zeros and poles of
compensation network. The first one (method I) is useable
for tantalum output capacitors, which have a higher ESR
than ceramic, and its zeros and poles can be calculated
shown below:
fZ1 +0.75 @fP0
(eq. 22)
fZ2 +fP0
fP2 +fZ0
fP3 +
fS
2
The second one (method II) is for ceramic capacitors:
fZ2 +f0@1*sin max
1)sin max
Ǹ
(eq. 23)
fP2 +f0@1)sin max
1*sin max
Ǹ
fZ1 +0.5 @fZ2
fP3 +0.5 @fS
The remaining calculations are the same for both methods.
RC1 uu 2
gm
(eq. 24)
CC1 +1
2@@fZ1 @RC1
CC2 +1
2@@fP3 @RC1
CFB1 +
2@@f0@L@VRAMP @COUT
VIN @RC1
RFB1 +1
2@CFB1 @fP2
R1 +1
2@@CFB1 @fZ2
*RFB1
R2 +
Vref
VOUT *Vref
@R1
To check the design of this compensation network, the
equation must be true
R1 @R2 @RFB1
R1 @RFB1 )R2 @RFB1 @R1 @R2 u1
gm (eq. 25)
If it is not true, then a higher value of RC1 must be selected.
Input Power Supply
The NCP1034 controller and built−in drivers need to be
powered through VCC, DRVVCC and Vb pins with a voltage
between 10 V – 18 V. The supply current requirement is a
summation of the static and dynamic currents. Static current
consumption can be calculated by the following equation:
ICS +ICC )IC)IB(eq. 26)
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Dynamic current consumption is calculated using the
following equation, base on the switching frequency and
MOSFET gate charge.
ICD +ǒQG(low) )QG(high)Ǔ@f(eq. 27)
To power the device, an external power supply or voltage
regulator from VIN can be used. Two options are a linear
shunt voltage regulator and a shunt voltage regulator with
transistor, as shown in Figure 31. A voltage regulator
without a transistor can be used when the power
consumption is low and zener diode power dissipation is
acceptable. Otherwise, a shunt regulator with transistor can
be used.
Figure 31. Linear Shunt
Voltage Regulator
VCC
VIN
CD
VCC
VIN
CD
Figure 32. Shunt Voltage
Regulator with Transistor
R
For the linear shunt voltage regulator (option a) the VCC
voltage is the same as the zener diode reverse voltage VZ.
The value of the resistor R can be calculated using
Equation 28, where IZT is the minimum reverse current at
VZ. The value selected should be lower than the calculated
value. The maximum power losses of resistor R and the
zener diode D can be calculated by Equations 29 and 30.
Rt
VINmin *VCC
ICS )ICD )IZT
(eq. 28)
PR+(VINmax *VCC)@(ICS )ICD)(eq. 29)
PD+ǒVINmax *VCC
R*ICSǓ(eq. 30)
The shunt voltage regulator with transistor (option b) is
advantageous when the zener diode loss is too high or when
input voltage varies across a wide range and it is difficult to
set a bias point. The output voltage is lower than VZ due to
the VBE of the transistor. The maximum resistor value of R
can be calculated by Equation 31, where is the transistor
DC current gain. The maximum power dissipation of the
resistor, zener diode and transistor are calculated by
Equations 32 to 34. The transistor reverse breakdown
voltage must be selected to be able to withstand the voltage
difference between maximum input voltage and VCC.
Rt
VINmin *VZT
ICS)ICD
)IZT
(eq. 31)
PR+ǒVINmax *VCCǓ@ǒICS )ICD
)IZTǓ(eq. 32)
PD+ǒVINmax *VZT
R*
ICS
Ǔ@VZT (eq. 33)
PD+ǒVINmax *VZT
R*
ICS
Ǔ@VZT (eq. 34)
PT+ǒVINmax *VCCǓ@ǒICS )ICDǓ(eq. 35)
Table 2. POWER SUPPLY REGULTOR EXAMPLES
Components MOSFETs
QG(TOT)
(nC)
f
(kHz)
VINmax
(V)
VINmin
(V)
ISUPPLYmax
(mA)
RBIAS
(kW)ZD Transistor
LS−FET NTD24N06 24 200 60 36 8.7 2.6 MMSZ4699 −
HS−FET NTD3055 7.1
LS−FET NTD24N06 24 300 60 20 16.9 10 MMSZ4699 MJD31
HS−FET NTD24N06 24
PCB Layout
The layout of high−frequency and high−current switching
converters has a large impact on the circuit parameters. It is
important, therefore, to pay close attention to the PCB
layout.
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The input capacitor, MOSFETs, inductor and output
capacitor should be placed as close as possible to one
another. This is suitable to reduce EMI and to minimize VS
overshoots. Connecting the signal and power ground at one
point near the output connector improves load regulation.
Connection between the source pin of the low side MOSFET
and the IC should be very short with wide traces and
optimally using two layers to achieve minimum inductance
between them.
The blocking and bootstrap capacitors should be placed as
close as possible to the IC. The feedback and compensation
network should be close to the IC to minimize noise.
TYPICAL APPLICATION
Figure 33. Single Output Buck Converter from 38 V − 58 V to 5 V/5 A @ 200 kHz
12
5
15
4
16
1
14
10
11
13
7
6
2
3
R7
10k
R6
20k
C5
220n
R5
3k9
VCC
SYNC
RT
UVLO
OCSET
GND
HDRV
VS
OCIN
LDRV
PGND
FB
COMP
SS/SD
C10
100n
D1
1N4148
C4
100n
R4
110k
IC1
NCP1034SMD
89
DRVVCC VB
R3
4k7
C7
330p
C6
12n
R8
10k
48 V $20%
C1A
2u2
C9
47
C9B
47
Q2
NTD3055
Q3
NTD24N06
L1
13
R2
5k6
R1
16k9
R9
1k2
C8
1n8
GND GND GND GND GND
GND
GND
GND
GND
C1B
2u2
C9C
47
GND
GND
R10
10k
GND
D2
C2
100n
C3 100n
X1−1
X1−2
X2−2
X2−1
R15
0R
R11A 10k
R11B 10k
R11C 10k
R11D 10k
R11E 10k
MMSZ4699
5V@5A, 200kHz
50
55
60
65
70
75
80
85
90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN = 58 V
48 V
38 V
Figure 34. Efficiency and Power Loss of Circuit at Figure 33
IOUT (A)
EFFICIENCY (%)
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Bill of Materials
Designator Qty Description Value Tolerance Footprint Manufacturer
Manufacturer
Part Number
R9 1 Resistor 1k2 1% 1206 Vishay CRCW10261K20FKEA
R5 1 Resistor 3k9 1% 1206 Vishay CRCW10263K90FKEA
R3 1 Resistor 4k7 1% 1206 Vishay CRCW10264K60FKEA
R2 1 Resistor 5k6 1% 1206 Vishay CRCW10265K60FKEA
R1 1 Resistor 16k9 1% 1206 Vishay CRCW102616K9FKEA
R6 1 Resistor 20k 1% 1206 Vishay CRCW102620K0FKEA
R11A, R11B,
R11C, R11D,
R11E
5 Resistor 12k 1% 1206 Vishay CRCW102612K0FKEA
R4 1 Resistor 110k 1% 1206 Vishay CRCW1206110KFKEA
R7, R8, R10 3 Resistor 10k 1% 1206 Vishay CRCW120610K0FKEA
C8 1 Ceramic Capacitor 1n8 10% 1206 Kemet C1206C182K5FA−TU
C6 1 Ceramic Capacitor 12n 10% 1206 Kemet C1206C123K5FACTU
C5 1 Ceramic Capacitor 220n 10% 1206 Kemet C1206C224K5RACTU
C7 1 Ceramic Capacitor 330p 10% 1206 Kemet −
C2, C3, C4, C10 4Ceramic Capacitor 100n 10% 1206 Kemet C1206F104K1RACTU
C9A, C9B, C9C 3Ceramic Capacitor 47/6.3V 20% 1210 Kemet C1210C476M9PAC7800
C1A, C1B 2Ceramic Capacitor 2.2/100V 10% 1210 Murata GRM32ER72A225KA35L
L1 1 Inductor SMD 1320% 13x13 Würth 744355131
D1 1 Switching Diode MMSD4148 −SOD123 ON Semiconductor MMSD4148T1G
D2 1 Zener Diode 12V MMSZ4699 −SOD123 ON Semiconductor MMSZ4699T1G
Q2 1 Power N−MOSFET NTD3055 −DPAK ON Semiconductor NTD3055−150G
Q3 1 Power N−MOSFET NTD24N06 −DPAK ON Semiconductor NTD24N06T4G
IO1 1 Synchronous PWM
Buck Controller
NCP1034 −SOIC16 ON Semiconductor NCP1034DR2G
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Figure 35. Top Layer Figure 36. Bottom Layer
Figure 37. Top Side Components Figure 38. Bottom Side Components
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70 mm_
44 mm_
Figure 39. Typical Application Board Photos
ORDERING INFORMATION
Device Package Shipping†
NCP1034DR2G SOIC−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1034
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PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NCP1034/D
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5817−1050
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