LT3800EFE - Linear Technology Corporation

LT3800

3800f

TYPICAL APPLICATIO

APPLICATIO S

FEATURES

■

Wide 4V to 60V Input Voltage Range

■

Output Voltages up to 36V

■

Adaptive Nonoverlap Circuitry Prevents Switch

Shoot-Through

■

Reverse Inductor Current Inhibit for Discontinuous

Operation Improves Efficiency with Light Loads

■

Output Slew Rate Controlled Soft-Start with

Auto-Reset

■

100µA No Load Quiescent Current

■

Low 10µA Current Shutdown

■

1% Regulation Accuracy

■

200kHz Operating Frequency

■

Standard Gate N-Channel Power MOSFETs

■

Current Limit Unaffected by Duty Cycle

■

Reverse Overcurrent Protection

■

16-Lead Thermally Enhanced TSSOP Package

High-Voltage Synchronous

Current Mode Step-Down

Controller

The LT

3800 is a 200kHz fixed frequency high voltage

synchronous current mode step-down switching regula-

tor controller. The IC drives standard gate N-channel power

MOSFETs and can operate with input voltages from 4V to

60V. An onboard regulator provides IC power directly from

and provides for output-derived power to minimize V

quiescent current. MOSFET drivers employ an internal

dynamic bootstrap feature, maximizing gate-source “ON”

voltages during normal operation for improved operating

efficiencies. The LT3800 incorporates Burst Mode

opera-

tion, which reduces no load quiescent current to under

100µA. Light load efficiencies are also improved through

a reverse inductor current inhibit, allowing the controller

to support discontinuous operation. Both Burst Mode

operation and the reverse-current inhibit features can be

disabled if desired. The LT3800 incorporates a program-

mable soft-start that directly controls the voltage slew rate

of the converter output for reduced startup surge currents

and overshoot errors. The LT3800 is available in a 16-lead

thermally enhanced TSSOP package.

DESCRIPTIO

■

12V and 42V Automotive and Heavy Equipment

■

48V Telecom Power Supplies

■

Avionics and Industrial Control Systems

■

Distributed Power Converters

12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO

Efficiency and Power Loss

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a registered trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258.

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

1.5nF 200k

100pF

680pF

174k

20k

82.5k

0.015Ω

BAS19

1N4148

1µF

×3

56µF

×2

10µF270µF

Si7850DP

Si7370DP B160

15µH

VIN

20V TO 55V

VOUT

12V AT 75W

3800 TA01a

LOAD

(A)

EFFICIENCY (%)

POWER LOSS (W)

100

3800 TA01b

0.1 1

= 24V

LOSS (48V)

= 48V

= 60V

= 36V

LT3800

3800f

FE PACKAGE

16-LEAD PLASTIC TSSOP

TOP VIEW

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

Supply Voltages

Input Supply Pin (V

) .............................. –0.3V to 65V

Boosted Supply Pin (BOOST) ................... –0.3V to 80V

Boosted Supply Voltage (BOOST – SW) .. –0.3V to 24V

Boosted Supply Reference Pin (SW) ........... –2V to 65V

Local Supply Pin (V

) ............................. –0.3V to 24V

Input Voltages

SENSE

, SENSE

–

...................................... –0.3V to 40V

SENSE

– SENSE

–

......................................... –1V to 1V

BURST_EN Pin ......................................... –0.3V to 24V

Other Inputs (SHDN, C

, V

) .......... –0.3V to 5.0V

Input Currents

SHDN, C

............................................... –1mA to 1mA

Maximum Temperatures

Operating Junction Temperature Range (Note 2)

LT3800E (Note 3) ............................. –40°C to 125°C

LT3800I ............................................ –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

ORDER PART

NUMBER

JMAX

= 125°C, θ

= 40°C/W, θ

= 10°C/W

EXPOSED PAD (PIN 17) IS SGND

MUST BE SOLDERED TO PCB

LT3800EFE

LT3800IFE

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UUW

(Note 1)

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,

SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range (Note 4) ●460V

Minimum Start Voltage ●7.5 V

UVLO Threshold (Falling) ●3.65 3.80 3.95 V

UVLO Hysteresis 670 mV

VIN

Supply Current V

> 9V 20 µA

Burst Mode Current V

BURST_EN

= 0V, V

= 1.35V 20 µA

Shutdown Current V

SHDN

= 0V ●815 µA

BOOST

Operating Voltage ●75 V

Operating Voltage Range (Note 5) V

BOOST

– V

●20 V

UVLO Threshold (Rising) V

BOOST

– V

UVLO Hysteresis V

BOOST

– V

0.4 V

BOOST

BOOST Supply Current (Note 6) 1.4 mA

BOOST Burst Mode Current V

BURST_EN

= 0V 0.1 µA

BOOST Shutdown Current V

SHDN

= 0V 0.1 µA

Operating Voltage (Note 5) ●20 V

Output Voltage ●8.0 8.3 V

UVLO Threshold (Rising) 6.25 V

UVLO Hysteresis 500 mV

Consult LTC Marketing for parts specified with wider operating temperature ranges.

FE PART

MARKING

3800EFE

3800IFE

LT3800

3800f

Note 1: Absolute Maximum ratings are those values beyond which the life

of a device may be impaired.

Note 2: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: The LT3800E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT3800I is guaranteed over the full –40°C to 125°C operating junction

temperature range.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC

Supply Current (Note 6) ●3 3.6 mA

Burst Mode Current V

BURST_EN

= 0V 80 µA

Shutdown Current V

SHDN

= 0V 20 µA

Short-Circuit Current ●–40 –120 mA

SHDN

Enable Threshold (Rising) ●1.30 1.35 1.40 V

Threshold Hysteresis 120 mV

SENSE

Common Mode Range ●036

Current Limit Sense Voltage V

SENSE+

– V

SENSE–

●140 150 175 mV

Reverse Protect Sense Voltage V

SENSE+

– V

SENSE–

, V

BURST_EN

= V

–150 mV

Reverse Current Offset V

BURST_EN

= 0V or V

BURST_EN

= V

10 mV

SENSE

Input Current V

SENSE(CM)

= 0V 0.8 mA

SENSE+

+ I

SENSE–

) 2V < V

SENSE(CM)

< 3.5V –20 µA

SENSE(CM)

> 4V –0.3 mA

Operating Frequency 190 200 210 kHz

●175 220 kHz

Error Amp Reference Voltage Measured at V

Pin 1.224 1.231 1.238 V

●1.215 1.245 V

Feedback Input Current 25 nA

FB(SS)

Soft-Start Disable Voltage V

Rising 1.185 V

Soft-Start Disable Hysteresis 300 mV

CSS

Soft-Start Capacitor Control Current 2 µA

Error Amp Transconductance ●275 350 400 µmhos

Error Amp DC Voltage Gain 62 dB

Error Amp Output Range Zero Current to Current Limit 1.2 V

Error Amp Sink/Source Current ±30 µA

TG,BG

Gate Drive Output On Voltage (Note 7) 9.8 V

Gate Drive Output Off Voltage 0.1 V

TG,BG

Gate Drive Rise/Fall Time 10% to 90% or 90% to 10% 50 ns

TG(OFF)

Minimum Off Time 450 ns

TG(ON)

Minimum On Time ●300 500 ns

NOL

Gate Drive Nonoverlap Time TG Fall to BG Rise 200 ns

BG Fall to TG Rise 150 ns

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V,

SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted.

Note 4: V

voltages below the start-up threshold (7.5V) are only

supported when V

is externally driven above 6.5V.

Note 5: Operating range dictated by MOSFET absolute maximum gate-

source voltage ratings.

Note 6: Supply current specification does not include switch drive

currents. Actual supply currents will be higher.

Note 7: DC measurement of gate drive output “ON” voltage is typically

8.6V. Internal dynamic bootstrap operation yields typical gate “ON”

voltages of 9.8V during standard switching operation. Standard operation

gate “ON” voltage is not tested but guaranteed by design.

LT3800

3800f

VCC UVLO Threshold (Rising)

vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

ICC Current Limit vs Temperature

Error Amp Transconductance

vs Temperature

Shutdown Threshold (Rising)

vs Temperature VCC vs Temperature

Shutdown Threshold (Falling)

vs Temperature

VCC vs ICC(LOAD) VCC vs VIN

TEMPERATURE (°C)

–50 –25

1.37

1.36

1.35

1.34

1.33 100

3800 G01

0 50 12525 75

SHUTDOWN THRESHOLD, RISING (V)

–50 –25 1000 50 12525 75

TEMPERATURE (°C)

1.240

1.235

1.230

1.225

1.220

3800 G02

SHUTDOWN THRESHOLD, FALLING (V)

TEMPERATURE (°C)

–50 –25

(V)

8.0

8.1

7.8

7.9

125

3800 G03

050

25 75 100

= 0mA

= 20mA

ICC(LOAD) (mA)

VCC (V)

3800 G04

10 20 30

8.05

8.00

7.95

7.90

7.85 51525

TA = 25°C

(V)

379 12

3800 G05

56 810 11

= 20mA

= 25°C

–50 –25 1000 50 12525 75

TEMPERATURE (°C)

200

175

150

125

100

3800 G06

ICC CURRENT LIMIT (mA)

TEMPERATURE (°C)

–50 –25 100

3800 G07

0 50 12525 75

6.30

6.25

6.20

6.15

UVLO THRESHOLD, RISING (V)

ICC vs VCC (SHDN = 0V)

(V)

(µA)

3800 G12

0246810

12 14 18 20

= 25°C

TEMPERATURE (°C)

–50 –25 1000 50 12525 75

380

360

340

320

3800 G08

ERROR AMP TRANSCONDUCTANCE (µmho)

LT3800

3800f

Operating Frequency

vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

PI FU CTIO S

(Pin 1): Converter Input Supply.

NC (Pin 2): No Connection.

SHDN (Pin 3): Precision Shutdown Pin. Enable threshold

is 1.35V (rising) with 120mV of input hysteresis. When in

shutdown mode, all internal IC functions are disabled. The

precision threshold allows use of the SHDN pin to incor-

porate UVLO functions. If the SHDN pin is pulled below

0.7V, the IC enters a low current shutdown mode with

VIN

< 10µA. In low-current shutdown, the IC will sink 20µA

from the V

pin until that local supply has collapsed.

Typical pin input bias current is <10nA and the pin is

internally clamped to 6V.

(Pin 4): Soft-Start AC Coupling Capacitor Input.

Connect capacitor (C

) in series with a 200k resistor from

pin to converter output (V

OUT

). Controls converter start-

up output voltage slew rate (∆V

OUT

/∆t). Slew rate corre-

sponds to 2µA average current through the soft-start

coupling capacitor. The capacitor value for a desired

output startup slew rate follows the relation:

= 2µA/(∆V

OUT

/∆t)

Shorting this pin to SGND disables the soft-start function.

BURST_EN (Pin 5): Burst Mode Operation Enable Pin.

This pin also controls reverse-inhibit mode of operation.

When the pin voltage is below 0.5V, Burst Mode operation

and reverse-current inhibit functions are enabled. When

the pin voltage is above 0.5V, Burst Mode operation is

disabled, but reverse-current inhibit operation is main-

tained. DC/DC converters operating with reverse-current

inhibit operation (BURST_EN = V

) have a 1mA minimum

load requirement. Reverse-current inhibit is disabled when

the pin voltage is above 2.5V. This pin is typically shorted

to ground to enable Burst Mode operation and reverse-

current inhibit, shorted to V

to disable Burst Mode

operation while enabling reverse-current inhibit, and con-

nected to V

pin to disable both functions. See Applica-

tions Information section.

(Pin 6): Error Amplifier Inverting Input. The

noninverting input of the error amplifier is connected to an

internal 1.231V reference. Desired converter output volt-

age (V

OUT

) is programmed by connecting a resistive

divider from the converter output to the V

pin. Values for

the resistor connected from V

OUT

to V

(R2) and the

resistor connected from V

to ground (R1) can be calcu-

lated via the following relationship:

RR VOUT

1 231 1=⎛

⎝

⎜⎞

⎠

⎟

•.–

Error Amp Reference

vs Temperature

I(SENSE+ + SENSE–) vs VSENSE(CM)

SENSE(CM)

(V)

0 0.5 1.5 2.5 3.5 4.5

(SENSE+ + SENSE

–

)

(µA)

800

600

400

200

–200

–400 1.0 2.0 3.0 4.0

3800 G09

5.0

= 25°C

TEMPERATURE (°C)

3800 G10

–50

220

210

200

190

180

–25

OPERATING FREQUENCY (kHz)

1000 50 12525 75

–50 –25 1000 50 12525 75

TEMPERATURE (°C)

ERROR AMP REFERENCE (V)

1.232

1.231

1.230

1.229

1.228

1.227

3800 G11

LT3800

3800f

The V

pin input bias current is 25nA, so use of extremely

high value feedback resistors could cause a converter

output that is slightly higher than expected. Bias current

error at the output can be estimated as:

∆V

OUT(BIAS)

= 25nA • R2

(Pin 7): Error Amplifier Output. The voltage on the V

pin corresponds to the maximum (peak) switch current

per oscillator cycle. The error amplifier is typically config-

ured as an integrator by connecting an RC network from

this pin to ground. This network creates the dominant pole

for the converter voltage regulation feedback loop. Spe-

cific integrator characteristics can be configured to opti-

mize transient response. Connecting a 100pF or greater

high frequency bypass capacitor from this pin to ground

is also recommended. When Burst Mode operation is

enabled (see Pin 5 description), an internal low impedance

clamp on the V

pin is set at 100mV below the burst

threshold, which limits the negative excursion of the pin

voltage. Therefore, this pin cannot be pulled low with a

low-impedance source. If the V

pin must be externally

manipulated, do so through a 1kΩ series resistance.

SENSE

–

(Pin 8): Negative Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

SENSE

(Pin 9): Positive Input for Current Sense Ampli-

fier. Sensed inductor current limit set at ±150mV across

SENSE inputs.

PI FU CTIO S

PGND (Pin 10): High Current Ground Reference for Syn-

chronous Switch. Current path from pin to negative termi-

nal of V

decoupling capacitor must not corrupt SGND.

BG (Pin 11): Synchronous Switch Gate Drive Output.

(Pin 12): Internal Regulator Output. Most IC func-

tions are powered from this pin. Driving this pin from an

external source reduces V

pin current to 20µA. This pin

is decoupled with a low ESR 1µF capacitor to PGND.

In shutdown mode, this pin sinks 20µA until the pin

voltage is discharged to 0V. See Typical Performance

Characteristics.

NC (Pin 13): No Connection.

SW (Pin 14): Reference for V

BOOST

Supply and High

Current Return for Bootstrapped Switch.

TG (Pin 15): Bootstrapped Switch Gate Drive Output.

BOOST (Pin 16): Bootstrapped Supply – Maximum Oper-

ating Voltage (Ground Referred) to 75V. This pin is

decoupled with a low ESR 1µF capacitor to pin SW. The

voltage on the decoupling capacitor is refreshed through

a rectifier from either V

or an external source.

Exposed Package Backside (SGND) (Pin 17): Low Noise

Ground Reference. SGND connection is made through the

exposed lead frame on back of TSSOP package which

must be soldered to the PCB ground.

LT3800

3800f

FU CTIO AL DIAGRA

–+

–

UVLO

(<4V)

BST

UVLO

REG

FEEDBACK

REFERENCE

–

1.231V

3.8V

REG

INTERNAL

SUPPLY RAIL

116

UVLO

(<6V)

SHDN

DRIVE

CONTROL

DRIVE

CONTROL

NOL

SWITCH

LOGIC

DRIVE

CONTROL

BURST_EN

SENSE

–

1.185V

0.5V

ERROR

AMP

2µA

Burst Mode

OPERATION

SOFT-START

DISABLE/BURST

ENABLE

OSCILLATOR

SLOPE COMP

GENERATOR

BOOST

11 BG

PGND

SENSE

GND

3800 FD

BOOSTED

SWITCH

DRIVER

CURRENT

SENSE

COMPARATOR

–+

160mV

SYNCHRONOUS

SWITCH DRIVER

REVERSE

CURRENT

INHIBIT

10mV

–

LT3800

3800f

Overview

The LT3800 is a high input voltage range step-down

synchronous DC/DC converter controller IC that uses a

200kHz constant frequency, current mode architecture

with external N-channel MOSFET switches.

The LT3800 has provisions for high efficiency, low load

operation for battery-powered applications. Burst Mode

operation reduces total average input quiescent currents

to 100µA during no load conditions. A low current shutdown

mode can also be activated, reducing quiescent current to

<10µA. Burst Mode operation can be disabled if desired.

The LT3800 also employs a reverse-current inhibit fea-

ture, allowing increased efficiencies during light loads

through nonsynchronous operation. This feature disables

the synchronous switch if inductor current approaches

zero. If full time synchronous operation is desired, this

feature can be disabled.

Much of the LT3800’s internal circuitry is biased from an

internal linear regulator. The output of this regulator is the

pin, allowing bypassing of the internal regulator. The

associated internal circuitry can be powered from the

output of the converter, increasing overall converter effi-

ciency. Using externally derived power also eliminates the

IC’s power dissipation associated with the internal V

regulator.

Theory of Operation (See Block Diagram)

The LT3800 senses converter output voltage via the V

pin. The difference between the voltage on this pin and an

internal 1.231V reference is amplified to generate an error

voltage on the V

pin which is, in turn, used as a threshold

for the current sense comparator.

During normal operation, the LT3800 internal oscillator

runs at 200kHz. At the beginning of each oscillator cycle,

the switch drive is enabled. The switch drive stays enabled

until the sensed switch current exceeds the V

derived

threshold for the current sense comparator and, in turn,

disables the switch driver. If the current comparator

APPLICATIO S I FOR ATIO

WUUU

threshold is not obtained for the entire oscillator cycle, the

switch driver is disabled at the end of the cycle for 450ns.

This minimum off-time mode of operation assures regen-

eration of the BOOST bootstrapped supply.

Power Requirements

The LT3800 is biased using a local linear regulator to

generate internal operational voltages from the V

pin.

Virtually all of the circuitry in the LT3800 is biased via an

internal linear regulator output (V

). This pin is decoupled

with a low ESR 1µF capacitor to PGND.

The V

regulator generates an 8V output provided there

is ample voltage on the V

pin. The V

regulator has

approximately 1V of dropout, and will follow the V

with voltages below the dropout threshold.

The LT3800 has a start-up requirement of V

> 7.5V. This

assures that the onboard regulator has ample headroom

to bring the V

pin above its UVLO threshold. The V

regulator can only source current, so forcing the V

above its 8V regulated voltage allows use of externally

derived power for the IC, minimizing power dissipation in

the IC. Using the onboard regulator for start-up, then

deriving power for V

from the converter output maxi-

mizes conversion efficiencies and is common practice. If

is maintained above 6.5V using an external source, the

LT3800 can continue to operate with V

as low as 4V.

The LT3800 operates with 3mA quiescent current from the

supply. This current is a fraction of the actual V

quiescent currents during normal operation. Additional

current is produced from the MOSFET switching currents

for both the boosted and synchronous switches and are

typically derived from the V

supply.

Because the LT3800 uses a linear regulator to generate

, power dissipation can become a concern with high

voltages. Gate drive currents are typically in the range

of 5mA to 15mA per MOSFET, so gate drive currents can

create substantial power dissipation. It is advisable to

derive V

and V

BOOST

power from an external source

whenever possible.

LT3800

3800f

The onboard V

regulator will provide gate drive power for

start-up under all conditions with total MOSFET gate charge

loads up to 180nC. The regulator can operate the LT3800

continuously, provided the V

voltage and/or MOSFET gate

charge currents do not create excessive power dissipation

in the IC. Safe operating conditions for continuous regu-

lator use are shown in Figure 1. In applications where these

conditions are exceeded, V

must be derived from an

external source after start-up.

APPLICATIO S I FOR ATIO

WUUU

Charge Pump Doubler

TOTAL FET GATE CHARGE (nC)

VIN (V)

50 100 150 200

3800 F01

SAFE

OPERATING

CONDITIONS

Figure 1. VCC Regulator Continuous Operating Conditions

OUT

1µF

B0520 B0520

1µF

Si1555DL

LT3800

OUT

1µF

B0520

1µF

Si1555DLSi1555DL

LT3800

B0520

3800 AI01

OUT

3800 AI04

•

LT3800

Inductor Auxiliary Winding

Charge Pump Tripler

In LT3800 converter applications with output voltages in

the 9V to 20V range, back-feeding V

and V

BOOST

from

the converter output is trivial, accomplished by connect-

ing diodes from the output to these supply pins. Deriving

these supplies from output voltages greater than 20V will

require additional regulation to reduce the feedback volt-

age. Outputs lower than 9V will require step-up techniques

to increase the feedback voltage to something greater than

the 8V V

regulated output. Low power boost switchers

are sometimes used to provide the step-up function, but

a simple charge-pump can perform this function in many

instances.

LT3800

3800f

Burst Mode

The LT3800 employs low current Burst Mode functionality

to maximize efficiency during no load and low load condi-

tions. Burst Mode operation is enabled by shorting the

BURST_EN pin to SGND. Burst Mode operation can be

disabled by shorting BURST_EN to either V

or V

When the required switch current, sensed via the V

voltage, is below 15% of maximum, the Burst Mode

operation is employed and that level of sense current is

latched onto the IC control path. If the output load requires

less than this latched current level, the converter will

overdrive the output slightly during each switch cycle.

This overdrive condition is sensed internally and forces

the voltage on the V

pin to continue to drop. When the

voltage on V

drops 150mV below the 15% load level,

switching is disabled and the LT3800 shuts down most of

its internal circuitry, reducing total quiescent current to

100µA. When the converter output begins to fall, the V

voltage begins to climb. When the voltage on the V

climbs back to the 15% load level, the IC returns to normal

operation and switching resumes. An internal clamp on

the V

pin is set at 100mV below the switch disable

threshold, which limits the negative excursion of the pin

voltage, minimizing the converter output ripple during

Burst Mode operation.

During Burst Mode operation, V

pin current is 20µA and

current is reduced to 80µA. If no external drive is

provided for V

, all V

bias currents originate from the

pin, giving a total V

current of 100µA. Burst current

can be reduced further when V

is driven using an output

derived source, as the V

component of V

current is

then reduced by the converter buck ratio.

Reverse-Current Inhibit

The LT3800 contains a reverse-current inhibit feature to

maximize efficiency during light load conditions. This

mode of operation allows discontinuous operation, and is

sometimes referred to as “pulse-skipping” mode. Refer to

Figure 2.

This feature is enabled with Burst Mode operation, and can

also be enabled while Burst Mode operation is disabled by

shorting the BURST_EN pin to V

When reverse-current inhibit is enabled, the LT3800 sense

amplifier detects inductor currents approaching zero and

disables the synchronous switch for the remainder of the

switch cycle. If the inductor current is allowed to go

negative before the synchronous switch is disabled, the

switch node could inductively kick positive with a high

dv/dt. The LT3800 prevents this by incorporating a 10mV

positive offset at the sense inputs.

APPLICATIO S I FOR ATIO

WUUU

PULSE SKIP MODE

ILILFORCED CONTINUOUS

DECREASING

LOAD

CURRENT

3800 F02

Figure 2. Inductor Current vs Mode

LT3800

3800f

With the reverse-current inhibit feature enabled, an LT3800

converter will operate much like a nonsynchronous

converter during light loads. Reverse-current inhibit re-

duces resistive losses associated with inductor ripple

currents, which improves operating efficiencies during

light-load conditions.

An LT3800 DC/DC converter that is operating in reverse-

inhibit mode has a minimum load requirement of 1mA

(BURST_EN = V

). Since most applications use output-

generated power for the LT3800, this requirement is met

by the bias currents of the IC, however, for applications

that do not derive power from the output, this require-

ment is easily accomplished by using a 1.2k resistor

connected from V

to ground as one of the converter

output voltage programming resistors (R1). There are no

minimum load restrictions when in Burst Mode operation

(BURST_EN < 0.5V) or continuous conduction mode

(BURST_EN > 2.5V).

Soft-Start

The LT3800 incorporates a programmable soft-start func-

tion to control start-up surge currents, limit output over-

shoot and for use in supply sequencing. The soft-start

function directly monitors and controls output voltage

slew rate during converter start-up.

As the output voltage of the converter rises, the soft-start

circuit monitors δV/δt current through a coupling capaci-

tor and adjusts the voltage on the V

pin to maintain an

average value of 2µA. The soft-start function forces the

programmed slew rate while the converter output rises to

95% regulation, which corresponds to 1.185V on the V

pin. Once 95% regulation is achieved, the soft-start circuit

is disabled. The soft-start circuit will re-enable when the V

pin drops below 70% regulation, which corresponds to

300mV of control hysteresis on the V

pin, which allows

for a controlled recovery from a ‘brown-out’ condition.

The desired soft-start rise time (t

) is programmed via

a programming capacitor C

SS1

, using a value that

corresponds to 2µA average current during the soft-start

interval. This capacitor value follows the relation:

SS1

–•t

OUT

is typically set to 200k for most applications.

APPLICATIO S I FOR ATIO

WUUU

OUT

SS1

3800 AI06

LT3800

Considerations for Low Voltage Output Applications

The LT3800 C

pin biases to 220mV during the soft-start

cycle, and this voltage is increased at network node “A” by

the 2µA signal current through R

, so the output has to

reach this value before the soft-start function is engaged.

The value of this output soft-start start-up voltage offset

OUT(SS)

) follows the relation:

OUT(SS)

= 220mV + R

• 2E

–6

which is typically 0.64V for R

= 200k.

In some low voltage output applications, it may be desir-

able to reduce the value of this soft-start start-up voltage

offset. This is possible by reducing the value of R

. With

reduced values of R

, the signal component caused by

voltage ripple on the output must be minimized for proper

soft-start operation.

Peak-to-peak output voltage ripple (∆V

OUT

) will be im-

posed on node “A” through the capacitor C

SS1

. The value

of R

can be set using the following equation:

SS OUT

=∆

1.3E

–6

It is important to use low ESR output capacitors for

LT3800 voltage converter designs to minimize this ripple

voltage component. A design with an excessive ripple

component can be evidenced by observing the V

during the start cycle.

LT3800

3800f

The soft-start cycle should be evaluated to verify that the

reduced R

value allows operation without excessive

modulation of the V

pin before finalizing the design.

If the V

pin has an excessive ripple component during the

soft-start cycle, converter output ripple should be reduced

or R

increased. Reduction in converter output ripple is

typically accomplished by increasing output capacitance

and/or reducing output capacitor ESR.

External Current Limit Foldback Circuit

An additional start-up voltage offset can occur during the

period before the LT3800 soft-start circuit becomes ac-

tive. Before the soft-start circuit throttles back the V

in response to the rising output voltage, current as high as

the peak programmed current limit (I

MAX

) can flow in the

inductor. Switching will stop once the soft-start circuit

takes hold and reduces the voltage on the V

pin, but the

output voltage will continue to increase as the stored

energy in the inductor is transferred to the output capaci-

tor. With I

MAX

flowing in the inductor, the resulting lead-

ing-edge rise on V

OUT

due to energy stored in the inductor

follows the relationship:

∆=⎛

⎝

⎜⎞

⎠

⎟

VI L

OUT MAX OUT

•

/12

APPLICATIO S I FOR ATIO

WUUU

Soft-Start Characteristic Showing Excessive Ripple Component Desirable Soft-Start Characteristic

Inductor current typically doesn’t reach I

MAX

in the few

cycles that occur before soft-start becomes active, but can

with high input voltages or small inductors, so the above

relation is useful as a worst-case scenario.

This energy transfer increase in output voltage is typically

small, but for some low voltage applications with relatively

small output capacitors, it can become significant. The

voltage rise can be reduced by increasing output capaci-

tance, which puts additional limitations on C

OUT

for these

low voltage supplies. Another approach is to add an

external current limit foldback circuit which reduces the

value of I

MAX

during start-up.

An external current limit foldback circuit can be easily

incorporated into an LT3800 DC/DC converter application

by placing a 1N4148 diode and a 47k resistor from the

converter output (V

OUT

) to the LT3800’s V

pin. This limits

the peak current to 0.25 • I

MAX

when V

OUT

= 0V. A current

limit foldback circuit also has the added advantage of

providing a reduced output current in the DC/DC converter

during short-circuit fault conditions, so a foldback circuit

may be useful even if the soft-start function is disabled.

If the soft-start circuit is disabled by shorting the C

to ground, the external current limit fold-back circuit must

be modified by adding an additional diode and resistor.

The 2-diode, 2-resistor network shown also provides

0.25 • I

MAX

when V

OUT

= 0V.

VOUT

VOUT(SS)

V(VC)

250µs/DIV 3800 AI07

VOUT

VOUT(SS)

V(VC)

250µs/DIV 3800 AI08

LT3800

3800f

Adaptive Nonoverlap (NOL) Output Stage

The FET driver output stages implement adaptive

nonoverlap control. This feature maintains a constant

dead time, preventing shoot-through switch currents,

independent of the type, size or operating conditions of the

external switch elements.

Each of the two switch drivers contains a NOL control

circuit, which monitors the output gate drive signal of the

other switch driver. The NOL control circuits interrupt the

“turn on” command to their associated switch driver until

the other switch gate is fully discharged.

Antislope Compensation

Most current mode switching controllers use slope com-

pensation to prevent current mode instability. The LT3800

is no exception. A slope-compensation circuit imposes an

artificial ramp on the sensed current to increase the rising

slope as duty cycle increases. Unfortunately, this addi-

tional ramp corrupts the sensed current value, reducing

the achievable current limit value by the same amount as

the added ramp represents. As such, current limit is

typically reduced as duty cycles increase. The LT3800

contains circuitry to eliminate the current limit reduction

typically associated with slope compensation. As the

slope-compensation ramp is added to the sensed current,

a similar ramp is added to the current limit threshold

reference. The end result is that current limit is not

compromised, so a LT3800 converter can provide full

power regardless of required duty cycle.

APPLICATIO S I FOR ATIO

WUUU

Shutdown

The LT3800 SHDN pin uses a bandgap generated refer-

ence threshold of 1.35V. This precision threshold allows

use of the SHDN pin for both logic-level controlled appli-

cations and analog monitoring applications such as power

supply sequencing.

The LT3800 operational status is primarily controlled by a

UVLO circuit on the V

regulator pin. When the IC is

enabled via the SHDN pin, only the V

regulator is

enabled. Switching remains disabled until the UVLO thresh-

old is achieved at the V

pin, when the remainder of the

IC is enabled and switching commences.

Because an LT3800 controlled converter is a power trans-

fer device, a voltage that is lower than expected on the

input supply could require currents that exceed the sourc-

ing capabilities of that supply, causing the system to lock

up in an undervoltage state. Input supply start-up protec-

tion can be achieved by enabling the SHDN pin using a

resistive divider from the V

supply to ground. Setting the

divider output to 1.35V when that supply is at an adequate

voltage prevents an LT3800 converter from drawing large

currents until the input supply is able to provide the

required power. 120mV of input hysteresis on the SHDN

pin allows for almost 10% of input supply droop before

disabling the converter.

VOUT

1N4148

3800 AI09

47k

VOUT

1N4148

3800 AI10

39k

27k

Current Limit Foldback Circuit for

Applications That Use Soft-Start

Alternative Current Limit Foldback Circuit for Applications That

Have Soft-Start Disabled

LT3800

3800f

The UVLO voltage, V

IN(UVLO)

, is set using the following

relation:

IN UVLO

=•–.

()

135

If additional hysteresis is desired for the enable function,

an external positive feedback resistor can be used from the

LT3800 regulator output.

The shutdown function can be disabled by connecting the

SHDN pin to V

through a large value pull-up resistor.

This pin contains a low impedance clamp at 6V, so the

SHDN pin will sink current from the pull-up resistor (R

IVV

SHDN IN

=–6

Because this arrangement will pull the SHDN pin to the 6V

clamp voltage, it will violate the 5V absolute maximum

voltage rating of the pin. This is permitted, however, as

long as the absolute maximum input current rating of 1mA

is not exceeded. Input SHDN pin currents of <100µA are

recommended; a 1MΩ or greater pull-up resistor is typi-

cally used for this configuration.

Inductor Selection

The primary criterion for inductor value selection in LT3800

applications is ripple current created in that inductor.

Basic design considerations for ripple current are output

voltage ripple, and the ability of the internal slope compen-

sation waveform to prevent current mode instability. Once

the value is determined, an inductor must also have a

saturation current equal to or exceeding the maximum

peak current in the inductor.

Ripple current (∆I

) in an inductor for a given value (L) can

be approximated using the relation:

∆=⎛

⎝

⎜⎞

⎠

⎟

LOUT

OUT

1– • •

The typical range of values for ∆I is 20% to 40% of

OUT(MAX)

, where I

OUT(MAX)

is the maximum converter

output load current. Ripple currents in this range typically

yield a good design compromise between inductor perfor-

mance versus inductor size and cost, and values in this

range are generally a good starting point. A starting point

inductor value can thus be determined using the relation:

OUT

O OUT MAX

⎛

⎝

⎜⎞

⎠

⎟

•

–

•.•

()

Use of smaller inductors increase output ripple currents,

requiring more capacitance on the converter output. Also,

with converter operation with duty cycles greater than

50%, the slope compensation criterion, described later,

must be met. Designing for smaller ripple currents re-

quires larger inductor values, which can increase con-

verter cost and/or footprint.

APPLICATIO S I FOR ATIO

WUUU

Programming LT3800 VIN UVLO

3800 AI02

LT3800

VIN

SHDN

SGND

LT3800

3800f

Some magnetics vendors specify a volt-second product in

their data sheet. If they do not, consult the vendor to make

sure the specification is not being exceeded by your

design. The required volt-second product is calculated as

follows:

Volt f

OUT

- Second V

OUT

≥⎛

⎝

⎜⎞

⎠

⎟

•–1

Magnetics vendors specify either the saturation current,

the RMS current, or both. When selecting an inductor

based on inductor saturation current, the peak current

through the inductor, I

OUT(MAX)

+ (∆I/2), is used. When

selecting an inductor based on RMS current the maximum

load current, I

OUT(MAX)

, is used.

The requirement for avoiding current mode instability is

keeping the rising slope of sensed inductor ripple current

(S1) greater than the falling slope (S2). During continuous-

current switcher operation, the rising slope of the current

waveform in the switched inductor is less than the falling

slope when operating at duty cycles (DC) greater than 50%.

To avoid the instability condition during this operation, a

false signal is added to the sensed current, increasing the

perceived rising slope. To prevent current mode instabil-

ity, the slope of this false signal (Sx) must be sufficient such

that the sensed rising slope exceeds the falling slope, or

S1 + Sx ≥ S2. This leads to the following relations:

Sx ≥ S2 (2DC – 1)/DC

where:

S2 ~ V

OUT

Solving for L yields a relation for the minimum inductance

that will satisfy slope compensation requirements:

LV DC

DC Sx

MIN OUT

=•–

•

The LT3800 maximizes available dynamic range using a

slope compensation generator that continuously increases

the additional signal slope as duty cycle increases. The

slope compensation waveform is calibrated at an 80%

duty cycle, to generate an equivalent slope of at least

• I

LIMIT

A/sec, where I

LIMIT

is the programmed con-

verter current limit. Current limit is programmed by using

a sense resistor (R

) such that I

LIMIT

= 150mV/R

, so the

equation for the minimum inductance to meet the current

mode instability criterion can be reduced to:

MIN

= (5E

–5

)(V

OUT

)(R

)

For example, with V

OUT

= 5V and R

= 20mΩ:

MIN

= (5E

–5

)(5)(0.02) = 5µH

After calculating the minimum inductance value, the volt-

second product, the saturation current and the RMS

current for your design, an off the shelf inductor can be

selected from a magnetics vendor. A list of magnetics

vendors can be found at http://www.linear.com/ezone/

vlinks or by contacting the Linear Technology Applications

department.

Output Voltage Programming

Output voltage is programmed through a resistor feed-

back network to V

(Pin 6) on the LT3800. This pin is the

inverting input of the error amplifier, which is internally

referenced to 1.231V. The divider is ratioed to provide

1.231V at the V

pin when the output is at its desired

value. The output voltage is thus set following the relation:

RR VOUT

1 231 1=⎛

⎝

⎜⎞

⎠

⎟

•.–

when an external resistor divider is connected to the

output as shown.

APPLICATIO S I FOR ATIO

WUUU

Programming LT3800 Output Voltage

3800 AI03

LT3800

OUT

SGND

LT3800

3800f

Power MOSFET Selection

External N-channel MOSFET switches are used with the

LT3800. The positive gate-source drive voltage of the

LT3800 for both switches is roughly equivalent to the V

supply voltage, for use of standard threshold MOSFETs.

Selection criteria for the power MOSFETs include the “ON”

resistance (R

DS(ON)

), total gate charge (Q

), reverse transfer

capacitance (C

RSS

), maximum drain-source voltage (V

DSS

)

and maximum current.

The power FETs selected must have a maximum operating

DSS

exceeding the maximum V

. V

voltage maximum

must exceed the V

supply voltage.

Total gate charge (Q

) is used to determine the FET gate

drive currents required. Q

increases with applied gate

voltage, so the Q

for the maximum applied gate voltage

must be used. A graph of Q

vs. V

is typically provided

in MOSFET datasheets.

In a configuration where the LT3800 linear regulator is

providing V

and V

BOOST

currents, the V

8V output

voltage can be used to determine Q

. Required drive

current for a given FET follows the simple relation:

GATE

= Q

G(8V)

• f

G(8V)

is the total FET gate charge for V

= 8V, and f

operating frequency. If these currents are externally de-

rived by backdriving V

, use the backfeed voltage to

determine Q

. Be aware, however, that even in a backfeed

configuration, the drive currents for both boosted and

synchronous FETs are still typically supplied by the LT3800

internal V

regulator during start-up. The LT3800 can

start using FETs with a combined Q

G(8V)

up to 180nC.

Once voltage requirements have been determined, R

DS(ON)

can be selected based on allowable power dissipation and

required output current.

In an LT3800 buck converter, the average inductor current

is equal to the DC load current. The average currents

through the main (bootstrapped) and synchronous

(ground-referred) switches are:

MAIN

= (I

LOAD

)(DC)

SYNC

= (I

LOAD

)(1 – DC)

The R

DS(ON)

required for a given conduction loss can be

calculated using the relation:

LOSS

= I

SWITCH2

• R

DS(ON)

In high voltage applications (V

> 20V), the main switch

is required to slew very large voltages. MOSFET transition

losses are proportional to V

IN2

and can become the

dominant power loss term in the main switch. This transi-

tion loss takes the form:

≈ (k)(V

)

SWITCH

)(C

RSS

)(f

)

where k is a constant inversely related to the gate drive

current, approximated by k = 2 in LT3800 applications,

and I

SWITCH

is the converter output current. The power

loss terms for the switches are thus:

MAIN

= (DC)(I

SWITCH

)

(1 + d)(R

DS(ON)

) +

2(V

)

SWITCH

)(C

RSS

)(f

)

SYNC

= (1 – DC)(I

SWITCH

)

(1 + d)(R

DS(ON)

)

The (1 + d) term in the above relations is the temperature

dependency of R

DS(ON)

, typically given in the form of a

normalized R

DS(ON)

vs Temperature curve in a MOSFET

data sheet.

The C

RSS

term is typically smaller for higher voltage FETs,

and it is often advantageous to use a FET with a higher V

rating to minimize transition losses at the expense of

additional R

DS(ON)

losses.

In some applications, parasitic FET capacitances couple

the negative going switch node transient onto the bottom

gate drive pin of the LT3800, causing a negative voltage in

excess of the Absolute Maximum Rating to be imposed on

that pin. Connection of a catch Schottky diode from this

pin to ground will eliminate this effect. A 1A current rating

is typically sufficient for the diode.

APPLICATIO S I FOR ATIO

WUUU

LT3800

3800f

Input Capacitor Selection

The large currents typical of LT3800 applications require

special consideration for the converter input and output

supply decoupling capacitors. Under normal steady state

buck operation, the source current of the main switch

MOSFET is a square wave of duty cycle V

OUT

. Most of

this current is provided by the input bypass capacitor. To

prevent large input voltage transients and avoid bypass

capacitor heating, a low ESR input capacitor sized for the

maximum RMS current must be used. This maximum

capacitor RMS current follows the relation:

IIVVV

RMS

MAX OUT IN OUT

()

–2

which peaks at a 50% duty cycle, when I

RMS

= I

MAX

/2.

The bulk capacitance is calculated based on an acceptable

maximum input ripple voltage, ∆V

, which follows the

relation:

IN BULK OUT MAX

OUT

IN O

() ()

••

=∆

∆V is typically on the order of 100mV to 200mV. Alumi-

num electrolytic capacitors are a good choice for high

voltage, bulk capacitance due to their high capacitance per

unit area.

The capacitor voltage rating must be rated greater than

IN(MAX)

. The combination of aluminum electrolytic ca-

pacitors and ceramic capacitors is a common approach to

meeting supply input capacitor requirements. Multiple

capacitors are also commonly paralleled to meet size or

height requirements in a design.

Capacitor ripple current ratings are often based on only

2000 hours (three months) lifetime; it is advisable to

derate either the ESR or temperature rating of the capaci-

tor for increased MTBF of the regulator.

Output Capacitor Selection

The output capacitor in a buck converter generally has

much less ripple current than the input capacitor. Peak-to-

peak ripple current is equal to that in the inductor (∆I

typically a fraction of the load current. C

OUT

is selected to

reduce output voltage ripple to a desirable value given an

expected output ripple current. Output ripple (∆V

OUT

) is

approximated by:

∆V

OUT

≈ ∆I

(ESR + [(8)(f

) • C

OUT

]

–1

)

where f

= operating frequency.

∆V

OUT

increases with input voltage, so the maximum

operating input voltage should be used for worst-case

calculations. Multiple capacitors are often paralleled to

meet ESR requirements. Typically, once the ESR require-

ment is satisfied, the capacitance is adequate for filtering

and has the required RMS current rating. An additional

ceramic capacitor in parallel is commonly used to reduce

the effect of parasitic inductance in the output capacitor,

which reduces high frequency switching noise on the

converter output.

Increasing inductance is an option to reduce ESR require-

ments. For extremely low ∆VOUT, an additional LC filter

stage can be added to the output of the supply. Applica-

tion Note 44 has information on sizing an additional

output LC filter.

Layout Considerations

The LT3800 is typically used in DC/DC converter designs

that involve substantial switching transients. The switch

drivers on the IC are designed to drive large capacitances

and, as such, generate significant transient currents them-

selves. Careful consideration must be made regarding

supply bypass capacitor locations to avoid corrupting the

ground reference used by IC.

Typically, high current paths and transients from the input

supply and any local drive supplies must be kept isolated

from SGND, to which sensitive circuits such as the error

amp reference and the current sense circuits are referred.

APPLICATIO S I FOR ATIO

WUUU

LT3800

3800f

Effective grounding can be achieved by considering switch

current in the ground plane, and the return current paths

of each respective bypass capacitor. The V

bypass

return, V

bypass return, and the source of the synchro-

nous FET carry PGND currents. SGND originates at the

negative terminal of the V

OUT

bypass capacitor, and is the

small signal reference for the LT3800.

Don’t be tempted to run small traces to separate ground

paths. A good ground plane is important as always, but

PGND referred bypass elements must be oriented such

that transient currents in these return paths do not

corrupt the SGND reference.

During the dead-time between switch conduction, the

body diode of the synchronous FET conducts inductor

current. Commutating this diode requires a significant

charge contribution from the main switch. At the instant

the body diode commutates, a current discontinuity is

created and parasitic inductance causes the switch node

to fly up in response to this discontinuity. High currents

and excessive parasitic inductance can generate extremely

fast dV/dt rise times. This phenomenon can cause

avalanche breakdown in the synchronous FET body di-

ode, significant inductive overshoot on the switch node,

and shoot-through currents via parasitic turn-on of the

synchronous FET. Layout practices and component ori-

entations that minimize parasitic inductance on this node

is critical for reducing these effects.

Ringing waveforms in a converter circuit can lead to

device failure, excessive EMI, or instability. In many cases,

you can damp a ringing waveform with a series RC

network across the offending device. In LT3800 applica-

tions, any ringing will typically occur on the switch node,

which can usually be reduced by placing a snubber across

the synchronous FET. Use of a snubber network, however,

should be considered a last resort. Effective layout prac-

tices typically reduce ringing and overshoot, and will

eliminate the need for such solutions.

Effective grounding techniques are critical for successful

DC/DC converter layouts. Orient power path components

such that current paths in the ground plane do not cross

through signal ground areas. Signal ground refers to the

Exposed Pad on the backside of the LT3800 IC. SGND is

referenced to the (–) terminal of the V

OUT

decoupling

capacitor and is used as the converter voltage feedback

reference. Power ground currents are controlled on the

LT3800 via the PGND pin, and this ground references the

high current synchronous switch drive components, as

well as the local V

supply. It is important to keep PGND

and SGND voltages consistent with each other, so sepa-

rating these grounds with thin traces is not recommended.

When the synchronous FET is turned on, gate drive surge

currents return to the LT3800 PGND pin from the FET

source. The BOOST supply refresh surge currents also

return through this same path. The synchronous FET must

be oriented such that these PGND return currents do not

corrupt the SGND reference. Problems caused by the

PGND return path are generally recognized during heavy

load conditions, and are typically evidenced as multiple

switch pulses occurring during a single 5µs switch cycle.

This behavior indicates that SGND is being corrupted and

grounding should be improved. SGND corruption can

often be eliminated, however, by adding a small capacitor

(100pF-200pF) across the synchronous switch FET from

drain to source.

The high di/dt loop formed by the switch MOSFETs and the

input capacitor (C

) should have short wide traces to

minimize high frequency noise and voltage stress from

inductive ringing. Surface mount components are pre-

ferred to reduce parasitic inductances from component

leads. Connect the drain of the main switch MOSFET

directly to the (+) plate of C

, and connect the source of

the synchronous switch MOSFET directly to the (–) termi-

nal of C

. This capacitor provides the AC current to the

switch MOSFETs. Switch path currents can be controlled

by orienting switch FETs, the switched inductor, and input

and output decoupling capacitors in close proximity to

each other.

Locate the V

and BOOST decoupling capacitors in close

proximity to the IC. These capacitors carry the MOSFET

APPLICATIO S I FOR ATIO

WUUU

LT3800

3800f

BOOST

PGNDSGND

LT3800

SGND

REFERRED

COMPONENTS

OUT

3800 AI05

SENSE

Orientation of Components Isolates Power Path and PGND Currents,

Preventing Corruption of SGND Reference

drivers’ high peak currents. Locate the small-signal com-

ponents away from high frequency switching nodes

(BOOST, SW, TG, V

and BG). Small-signal nodes are

oriented on the left side of the LT3800, while high current

switching nodes are oriented on the right side of the IC to

simplify layout. This also helps prevent corruption of the

SGND reference.

Connect the V

pin directly to the feedback resistors in-

dependent of any other nodes, such as the SENSE

–

pin.

The feedback resistors should be connected between the

(+) and (–) terminals of the output capacitor (C

OUT

Locate the feedback resistors in close proximity to the

LT3800 to minimize the length of the high impedance V

node.

The SENSE– and SENSE+ traces should be routed to-

gether and kept as short as possible.

The LT3800 packaging has been designed to efficiently

remove heat from the IC via the Exposed Pad on the

backside of the package. The Exposed Pad is soldered to

a copper footprint on the PCB. This footprint should be

made as large as possible to reduce the thermal resistance

of the IC case to ambient air.

APPLICATIO S I FOR ATIO

WUUU

LT3800

3800f

TYPICAL APPLICATIO S

6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler VCC Refresh and Current Limit Foldback

SHDN

BURST_EN

SENSE

–

BOOST

PGND

SENSE

LT3800

SGND

1.5nF

62k R5

47k

1N4148

R4 75k

470pF

C10

100pF

309k

100k

0.01Ω

BAS19

C1 1µF

16V X7R

C3 1µF

16V X7R

1µF

100V

X7R ×3

56µF

63V

×2

10µF

6.3V

X7R

220µF

×2

Si7850DP

×2

Si7370DP

×2

1/2 Si1555DL

DS3

B160

×2

DS1

MBRO520L

1µF

DS2

MBRO520L

5.6µH

6.5V TO 55V

OUT

5V AT 10A

3800 TA02a

C5: SANYO POSCAP 6TP220M

L1: IHLP-5050FD-01

OUT

(A)

EFFICIENCY (%)

POWER LOSS (W)

100

2468

3800 TA02b

= 13.8V

= 55V

= 24V

= 48V

POWER LOSS

= 48V

POWER LOSS

= 13.8V

Efficiency and Power Loss

LT3800

3800f

TYPICAL APPLICATIO S

9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode Operation

No Load I(VIN) = 100µA

Efficiency and Power Loss

SHDN

BURST_EN

SENSE

–

BOOST

PGND

SENSE

LT3800

SGND

C1 1nF

100pF

330pF

C10

100pF

169k

100k

R4 39k

82k

187k

0.01Ω

MBR520

C5 1µF

16V X7R

C4 1µF

16V X7R

4.7µF

50V

X7R ×3

100µF

50V

×2

10µF

6.3V

X7R

470µF

×2

Si7884DP

DS1

SS14

×2

3.3µH

9V TO 38V

OUT

3.3V AT 10A

3800 TA03a

C6: SANYO POSCAP 4TPD470M

L1: IHLP-5050FD-01

ILOAD (A)

3800 TA03b

EFFICIENCY (%)

POWER LOSS (W)

0.1 10

VIN = 13.8V

LT3800

3800f

TYPICAL APPLICATIO S

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

C1 3.9nF

C9 1nF

100pF

1nF

47pF

154k

49.9k

47k

1N4148

R4 51k

27k

RB 187k

0.02Ω

BAS19

C5 1µF

10V X7R

C4 1µF

10V X7R

22µF

×3

100µF

×2

Si7884DP

DS1

SS14

10µH

VIN

9V TO 38V

VOUT

5V AT 6A

3800 TA05a

C7: TDK C4532X5R0J107MT

C8: TDK C5750X7R1E226MT

L1: IHLP-5050FD-01

9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO,

Burst Mode Operation and Current Limit Foldback

Efficiency and Power Loss

LOAD

(A)

EFFICIENCY (%)

POWER LOSS (W)

100

0.001 0.1 1 10

3800 TA05b

0.01

0.80

1.60

2.00

2.80

3.20

2.40

1.20

0.40

= 13.8V

LT3800

3800f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

PACKAGE DESCRIPTIO

FE16 (BC) TSSOP 0204

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678

10 9

4.90 – 5.10*

(.193 – .201)

16 1514 13 12 11

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC

2.94

(.116)

0.195 – 0.30

(.0077 – .0118)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

2.94

(.116)

3.58

(.141)

3.58

(.141)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

LT3800

3800f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●

www.linear.com

LT/TP 0305 1K • PRINTED IN USA

24V-48V to –12V 75W Inverting DC/DC Converter with VIN UVLO

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1735 Synchronous Step-Down Controller 4V ≤ V

≤ 36V, 0.8V ≤ V

OUT

≤ 6V, I

OUT

≤ 20A

LTC1778 No R

SENSE

TM Synchronous Step-Down Controller Current Mode Without Using Sense Resistor, 4V ≤ V

≤ 36V

LT®1934 Micropower Step-Down Switching Regulator 3.2V ≤ V

≤ 34V, 300mA Switch, ThinSOTTM Package

LT1952 Synchronous Single Switch Forward Converter 25W to 500W Isolated Power Supplies, Small Size, High Efficiency

LT1976 60V Switching Regulator 3.2V ≤ V

≤ 60V, 1.5A Switch, 16-Lead TSSOP

LT3010 3V to 80V LDO 50mA Output Current, 1.275V ≤ V

OUT

≤ 60V

LT3430/LT3431 3A, 60V Switching Regulators 5.5V ≤ V

≤ 60V, 200kHz, 16-Lead TSSOP

LTC3703 100V Synchronous Step-Down Controller Large 1Ω Gate Drivers, No R

SENSE

LTC3703-5 60V Synchronous Step-Down Controller Large 1Ω Gate Drivers, No R

SENSE

LTC3727-1 High V

OUT

2-Phase Dual Step-Down Controller 0.8V ≤ V

OUT

≤ 14V, PLL: 250kHz to 550kHz

LTC3728L 2-Phase, Dual Synchronous Step-Down Controller 550kHz, PLL: 250kHz to 550kHz, 4V ≤ V

≤ 36V

No R

SENSE

and ThinSOT are trademarks of Linear Technology Corporation.

VIN

SHDN

CSS

BURST_EN

VFB

SENSE–

BOOST

VCC

PGND

SENSE+

LT3800

SGND

C1 1nF R1 200k

470pF

130k

39k

20k

174k

C2 1µF

16V X7R

100pF

4.7µF

16V

X7R

270µF

16V

SPRAGUE SP

150pF

100V

1N4148

BAS19

56µF

63V

×2

C10

1µF

100V

X7R

×4

1µF

16V

X7R

FDD3570

L1: COEV MGPWL-00099

VIN

24V TO 48V

VOUT

–12V

75W

0.01Ω

15µH

DS1

B180

2N3906

3800 TA04a

ILOAD (A)

0.1

EFFICIENCY (%)

POWER LOSS (W)

100

110

3800 TA04b

VIN = 24V

VIN = 48V

VIN = 36V LOSS

VIN = 36V

Efficiency and Power Loss

TYPICAL APPLICATIO