Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
Description
The Atmel® | SMART SAM G55 is a series of Flash microco ntrollers based on the
high-perfor mance 32-bit ARM® Cortex®-M4 RISC processor with FPU (Floating
Point Unit). It operates at a maximum speed of 120 MHz and features 512 Kbytes
of Flash and up to 176 Kbytes of SRAM. The peripheral set inc lud e s eig h t fle xib le
communication units comprising USARTs, SPIs and I2C-bus interfaces (TWIs),
two three-channel general-purpose 16-bit timers, two I2S controllers, one-channel
pulse density modulation, one 8-ch annel 12-bit ADC, one re al-time timer (RTT)
and one real-time clock (RTC), both located in the ultra low-power backup area.
The Atmel | SMART SAM G55 devic es have thre e softwar e-selec table lo w-power
modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while
all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on
events, including partial asynchronous wakeup (SleepWalking™). In Backup
mode, RTT, RTC and wakeup logic are running.
For power consumption optimization, the flexible clock system offers the capability
of having different clock frequencies for some peripherals. Moreover, the
processor and bus clock frequency can be modified without affecting the
peripheral processing.
The real-time event management allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM G55 devices are general-purpose low-power microcontrollers that offer
high perfo rmance, pr ocessing power and small packa ge options c ombined with a
rich and flexible peripheral set. With this unique combination of features, the SAM
G55 series is suitable for a wide range of applications including consumer,
industrial control and PC peripherals.
The device operates from 1.62V to 3.6V and is available in three packages:
49-pin WLCSP, 64-pin QFN and 64-pin LQFP.
SAM G55G / SAM G55J
Atmel | SMART ARM-based Flash MCU
DATASHEET
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
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Features
Core
ARM Cortex-M4 with up to 16 Kbytes SRAM on I/D bus providing 0 wait state execution at up to
120 MHz (1)
Memory Protection Unit (MPU)
DSP Instructions
Floating Point Unit (FPU)
Thumb®-2 instruction set
Note: 1. 120 MHz with VDDCOREXT120 or with VDDCORE trimmed by regulator.
Memories
Up to 512 Kbytes embedded Flash
Up to 176 Kbytes embedded SRAM
8 Kbytes ROM with embedded boot loader, single-cycle access at full speed
System
Embedded voltage regulator for single-supply operation
Power-on reset (POR) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz with clock failure detection and 32.768 kHz for
RTT or system clock
High-precision 8/16/24 MHz factory-trimmed internal RC oscillator. In-application trimming access for
frequency adjustment
Slow clock internal RC oscillator as permanent low-power mode device clock
PLL range from 48 MHz to 120 MHz for device clock
PLL range from 24 MHz to 48 MHz for USB device and USB OHCI
Up to 30 peripheral DMA (PDC) channels
256-bit General-Purpose Backup Registers (GPBR)
16 external interrupt lines
Peripherals
8 flexible communication units supporting:
USART
SPI
Two-wire Interface (TWI) featuring TWI masters and high-speed TWI slaves
Crystal-less USB 2.0 Device and USB Host OHCI with On-chip Transceiver
2 Inter-IC Sound Controllers (I2S)
1 Pulse Density Modulation Interface (PDMIC) (supports up to two microphones)
2 three-channel 16-bit Timer/Counters (TC) with capture, waveform, compare and PWM modes
1 48-bit Real-Time Timer (RTT) with 16-bit prescale r and 32-bit counter
1 RTC with calendar and alarm features
1 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
I/O
Up to 48 I/O lines with external interrupt capability (edge or level), debouncing, glitch filtering and on-
die series resistor termination. Individually programmable open-dra in, pull-up and pull-down resistor
and synchronous output
Two PIO Controllers provide control of up to 48 I/O lines
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
Analog
One 8-channel ADC, resolution up to 12 bits, sampling rate up to 500 ksps
Package
49-lead WLCSP
64-lead LQFP
64-lead QFN
Operating Temperature Range
Industrial (-40°C to +85°C)
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
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1. Configuration Summary
Table 1-1 summarizes the SAM G55 device configurations.
Table 1-1. Configuration Summary
Feature SAM G55G19 SAM G55J19
Flash 512 Kbytes 512 Kbytes
Cache (CMCC) up to 8 Kbytes up to 8 Kbytes
SRAM 160 Kbytes
+ up to 16 Kbytes (Cache + I/D RAM) 160 Kbytes
+ up to 16 Kbytes (Cache + I/D RAM)
Package WLCSP49 QFN64, LQFP64
Number of PIOs 38 48
Event System Yes Yes
External Interrupt 16 16
12-bit ADC 8 channels
Performance: 500 kSps 8 channels
Performance: 500 kS ps
16-bit Timer 6 channels
(3 external channels) 6 channels
(3 external channels)
I2SC/PDM 2 / 1-channel 2-way 2 / 1-channel 2-way
PDC Channels 28 30
USART
78SPI
TWI
USB Full Speed / OHCI Full Speed / OHCI
CRCCU 1 1
RTT 1 (backup area) 1 (backup area)
RTC 1 (backup area) 1 (backup area)
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
2. Block Diagram
Figure 2-1. SAM G55 Block Diagram
ID
AHB/APB
Bridge
PCK[2:0]
XIN32
XOUT32
ERASE
VDDCORE
ADTRG
System Controller
TCK/SWCLK
TDI
TDO
JTAGSEL
VDDIO
VDDOUT
JTAG and Serial Wire
Flash
Unique
Identifier
Voltage
Regulator
TST
12-bit ADC
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
USB 2.0
Full-speed
In-Circuit Emulator
MPU
Cortex-M4 Processor
f
MAX
120 MHz
NVIC 24-bit SysTick
Counter
DSP
Flash
512 Kbytes
DP
DM
PDC
User
Signature
WKUP[15:0]
FPU
MUX
Transceiver
VDDIO
XIN
XOUT
VDDUSB
(64-pin package only)
NRST
AD[7:0]
PIOA/PIOB
TMS/SWDIO
PDC
Timer Counter A
TC[0..2]
Timer Counter B
TC[3..5]
SRAM
160 Kbytes
ROM
8 Kbytes
Event System
S
SRAM
Up to 16 Kbytes
Watchdog
Timer
PLLA
Power
Management
Controller
RC OSC
8/16/24 MHz
PLLUSB
CMCC
2/4/8 KB Cache
CRCCU
8 x
USART, SPI, TWI
PDC
2668
bytes
FIFO
Supply
Monitor
USB OHCI
I2SDI0...1
I2SWS0...1
I2SCK0...1
I2SDO0...1
I2SMCK0...1
2 x I2SC
PDC
PDMIC_CLK
PDMIC_DAT
PDMIC0
PDC
PDMIC1
PDC
DMA
Backup area
Power-on
Reset
32K OSC
32K RC
Supply
Controller
Real-time
Timer
Real-time
Clock
Tamper Detection
RXD_MISO_TWCK0...7
TXD_MOSI_TWD0...7
SCK_SPCK0...7
RTS_NPCS1_0...7
CTS_NPCS0NSS_0...7
FLEXCOM
Reset
Controller
256-bit
General-purpose
Backup Registers
4-layer AHB Bus Matrix
fMAX 120 MHz
S
S
S
S
M
MM
M
M
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
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3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Voltage
Reference Comments
Power Supplies
VDDIO Peripheral I/O Lines, Voltage Regulator,
ADC Power Supply Power – – 1.62V to 3.6V
VDDOUT Voltage Regulator Output Power – – 1.08V to 1.32V
VDDCORE Core Chip Power Supply Power – – Connected externally to
VDDOUT or VDDCOREXT100 or
VDDCOREXT120
VDDUSB USB Power Supply Power – – Only available on 64-pin
package
GND Ground Ground – – –
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input – VDDIO Reset state:
- PIO input
- Internal pul l- up disa bl e d
- Schmitt Trigger enabled
XOUT Main Oscillator Output Output – –
XIN32 Slow Clock Oscillator Input Input – VDDIO
XOUT32 Slow Clock Oscillator Output Output – –
PCK0–PCK2 Programmable Clock Output Output – –
Reset state:
- PIO input
- Internal pull-up enabled
- Schmitt Trigger enabled
ICE and JTAG
TCK Test Clock Input – VDDIO No pull-up resistor
TDI Test Data In Input – VDDIO No pull-up resistor
TDO Test Data Out Output – VDDIO –
TRACESWO Trace Asynchronous Data Out Output – VDDIO –
SWDIO Serial Wire Input/Output I/O – VDDIO –
SWCLK Serial Wire Clock Input – VDDIO –
TMS Test Mode Select Input – VDDIO No pull-up resistor
JTAGSEL JTAG Selection Input High VDDIO Pull-down resistor
Flash Memory
ERASE Flash and NVM Configuration Bits Erase
Command Input High VDDIO Pull-down (15 kΩ) resistor
Reset/Test
NRST Microcontroller Reset I/O Low VDDIO Pull-up resistor
TST Test Mode Select Input – VDDIO Pull-down resistor
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
PIO Controller - PIOA - PIOB
PA0–PA3 1 Parallel I/O Controller A I/O – VDDIO Pulled-up input at reset. No
pull-down for PA3/PA4/PA14
PB0–PB15(1) Parallel I/O Controller B I/O – VDDIO Pulled-up input at reset
Wakeup Pins
WKUP0–15 Wakeup Pin / External Interrupt I/O – VDDIO Wakeup pins are used also
as External Interrupt
Serial Peripheral Interface - SPIx
MISOx Master In Slave Out I/O – – –
MOSIx Master Out Slave In I/O – – –
SPCKx SPI Serial Clock I/O – – High Speed Pad
NPCS0x SPI Peripheral Chip Select 0 I/O Low – –
NPCS1x SPI Peripheral Chip Select Output Low – –
Two-Wire Interface - TWIx
TWDx TWIx Two-wire Serial Data I/O – – High Sp eed Pad for TWD0
TWCKx TWIx Two-wire Serial Clock I/O – – High Speed Pad for
TWDCK0
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USART Serial Clock I/O – – –
TXDx USART Transmit Data I/O – – –
RXDx USART Receive Data Input – – –
RTSx USART Request To Send Output – – –
CTSx USART Clear To Send Input – – –
Timer/Counter - TCx
TCLKx TC Channel x External Clock Input Input – – –
TIOAx TC Channel x I/O Line A I/O – – –
TIOBx TC Channel x I/O Line B I/O – – –
12-bit Analog-to-Digital Converter - ADC
AD0–AD7 Analog Inputs Ana lo g – – –
ADTRG ADC Trigger Input – – –
ADVREF ADC Voltage Reference Input – – Only available on 64-pin
package
Inter-IC Sound Controller - I2SCx
I2SMCKx Master Clock Output – – –
I2SCKx Serial Clock I/O – – –
I2SWSx I2S Word Select I/O – – –
I2SDIx Serial Data Input Input – – –
I2SDOx Serial Data Output Output – – –
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
8
Note: 1. Pull-up disabled on PB8/PB9.
Pulse Density Modulation Interface Co ntro ller - PDMICx
PDMIC_CLK Pulse Density Modulation Clock Output – – –
PDMIC_DAT Pulse Densi ty Modulation Data Input – – –
USB OHCI/FS - USB
DM USB Data -
Analog, Digital –
WLCSP49:
VDDIO
64-pin
package:
VDDUSB
DM and DP in PIO
configuration
DP USB Data +
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
Reference Comments
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
4. Package and Pinout
4.1 49-ball WLCSP Pinout
Table 4-1. SAM G55 Packages
Device Package
SAM G55G19 WLCSP49
SAM G55J19 QFN64
LQFP64
Table 4-2. SAM G55G19 49-ball WLCSP Pinout
A1 PA9 B6 NRST D4 PB10 F2 PA19/AD2
A2 GND B7 PB12 D5 PA1 F3 PA17/AD0
A3 PA24 C1 VDDCORE D6 PA5 F4 PA21
A4 PB8/XOUT C2 PA11 D7 VDDCORE F5 PA23
A5 PB9/XIN C3 PA12 E1 PB2/AD6 F6 PA16
A6 PB4 C4 PB6 E2 PB0/AD4 F7 PA8/XOUT32
A7 VDDIO C5 PA4 E3 PA18/AD1 G1 VDDIO
B1 PB11 C6 PA3 E4 PA14 G2 VDDOUT
B2 PB5 C7 PA0 E5 PA10 G3 GND
B3 PB7 D1 PA13 E6 TST G4 VDDIO
B4 PA2 D2 PB3/AD7 E7 PA7/XIN32 G5 PA22
B5 JTAGSEL D3 PB1/AD5 F1 PA20/AD3 G6 PA15
G7 PA6
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
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4.2 64-lead QFN/LQFP Pinout
4.2.1 64-lead QFN / LQFP Pinout
Note: 1. The bottom pad of the QFN package must be tied to ground.
Table 4-3. SAM G55J19 64-pin LQFP and QFN Pinout
1 VDDIO 17 PA6 33 PA17 49 PA9
2 NRST 18 PA16 34 PA18 50 PB5
3 PB12 19 PA30 35 PA19 51 PA27
4 PA4 20 PA29 36 PA20 52 PA26
5 PA3 21 PA28 37 PB0 53 GND
6 PA0 22 PA15 38 PB1 54 PB6
7 PA1 23 PA23 39 PB2 55 PB7
8 PA5 24 PA22 40 PB3 56 PA25
9 VDDCORE 25 PA21 41 PA14 57 PB13
10 TEST 26 VDDUSB 42 PA13 58 PA24
11 PA7 27 VDDIO 43 PA12 59 PB8/XOUT
12 PA8 28 ADVREF 44 PA11 60 PB9/XIN
13 GND 29 GND 45 VDDCORE 61 PA2
14 PB15 30 VDDOUT 46 PB10 62 PB4
15 PB14 31 VDDIO 47 PB11 63 JTAGSEL
16 PA31 32 VDDIO 48 PA10 64 VDDIO
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
5. Power Considerations
5.1 Power Supplies
The SAM G55 has the following power supply pins:
VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals,
except the RTC, R T T, and Supply controller (SUPC). It is recommended to connect VDDCORE to VDDOUT.
VDDIO pins: Power the peripheral I/O lines, RTC, RTT, and SUPC peripherals, voltage regulator and ADC;
voltage ranges from 1.62V to 3.6V.
VDDUSB pins: Power the USB (only for devices with 64-pin package), volt age ranges from 3.0V to 3.6V.
The ground pins GND are common to VDDCORE and VDDIO.
5.2 Powerup Considerations
In order to prevent any overcurrent at powerup, it is recommended to connect pin ADVREF to VDDIO, or to get
ADVREF to rise as much as possible at the same time as VDDIO.
Note: Pin ADVREF is only available on 64-pin packages QFN and LQFP.
5.2.1 VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCOREXT(min). The
minimum slope for VDDCORE is defined by (VDDCOREXT(min) - VTH+) / tRES.
If VDDCOREXT rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 7V/ms.
If VDDCORE is powered by the internal regulator, all powerup considerations are met.
Figure 5-1. VDDCORE and VDDIO Constraints at Startup
At powerdown, there is no constraint on VDDCORE and VDDIO as the regulator must be enabled.
Supply (V)
Time (t)
t
RES
VDDIO
VTH+
VDDCORE
VDDIO(min)
VDDCORE(min)
Core supply POR output
SLCK
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
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5.3 Voltage Regulator
The SAM G55 embeds a core voltage regulator that is managed by the Supply Controll er and that supplies the
Cortex-M4 core, internal memories (SRAM, ROM and Flash logic) and the peripherals. An internal adaptive
biasing adjusts the regulator quiescent current depending on the required load current.
For adequate input and output power supply decoupling/bypassing, refer to Table 39-4 “VDDCORE Voltage
Regulator Characteristics” in section “Electrical Characteristics”.
In case of dual supply, the voltage regulator must be enabled and VDDOUT must be used as input control of the
external DC/DC. This will allow a correct slope at first startup and for low power mode.
5.4 Typical Powering Schematics
The SAM G55 supports single and dual voltage supply, with VDDIO from 1.62V to 3.6V and VDDCORE from
external DC/DC controlled by the internal regulator. Figure 5-2 and Figure 5-3 illustrate the power schematics.
To achieve system performances, the internal voltage regulator must be used.
5.4.1 Single Supply
The SAM G55 supports a 1 .62V to 3.6V single supply mode. The internal voltage regulator input is connected to
the source and its output feeds VDDCORE. Figure 5-2 illustrates the power schematics.
Figure 5-2. Single Supply
VDDIO
Voltage
Regulator
VDDOUT
Main Supply (1.62V–3.6V)
VDDCORE
(3.0V–3.6V)
VDDUSB
(only on 64-pin
packages)
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
5.4.2 Dual Supply
In dual voltage supply, the voltage regulator must always be enabled and must be used as input control of the
external DC/DC, to control the slope of VDDCORE after low power mode.
Figure 5-3. Dual Supply
In Wait mode, by default, the voltage regulator is down to VDDOUT Wait mode minimum value. Consequently, it
must be configured to keep VDDOUT in Running mode. To avoid any issue, the regulator must be configured by
software to deliver the correct supply voltage. To do this, use the following procedure:
Read the unique identifier bytes [65..64]
Write the four LSB bits of unique identifier bytes [65..64] in SUPC_PWMR.LPO W ER 0– LP OWER3
Enable SUPC_PWMR.LPOWERS
VDDIO
Voltage
Regulator
VDDOUT
VDDCORE
(3.0V–3.6V)
DC/DC
VIN
VOUT
ENA
VDDUSB
(only on 64-pin
packages)
1.2V
Main Supply
(1.62V–3.6V)
SAM G55 [DATASHEET]
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5.5 Functional Modes
5.5.1 Active Mode
Active Mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLL. The power management controll er can be used to adapt the frequency and to disable the
peripheral clocks.
5.5.2 Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is
performing periodic wakeups to perform tasks but not requiring fast startup time.
The zero-power power-on reset, SUPC, RTT, RTC, general-purpose backup registers (GPBR) and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the
core supply are off.
The SAMG55 can be awakened from this mode using the pins WKUP0–15, the supply monitor (SM), the RTT, or
the RTC.
Backup mode is entered by writing a 1 to the VROFF bit of the Supply Controller Control Register (SUPC_CR) (a
key is needed to write the VROFF bit, refer to section Supply Controller SUPC) and with the SLEEPDEEP bit in the
Cortex-M4 System Control Register set to 1 (see power m anagement description in section ARM Cortex-M4
Processor). To reduce consumption, the supply monitor on VDDIO can be disabled.
To enter Backup mode using the VROFF bit:
Write a 1 to the VROFF bit of SUPC_CR.
To enter Backup mode using the WFE instruction:
Write a 1 to the SLEEPDEEP bit of the Cortex-M4 processor.
Execute the WFE instruction of the processor.
In both cases, exit from Backup mode happens if one of the following enable wake up even ts occurs:
Pins WKUPEN0–15 (level tr ansition, configurable debouncing)
Supply Monitor alarm
RTC alarm
RTT alarm
5.5.3 Wait Mode
Wait mode allows the device to achieve very low power consumption levels while remaining in a powered state
with a wakeup time of less than a few µs. In Wait mode, the clocks of the core, the peripherals and memories are
stopped. However, power supplies are maintained to ensure memory and CPU context retention.
The wakeup time is achieved when entry into and exit from Wait mode are performed in internal SRAM. The
wakeup time increases to 6.9 µs if entry into Wakeup mode is performed in internal Flash.
Wait mode is entered using either the WAITMODE bit in the PMC Clock Generator Main Oscillator register
(CKGR_MOR) or the Wait for Event (WFE) instruction. Before entering Wait mode, the POR core must be
disabled. Detailed sequences are provided below.
Note that the WFE instruction can add complexity in application state machines due to the fact that the WFE
instruction go es alo n g w i th an e v ent fla g of th e Cortex core (cannot be managed by the software application). The
event flag can be set by interrupts, a debug event or an event signal from another processor. Since an interrupt
can take place just before the execution of WFE, WFE takes into account events that happened in the past. As a
result, WFE prevents the device from entering Wait mode if an interrupt event has occurred. To work around this
complexity, follow the sequence using the WAITMODE bit described below.
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SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
The Cortex-M4 proce ssor is able to han dle external or in tern al events in order to wake up the core. This is done by
configuring the ext ernal lines WKUP0–15 as fast startup wakeup p ins (refer to Section 5.6 “Fast Sta rtup”) or the
RTT and RTC alarms, USB in terrup t line or Slee pWalking for FLEXCOM0–7 (USART/SPI/TWI) for internal events.
To enter Wait mode using the WAITMODE bit:
1. Select the 8/16/24 MHz fast RC oscillator as the Main Clock. If frequency of 24 MHz is selected and the code
is running from the SRAM.
2. Program the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)(1).
3. Set the number of Flash wait states to 1 by writing a one to the FWS field in the EEFC Flash Mode Register
(EEFC_MR).
4. Write a one to the WAITMODE bit in the CKGR_MOR.
5. Wait for MCKRDY = 1 in the PMC Status Register (PMC_SR).
To enter Wait mode using the WFE instruction:
1. Select the 8/16/24 MHz fast RC oscillator as the Main Clock. If 24 MHz is selected and the code is running
on the SRAM.
2. Program the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)(1).
3. Set the number of Flash wait states to 1 by writing a one to the FWS field in the EEFC Flash Mode Register
(EEFC_MR).
4. Write a one to the LPM bit in PMC_FSMR.
5. Execute the Wait For Event (WFE) instruction of the processor.
Note: 1. Depending on the value of the field FLPM, the Flash enters on of three different modes:
FLPM = 0: Flash in Standby mode (low power consumption levels)
FLPM = 1: Flash in Deep-powerdown mode (extra low powe r con s umption levels)
FLPM = 2: Flash in Idle mode. Memory ready for Read access.
5.5.4 Sleep Mode
In Sleep mode, power consumption of the device versus response time is optimized. Only the core clock is
stopped. The peripheral clocks can be enabled. The current consumption in Sleep mode is application-dependent.
Sleep mode is entered via Wait for Interrupt (WFI) instructions.
The processor can be awakened from an interrupt if the WFI instruction of the Cortex-M4 is used.
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
16
5.5.5 Low-power Mode Configuration Summary
Table 5-1 summarizes the power consumption, wakeup time and system state in Wait mode and in Sleep mode.
Notes: 1. If the supply monitor is enabled, the Wakeup can be done through the SM.
2. The ext e rna l lo ad s on PIOs are not take n into account in the cal cu lation.
3. BOD current consumption is not included.
4. Refer to Section 39.4 “Power Consumption” in the electrical characteristics.
5. When considering wakeup time, the time required to start the PLL is not taken into account. Once started, the device works
with the 8/16/24 MHz Fast RC oscillator . The user has to add the PLL startup time if it is needed in the system. The wakeup
time is defined as the time taken for wake up until the first instruction is fetched.
Table 5-1. Low-power Mode Configuration Summary
Component or Parameter
Low-power Mode
Backup Mode W a it Mo de with Fl ash in
Deep-powerdown mode Sleep Mode
SUPC, 32 kHz Oscillator,
RTT, POR, Vo ltage
Regulator ON ON ON
POR, Supply Monitor on
VDDIO OFF(1) OFF ON
RAM Power Switch Not powered From all RAM powered
to
8 Kbytes RAM powered Powered
Core, Memory, Peripherals Not powered Powered (Not clocked) Powered (Not clocked)
Mode Entry SUPC_CR.VROFF = 1
+ SCB_SCR.SLEEPDEEP = 1
PMC_FSMR.FLPM = 1
+ CKGR_MOR.WAITMODE = 1
or
SCB_SCR.SLEEPDEEP = 0
+ PMC_FSMR.FLPM = 1
+ PMC_FSMR.LPM = 1
+ WFE
WFI
+ SCB_SCR.SLEEPDEEP = 0
+ PMC_FSMR.LPM = 0
Potential Wakeup Sources Pins WKUP0–15
RTC alarm
RTT alarm
Any event from:
- Fast startup through pins
WKUP0–15
- RTT alarm
- RTC alarm
- USB device interrupt line
- FLEXCOM0–7 and ADC
SleepWalking
Entry mode = WFI interrupt
only; any enabled interrupt
Core at Wakeup Reset Clocked back Clocked back
PIO State while in Low-
power Mode Previous state saved Previous state saved Previous state saved
PIO State at Wakeup PIOA & PIOB Inputs with pull-
ups Unchanged Unchanged
Consumption(2) (3) Refer to Table 39-9 Refer to Table 39-10 (4)
Wakeup Time(5) – Refer to Table 39-11 –
17
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
5.6 Fast Startup
The SAM G55 allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast
startup can occur upon detection of a low level on one of the 18 wakeup inputs.
The fast restart circuitry is fully asynchronous and provides a fast startup signal to the Power Management
Controller. As soon as the fast startup signal is asserted, the PMC restarts from the last Fast RC selected (the
embedded 24 MHz Fast RC oscillator), switches the master clock on the last clock of RC os cillator and reenables
the processor clock. At the wakeup of Wait mode, the code is executed in the SRAM.
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
18
6. Product Mapping
Figure 6-1. SAM G55 Product Mapping
Address memory space
Code
0x00000000
Internal SRAM
0x20000000
Peripherals
0x40000000
Reserved
0x60000000
System
0xE0000000
0xFFFFFFFF
Code
Boot Memory
0x00000000
GPNVM[1] = 0 Boot Memory = ROM
GPNVM[1] = 1 Boot Memory = Flash
Internal Flash
0x00400000
Internal ROM
0x00800000
Reserved
0x00C00000
0x1FFFFFFF
Internal SRAM
SRAM
0x20000000
Undefined (Abort)
0x20480000
0x3FFFFFFF
Peripherals
I2SC0 16
0x40000000
I2SC1 17
0x40004000
USART/TWI/SPI5 8
0x40008000
0x4000C000
TC0 TC0
0x40010000
23
TC0 TC1
+0x40
24
TC0 TC2
+0x80
25
TC1 TC3
0x40014000
26
TC1 TC4
+0x40
27
TC1 TC5
+0x80
28
USART/TWI/SPI3 14
0x40018000
USART/TWI/SPI4 19
0x4001C000
0x40020000
USART/TWI/SPI2 21
0x40024000
MEM2MEM 15
0x40028000
PDMIC0 13
0x4002C000
PDMIC1 18
0x40030000
USART/TWI/SPI7
0x40034000
ADC 29
0x40038000
CMCC
0x4003C000
USART/TWI/SPI6
0x40040000
UDP
0x40044000
CRCCU
0x40048000
System Controller
0x400E0000
Reserved
0x400E4000
0x60000000
System Controller
Reserved
0x400E0000
MATRIX
0x400E0200
PMC 5
0x400E0400
0x400E0600
CHIPID
0x400E0740
0x400E0800
EFC 6
0x400E0A00
Reserved
0x400E0C00
PIOA 11
0x400E0E00
PIOB 12
0x400E1000
Reserved
0x400E1200
SYSC RSTC
0x400E1400
1
SYSC SUPC
+0x10
SYSC RTT
+0x30
3
SYSC WDT
+0x50
4
SYSC RTC
+0x60
2
SYSC GPBR
+0x140
reserved
0x400E1600
0x400E3FFF
offset
ID
(+ : wired-or)
peripheral
block
9
20
USART/TWI/SPI1
Reserved
Reserved
USART/TWI/SPI0
RAM CMCC
0x1FFFC000
UHP DPRAM
0x20400000
19
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
7. Bootloader
The SAM G55 devices ship with a bootloader in ROM , used to downlo ad code, in interna l Flash, either th rough th e
SPI or through the TWI3.
The Bootloader mode is en tered automatically on powerup if no valid firmware is detected in the Flash. A valid
firmware is detected by performing a CRC on the content of the Flash. If the CRC is correct, the application is
started. Otherwise, the Bootloader mode is entered.
Alternatively, the Bootloader mode can be forced by applying low pulses on the NRST line. The NRST should be
asserted 10 times for a minimum of 1 µs at an interval less than 50 ms. When the bootloader detects this
sequence, it asserts the pin PA01 (NCHG) low as an acknowledge.
The Bootloader mode initializes the TWI3 in Slave Mode with the I2C address 0x26 and the SPI in Slave Mode, 8-
bit data length, SPI Mode 1.
Table 7-1 provides informatio n on the pins used by the bootloader.
For further details on bootloader operations, refer to the application note AT09002: Atmel SAM I2C - SPI
Bootloader on www.atmel.com.
Table 7-1. Boot Loader Pin Description
Pin Name Function Bootloader Use Description
PA01 NCHG Driven at 0 or pulled up Boot loader handshake
PA03 TWD Open drain input/output TWI/I2C data line
PA04 TWCK Open drain input/output TWI/I2C clock
PA11 NPCS0/NSS Input NSS, SPI slave select
PA12 MISO Push-pull output SPI master in slave out
PA13 MOSI Input SPI master out slave in
PA14 SPCK Input SPI clock
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
20
8. Memories
8.1 Internal SRAM
The SRAM G55 embeds a total of 176 Kbytes of high-speed SRAM, accessible at address 0x1FFF_C000.
The 160 Kbytes of SRAM are accessible over the Cortex-M4 system bus at address 0x2000 0000. The SRAM is in
the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. The SRAM is composed of
five blocks of 32 Kbytes. The five blocks have a power switch. Each power switch controls the supply of the SRAM
block to save power. The power switch control (SRAMxON) is in the SUPC_PWMR register (refer table 8-1).
The SRAM G55 also embeds up to 16 Kbytes of SRAM accessible at address 0x1FC0_0000. The 16 Kbytes of
SRAM can be assigned by the customer to Data Cache RAM and/or Tightly Coupled Memory (TCM) RAM
(CMCC) and on I/D bus following this configuration (PRGCSIZE) in the CMCC_CFG register:
2 Kbytes of Data RAM Cache and 14 Kbytes TCM RAM on I/D Bus (CMCC)
4 Kbytes of Data RAM Cache and 12 Kbytes TCM RAM on I/D Bus (CMCC)
8 Kbytes of Data RAM Cache and 8 Kbytes TCM RAM on I/D Bus (CMCC)
The 16 Kbytes of SRAM (Data Cache/TCM SRAM) also has a power switch (CDPSWITCH) on SUPC_MR which
controls the supply of the block.
8.2 Internal ROM
The SAMG55 product embeds an Internal ROM.
At any time, the ROM is mapped at address 0x0080 0000.
8.3 Embedded Flash
8.3.1 Flash Overview
The memory is organized in s ectors. Each sector comprises 128 Kbytes. The first sector of 128 Kbytes is divided
into three smaller sectors.
The three smalle r sectors are comprised of two sectors of 8 Kbytes and one sector of 112 Kbytes.
Refer to Figure 8-1.
Table 8-1. SRAM Power Switch vs SRAM Block
Power Switch SRAM Block SRAM Size Address SUPC_PWMR
0Block 0 8 Kbytes 0x2000_0000 SRAM0ON
1Block 0 8 Kbytes 0x2000_2000 SRAM1ON
2Block 0 16 Kbytes 0X2000_4000 SRAM2ON
3Block 1 32 Kbytes 0x2000_8000 SRAM3ON
4Block 2 32 Kbytes 0x2001_0000 SRAM4ON
5Block 3 32 Kbytes 0x2001_8000 SRAM5ON
6Block 4 32 Kbytes 0x2002_0000 SRAM6ON
7USB DPRAM – – DPRAMON
21
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
Figure 8-1. Global Flash Orga nization
Each sector is organized in pages of 512 bytes.
For sector 0:
The smaller sector 0 has 16 pages of 512 bytes.
The smaller sector 1 has 16 pages of 512 bytes.
The larger secto r ha s 22 4 pages of 512 by te s.
From sector 1 to n:
The rest of the array is comp osed of 128 -Kbyte sectors of 256 pages of 512 bytes each. Refer to Figure 8-2.
Figure 8-2. Flash Sector Organization
The SAM G55 Flash size is 512 Kbytes. Refer to Figure 8-3 for the organization of the Flash.
Flash Organization
Small Sector 0
8 Kbytes
Small Sector 1
8 Kbytes
Larger Sector
112 Kbytes
Sector 1
128 Kbytes
128 Kbytes Sector n
Sector 0
Sector size Sector name
Sector 0
Sector n
Smaller sector 0
Smaller sector 1
Larger sector
A sector size is 128 Kbytes
16 pages of 512 bytes
16 pages of 512 bytes
224 pages of 512 bytes
256 pages of 512 bytes
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
22
Figure 8-3. Flash Size
The following era se co mm a nd s ca n be use d de pe ndin g on the sect or size:
8 Kbyte small sector
Erase and write page (EWP)
Erase and write page and lock (EWPL)
Erase sector (ES) with FARG set to a page number in the sector to erase
Erase pages (EPA) with FARG [1:0] = 0 to erase 4 pages, FARG [1:0] = 1 to erase 8 pages or FARG
[1:0] = 2 to erase 16 pages. FARG [1:0] = 3 must not be used.
112 Kbyte and 128 Kbyte sectors
One block of 16 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 2
One block of 32 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 3
One sector with the command Erase sector (ES) and FARG set to a page number in the secto r to
erase
Entire memory plane
The entire Flash, with the command Erase all (EA)
The memory has one additional reprogrammable page that can be used as page signature by the user. It is
accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the user
signatur e page.
Flash 512 Kbytes
2 * 8 Kbytes
1 * 112 Kbytes
3 * 128 Kbytes
23
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
8.3.1.1 Enhanced Embedded Flash Controller
The Enhanced Em bedded Flash Co ntroller m anage s accesses performed by the masters of th e system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
8.3.1.2 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to Section 39.9 “AC Characteristics”.
8.3.1.3 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of
several consecutive pages, and each lock region has its associated lock bit.
If the erase or program command of a locked region occurs, the command is aborted and the EEFC triggers an
interrupt.
The lock bits ar e software pro grammable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.3.1.4 User Signature
Each device contains a user signature of 512 bytes. The user signature can be used to store customer information
such as trimming, keys, etc., that the customer does not want erased when asserting the ERASE pin or by
software ERASE command.
Read, write and erase of this area is allowed.
Table 8-2. Lock Bit Number
Product Number of Lock Bits Lock Region Size
SAM G55 64 8 Kbytes
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
24
8.3.1.5 Unique Identifier
The G55 Flash contains two pages of 512 bytes called unique identifier. These two pages are read-only and
cannot be erased even by the Erase pin. Ea ch device integrates its own 128-bit unique identifier. These bits are
factory-configured and cannot be changed by the user.
The sequence to read the unique identifier area is described in Section 23.4.3.8 “Unique Identifier Area”.
Some bytes within the unique identifier pages are reserved for the trimming information of the 32 kHz RC oscillator
and the internal voltage regulator.
The mapping is as follows:
Bytes [15..0]: 128 bits for unique identifier
Bytes [47..16]: Atmel reserved
Bytes [49..48]: Measured frequency (on tester) of the internal 32 kHz RC when VDDIO= 3.3V (measurement
performed at 25°C). These two bytes contain the frequency in hertz.
Bytes [51..50]: Measured frequency (on tester) of the internal 32 kHz RC when VDDIO= 1.8V (measurement
performed at 25°C). These two bytes contain the frequency in hertz.
Bytes [63..52]: Atmel reserved
Bytes [65..64]: Trimmed code of the internal regulator which allows the device to run at up to 120 MHz. The
four LSB bits must be written in the SUPC_PWMR.ECPWRx.
Bytes [67..66]: Trimmed code of the internal regulator which allows the device to run at up to 100 MHz. Only
the four LSB bits are used. They must be written in the SUPC_PWMR.ECPWRx. It is the default value after
reset.
Bytes [67..511]: Atmel reserved
8.3.1.6 General-Purpose Non-Vo latile Memory Bits
The SAM G55 features three GPNVM bits that can be cleared or set, respectively, through the commands “Clear
GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
8.3.1.7 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be
changed using GPNVM bits.
A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the comm ands “Clear GPNVM Bit” and “Set GPNVM
Bit” of the EEFC User Interface.
Setting GPNVM1 selects the boot from th e Flash. Clearing it selects the boot from the ROM. Asserting ERASE
clears the GPNVM1 and thus selects the boot from the ROM by default.
Table 8-3. General-purpose Non-volatile Memory Bits
GPNVM Bit Function
0 Security bit
1 Boot Mode Selection
2 Reserved (do not use)
25
SAM G55 [DATASHEET]
Atmel-11289F-ATARM-SAM-G55G-SAM-G55J-Datasheet_27-May-16
8.3.1.8 Calibration Bits
The GPNVM bits are used to calibrate the POR, the voltage regulator and RC 8/16/24. These bits are factory-
configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
See Section 23.4.3.6 “Calibration Bit” for more information.
8.3.1.9 Security Bit
The SAM G55 features a se curity bit, based on a specific general-purpose NVM bit (GPNVM bit 0). When the
security is enabled, any access to the Flash, SRAM, core registers and internal periphera ls through the ICE
interface is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit can only be enabled with the command “Set GPNVM Bit 0” of the EEFC User Interface. Disabling
the security bit can only be done by asserting the ERASE pin to 1, and after a full Flash erase is performed. When
the security bit is deactivated, all accesses to the Flash, SRAM, core registers and internal peripherals are
permitted.
The ERASE pin integrates a permanent pull-down. As a result, it can be left unconnected during normal operation.
However, it is recommended, in harsh environments, to connect it directly to GND if the erase operation is not
used in the application.
To avoid unexpected erase at powerup, a minimum ERASE pin assertion time is required. This time is defined in
Table 39-50 “AC Flash Characteristics”.
The erase operation is not performed when the system is in Wait mode with the Flash in Deep-powerdown mode.
To ensure that the erase operation is performed after power up, the system must not reconfigu re the ERASE pin as
GPIO or enter Wait mode with Flash in Deep-powerdown mode before the ERASE pin assertion time has elapsed.
The following sequ e nc e de ta ils the step s of th e er ase operation:
1. Assert the ERASE pin (High).
2. Assert the NRST pin (Low).
3. Power cycle the device.
4. Maintain the ERASE pin high for at least the minimum assertion time.