ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 1/48
DDR SDRAM 1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
z Double-data-rate architecture, two data transfers per clock cycle
z Bi-directional data strobe (DQS)
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2, 2.5, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
z Data mask (DM) for write masking only
z VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V
z VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V (for speed -3.6)
z Auto & Self refresh
z 32ms refresh period (4K cycle)
z 2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID Max Freq. VDD Package Comments
M13S128324A -3.6BIG2M 275MHz (DDR550) 2.6V
M13S128324A -4BIG2M 250MHz (DDR500) 2.5V
M13S128324A -5BIG2M 200MHz (DDR400) 2.5V
M13S128324A -6BIG2M 166MHz (DDR333) 2.5V
144 ball FBGA Pb-free
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 2/48
Functional Block Diagram
CLK, CLK
Bank A
Command Decoder
Control Logic
Latch Circuit
Bank B
DM
DQ
Mode Register &
Extended Mode
Register
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Sense Amplifier
Column Decoder
Data Control Circuit
Input & Output
Buffer
Address, BA
Clock
Generator
CLK
CLK
CKE
CS
RAS
CAS
WE
DLL
DQS
Bank C
Bank D
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 3/48
BALL CONFIGURATION (TOP VIEW)
(BGA144, 12mmX12mmX1.4mm Body, 0.8mm Ball Pitch)
DQS0
VSS
Thermal
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
CS
RAS
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
BA0
NC
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSS
A0
BA1
23456789
VSSQ
VSSQ
VSSQ
VSSQ
DQ2
DQ1
VSSQ
VSSQ
VSS
A10
A1
A2
DQ0
VDDQ
VDD
VSS
VSS
VDD
A3
A11
DQ31
VDDQ
VDD
VSS
A4
A9
DQ29
DQ30
VSSQ
VSSQ
NC
A6
A5
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VDD
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
10
DQ28
VDDQ
VSSQ
VSS
VSS
A7
NC
VSSQ
NC
VSSQ
VDD
VDD
A8/AP
CLK
DM3
VDDQ
DQ26
VDDQ
CKE
CLK
DQS3
DQ27
DQ25
DQ24
NC
VREF
NC
DQ8
VDDQ
NC
DQ15
DQ13
DM1
DQ11
DQ9
NC
DQ14
DQ12
DQS1
DQ10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
11 12
VDDQ
VDDQ
VDDQ
13
B
C
D
E
F
G
H
J
K
L
M
N
Pin Description
Pin Name Function Pin Name Function
A0~A11,
BA0,BA1
Address inputs
- Row address A0~A11
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DM0~DM3
DM is an input mask signal for write data.
DM0 corresponds to the data on DQ0~DQ7;
DM1 corresponds to the data on DQ8~DQ15;
DM2 corresponds to the data on DQ16~DQ23;
DM3 corresponds to the data on DQ24~DQ31.
DQ0~DQ31 Data-in/Data-out CLK, CLK Clock input
RAS Row address strobe CKE Clock enable
CAS Column address strobe CS Chip select
WE Write enable VDDQ Supply Voltage for DQ
VSS Ground VSSQ Ground for DQ
VDD Power VREF Reference Voltage for SSTL_2
DQS0~DQS3
(for FBGA)
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7;
DQS1 correspond to the data on DQ8~DQ15;
DQS2 correspond to the data on DQ16~DQ23;
DQS3 correspond to the data on DQ24~DQ31.
NC No connection
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 4/48
Absolute Maximum Rating
Parameter Symbol Value Unit
Voltage on VDD & VDDQ supply relative to VSS V
DD, VDDQ -1.0 ~ 3.6 V
Voltage on inputs relative to VSS V
INPUT -1.0 ~ 3.6 V
Voltage on I/O pins relative to VSS V
IO -0.5 ~ VDDQ+0.5 V
Operating ambient temperature TA -40 ~ +85 C°
Storage temperature TSTG -55 ~ +150 C°
Power dissipation PD 2 W
Short circuit current IOS 50 mA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = -40 to 85 C°)
Min Max
Parameter Symbol
-3.6 -4/5/6 -3.6 -4/5/6
Unit Note
Supply voltage VDD 2.5 2.375 2.7 2.625 V
I/O Supply voltage VDDQ 2.5 2.375 2.7 2.625 V
I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1
I/O Termination voltage (system) VTT V
REF - 0.04 VREF + 0.04 V 2
Input logic high voltage VIH (DC) VREF + 0.15 VDDQ + 0.3 V
Input logic low voltage VIL (DC) -0.3 VREF - 0.15 V
Input Voltage Level, CLK and CLK inputs VIN (DC) -0.3 VDDQ + 0.3 V
Input Differential Voltage, CLK and CLK inputs VID (DC) 0.36 VDDQ + 0.6 V 3
V–I Matching: Pullup to Pulldown Current Ratio VI (Ratio) 0.71 1.4 - 4
Input leakage current: Any input 0V ≤ VIN ≤ VDD
(All other pins not tested under = 0V) IL -2 2
μ
A
Output leakage current
(DQs are disable; 0V ≤ VOUT ≤ VDDQ) IOZ -5 5
μ
A
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 5/48
DC Operation Conditions - continued
Parameter Symbol Min Max Unit Note
Output High Current (Full strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT) IOH -16.8 mA 5, 7
Output Low Current (Full strength driver)
(VOUT = 0.373V, max VREF, max VTT) IOL +16.8 mA 5, 7
Output High Current (Reduced strength driver – 60%)
(VOUT = VDDQ-0.763V, min VREF, min VTT) IOH -9 mA 6
Output Low Current (Reduced strength driver – 60%)
(VOUT = 0.763V, max VREF, max VTT) IOL +9 mA 6
Output High Current (Reduced strength driver – 30%)
(VOUT = VDDQ-1.056V, min VREF, min VTT) IOH -4.5 mA 6
Output Low Current (Reduced strength driver – 30%)
(VOUT = 1.056V, max VREF, max VTT) IOL +4.5 mA 6
Notes:
1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2. VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25 V to 1.0 V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
5. VOH = 2.15V, VOL =0.35V for speed -3.5; VOH = 2.025V, VOL =0.35V for others.
6. VOH = 2.1V, VOL =0.4V for speed -3.5; VOH = 1.975V, VOL =0.4V for others.
7. The values of IOH(DC) is based on VDDQ = 2.5V and VTT = 1.29V for speed -3.5; VDDQ = 2.375V and VTT = 1.2275V for
others.
The values of IOL(DC) is based on VDDQ = 2.5V and VTT = 1.21V for speed -3.5; VDDQ = 2.375V and VTT = 1.1475V for
others.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 6/48
IDD Parameters and Test Conditions
Test Condition Symbol Note
Operating Current (one bank Active - Precharge):
tRC = tRC (min); tCK = tCK (min); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
IDD0
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; tRC = tRC (min); tCK = tCK (min); IOUT = 0mA;
Address and control inputs changing once per deselect cycle; CS = high between valid commands
IDD1 2
Precharge Power-down Standby Current:
All banks idle; Power-down mode; tCK = tCK (min); CKE
≤
VIL(max); VIN = VREF for DQ, DQS and DM. IDD2P
Precharge Floating Standby Current:
CS ≥VIH(min); All banks idle; CKE ≥VIH(min); tCK = tCK (min);
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM.
IDD2F
Precharge Quiet Standby Current:
CS ≥VIH(min); All banks idle; CKE ≥VIH(min); tCK = tCK (min);
Address and other control inputs stable at ≥VIH(min) or
≤
VIL(max); VIN = VREF for DQ, DQS, and DM.
IDD2Q
Active Power-down Standby Current:
One bank active; Power-down mode; CKE ≤VIL(max); tCK = tCK (min); VIN = VREF for DQ, DQS, and DM. IDD3P
Active Standby Current:
CS ≥VIH(min); CKE ≥VIH(min); One bank active; tRC = tRAS (max); tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
IDD3N
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min); IOUT = 0mA;
50% of data changing on every transfer.
IDD4R
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
IDD4W
Auto Refresh Current:
tRC = tRFC(min) IDD5
Self Refresh Current:
CKE ≤0.2V; external clock on; tCK = tCK (min) IDD6 1
Operating Current (Four bank operation):
Four-bank interleaving READs (burst = 4) with auto precharge; tRC = tRC (min); tCK = tCK (min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; IOUT = 0mA.
IDD7 2
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 7/48
IDD Specifications
Version
Symbol
-3.6 -4 -5 -6
Unit
IDD0 235 210 175 145 mA
IDD1 245 220 190 180 mA
IDD2P 40 40 40 40 mA
IDD2F 135 120 115 95 mA
IDD2Q 135 120 115 95 mA
IDD3P 60 55 50 45 mA
IDD3N 150 130 120 110 mA
IDD4R 440 400 350 300 mA
IDD4W 470 430 380 330 mA
IDD5 320 290 270 250 mA
IDD6 5 5 5 5 mA
IDD7 500 460 410 360 mA
Input / Output Capacitance
(VDD = 2.375V~2.625V, VDDQ =2.375V~2. 625V, TA = 25 C° , f = 1MHz)
(VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 25 C° , f = 1MHz (for speed -3.6))
Parameter Symbol Min Max Unit
Input capacitance (A0~A11, BA0~BA1, CKE,
CS , RAS , CAS , WE ) CIN1 1 4 pF
Input capacitance (CLK, CLK ) CIN2 1 5 pF
Data & DQS input/output capacitance COUT 1 6.5 pF
Input capacitance (DM) CIN3 1 6.5 pF
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 8/48
AC Operation Conditions & Timing Specifications
AC Operation Conditions
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Differential Voltage, CLK and CLK inputs VID(AC) 0.7 VDDQ+0.6 V 1
Input Crossing Point Voltage, CLK and CLK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2
Notes:
1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
AC Overshoot / Undershoot Specification
Value
Parameter Pin
-3.6/ -4/ -5/ -6
Unit
Address, Control 1.5 V
Maximum peak amplitude allowed for overshoot Data, Strobe, Mask 1.2 V
Address, Control 1.5 V
Maximum peak amplitude allowed for undershoot Data, Strobe, Mask 1.2 V
Address, Control 4.5 V-ns
Maximum overshoot area above VDD
Data, Strobe, Mask 2.4 V-ns
Address, Control 4.5 V-ns
Maximum undershoot area below VSS
Data, Strobe, Mask 2.4 V-ns
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 9/48
AC Timing Parameter & Specifications (Note: 1~6, 9~10)
-3.6 -4 -5 -6
Parameter Symbol
Min Max Min Max Min Max Min Max
Unit Note
CL2 7.5 12 7.5 12 7.5 12 7.5 12
CL2.5 6.0 12 6.0 12 6.0 12 6.0 12
Clock Period
CL3
tCK
3.6 12 4.0 12 5.0 12 6.0 12
ns
DQ output access time from
CLK/ CLK tAC -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
CLK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
CLK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS output access time from
CLK/ CLK tDQSCK -0.6 +0.6 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns
Clock to first rising edge of DQS delay tDQSS 0.8 1.2 0.8 1.2 0.8 1.2 0.8 1.2 tCK
DQ and DM input setup time (to DQS) tDS 0.4 0.45 0.45 0.45 ns
DQ and DM input hold time (to DQS) tDH 0.4 0.45 0.45 0.45 ns
DQ and DM input pulse width (for
each input) tDIPW 1.75 1.75 1.75 1.75 ns 18
Address and Control Input setup time
(fast slew rate) tIS 0.9 0.9 1.0 1.0 ns 15,17~19
Address and Control Input hold time
(fast slew rate) tIH 0.9 0.9 1.0 1.0 ns 15,17~19
Address and Control Input setup time
(slow slew rate) tIS 1.0 1.0 1.1 1.1 ns 16~19
Address and Control Input hold time
(slow slew rate) tIH 1.0 1.0 1.1 1.1 ns 16~19
Control and Address input pulse width
(for each input) tIPW 2.2 2.2 2.2 2.2 ns 18
DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS falling edge to CLK setup time tDSS 0.2 0.2 0.2 0.2 tCK
DQS falling edge hold time from CLK tDSH 0.2 0.2 0.2 0.2 tCK
Data strobe edge to output data edge tDQSQ 0.4 0.4 0.4 0.45 ns 22
Data-out high-impedance time from
CLK/ CLK tHZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns 11
Data-out low-impedance time from
CLK/ CLK tLZ -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 -0.7 +0.7 ns 11
Clock half period tHP
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns 20,21
DQ-DQS output hold time from DQS tQH tHP-
tQHS tHP-
tQHS tHP-
tQHS tHP-
tQHS ns 21
Data hold skew factor tQHS 0.4 0.45 0.45 0.5 ns
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 10/48
AC Timing Parameter & Specifications - continued
-3.6 -4 -5 -6
Parameter Symbol
Min Max Min Max Min Max Min Max
Unit Note
Active to Precharge command tRAS 39.6 70K 40 70K 40 70K 42 70K ns
Active to Active /Auto Refresh
command period tRC 54 52 55 60 ns
Auto Refresh to Active /Auto Refresh
command period tRFC 64.8 68 70 72 ns
Active to Read delay tRCDRD 14.4 15 15 18 ns
Active to Write delay tRCDWR 10 10 10 18 ns
Precharge command period tRP 14.4 15 15 18 ns
Active to Read with Auto Precharge
command tRAP tRCDRD or
tRAS min tRCDRD or
tRAS min tRCDRD or
tRAS min tRCDRD or
tRAS min ns
Active bank A to Active bank B
command tRRD 10 10 10 12 ns
Write recovery time tWR 15 15 15 15 ns
Write data in to Read command delay tWTR 2 2 2 2 tCK
Col. Address to Col. Address delay tCCD 1 1 1 1 tCK
Average periodic refresh interval tREFI 7.8 7.8 7.8 7.8 us 14
Write preamble tWPRE 0.25 0.25 0.25 0.25 tCK
Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 12
Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK
Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Clock to DQS write preamble setup
time tWPRES 0 0 0 0 ns 13
Mode Register Set command cycle
time tMRD 2 2 2 2 tCK
Exit self refresh to Read command tXSRD 200 200 200 200 tCK
Exit self refresh to non-Read
command tXSNR 75 75 75 75 ns
Auto Precharge write recovery +
precharge time tDAL (tWR/tCK)
+(tRP/tCK) (tWR/tCK)
+(tRP/tCK) (tWR/tCK)
+(tRP/tCK) (tWR/tCK)
+(tRP/tCK) t
CK 23
Notes:
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference
load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial
transmission line terminated at the tester electronics).
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 11/48
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and
VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch
as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ
is recognized as LOW.
7. Enables on-chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross; the
input reference level for signals other than CLK/ CLK , is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level but specify when the device output is no longer driving (tHZ), or begins driving (tLZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK
edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no
writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a previous write was
in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CLK & CLK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed
by device design or tester correlation.
19. Slew Rate is measured between VOH(AC) and VOL(AC).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk))
into the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1)
The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed
by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output
pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for
any given cycle.
23. For each of the terms above, if not already an integer, round to the next highest integer.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 12/48
Command Truth Table
COMMAND CKEn-1 CKEn CS RAS CAS WE DM BA0~1 A8/AP A11~A9,
A7~A0 Note
Register Extended MRS H X L L L L X OP CODE 1,2
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X
3
L H H H 3
Refresh Self Refresh Exit L H
H X X X
XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column
Address Auto Precharge Enable H X L H L H X V H
Column
Address
(A0~A7) 4
Auto Precharge Disable L 4,8
Write &
Column
Address Auto Precharge Enable H X L H L L V V H
Column
Address
(A0~A7) 4,6,8
Burst Terminate H X L H H L X X 7
Bank Selection V L
Precharge All Banks H X L L H L X X H X 5
H X X X
Entry H L
L H H H
X
Active Power Down Mode
Exit L H X X X X X
X
H X X X
Entry H L
L H H H
X
H X X X
Precharge Power Down
Mode
Exit L H
L H H H
X
X
Deselect (NOP) H X X X
No Operation (NOP) H X
L H H H
XX
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A11 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “High” at row precharge, BA is ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding and
coincident DM is “High”. (Write DM latency is 0).
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 13/48
Basic Functionality
Power-Up and Initialization Sequence
DDR SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation. No power sequencing is specified during power up and power down given the following criteria:
VDD and VDDQ are driven from a single power converter output, AND
VTT is limited to 1.35 V, AND
VREF tracks VDDQ /2
OR, the following relationships must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3 V, AND
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V, AND
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V.
At least one of these two conditions must be met.
Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS
LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ
and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access).
After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 μs delay prior to
applying an executable command. Once the 200 μs delay has been satisfied, a DESELECT or NOP command should be applied,
and CKE should be brought HIGH.
Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command should
be issued for the Extended Mode Register, to enable the DLL, and then a MODE REGISTER SET command should be issued for
the Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset
and any executable command. A PRECHARGE ALL command should be applied, placing the device in the ”all banks idle” state.
Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode
Register, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 14/48
Mode Register Definition
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of
different applications. The default value of the register is not defined, therefore the mode register must be written after EMRS setting
for proper DDR SDRAM operation. The mode register is written by asserting low on CS , RAS , CAS , WE and BA0~BA1 (The
DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address
pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0~BA1 going low is written in the mode register. Two clock
cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is
divided into various fields depending on functionality. The burst length uses A0~A2, addressing mode uses A3, CAS latency (read
latency from column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS
operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 0 RFU DLL TM CAS Latency BT Burst Length Mode Register
A8 DLL Reset A7 Mode A3 Burst Type
0 No 0 Normal 0 Sequential
1 Yes 1 Test 1 Interleave
Burst Length
CAS Latency Length
A6 A5 A4 Latency
A2 A1 A0
Sequential Interleave
BA1 BA0 Operating Mode 0 0 0 Reserve 0 0 0 Reserve Reserve
0 0 MRS Cycle 0 0 1 Reserve 0 0 1 2 2
0 1 EMRS Cycle 0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserve 1 0 0 Reserve Reserve
1 0 1 Reserve 1 0 1 Reserve Reserve
1 1 0 2.5 1 1 0 Reserve Reserve
1 1 1 Reserve 1 1 1 Reserve Reserve
Note: RFU (Reserved for future use) must stay “0” during MRS cycle.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 15/48
Extended Mode Register Set (EMRS)
The extended mode register stores the data enabling or disabling DLL and selecting output drive strength. The default value of the
extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling
DLL. The extended mode register is written by asserting low on CS , RAS , CAS , WE , BA1 and high on BA0 (The DDR SDRAM
should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins
A0~A11 and BA0~BA1 in the same cycle as CS , RAS , CAS and WE going low is written in the extended mode register. Two
clock cycles are requested to complete the write operation the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable
or disable. A1 and A6 are used for setting drive strength. “High” on BA0 is used for EMRS. All the other address pins except A0~1,
A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0 1 RFU DS RFU DS DLL Extended Mode Register
A6 A1 Driver Strength A0 DLL Enable
0 0 100% Strength 0 Enable
0 1 60% Strength 1 Disable
1 0 RFU
1 1 30% Strength
BA1 BA0 Operating Mode
0 0 MRS Cycle
0 1 EMRS Cycle
Note: RFU (Reserved for future use) must stay “0” during EMRS cycle.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 16/48
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1, A0) Sequential Mode Interleave Mode
xx0 0, 1 0, 1
2 xx1 1, 0 1, 0
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
4
x11 3, 0, 1, 2 3, 2, 1, 0
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
8
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the
DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be
issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive strength
options, intended for lighter load and/or point-to-point environments.
Mode Register
01 234 567
COMMAND
t
CK
Precharge
All Banks MRS / EMRS
t
RP
*2
*1
CLK
CLK
Any
Command
t
MRD
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS/EMRS command.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 17/48
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each
bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged
when the command is initiated. For write cycle, tWR(min) must be satisfied until the precharge command can be issued. After tRP from
the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A8/AP BA1 BA0 Precharge
0 0 0 Bank A Only
0 0 1 Bank B Only
0 1 0 Bank C Only
0 1 1 Bank D Only
1 X X All Banks
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The DDR SDRAM has two independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank Activation
command must be applied before any Read or Write operation is executed. The Bank Activation command to the first Read or Write
command must meet or exceed the minimum of RAS to CAS delay time (tRCDRD or tRCDWR min). Once a bank has been activated,
it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
Address
01 23
Command
Bank A
Row Addr. Bank A
Row. Addr.
Bank B
Row Addr.
Bank A
Activate NOP Bank B
Activate NOP Bank A
Activate
RAS-CAS delay (
tRCDW R
)RAS-RAS delay (
tRRD
)
ROW Cycle Time (
tRC
)
:Don'tCare
CLK
CLK
NOP
Tn Tn+1 Tn+2
Bank A
Col. Addr.
Write A
with AP
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 18/48
Read
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating
CS , RAS , CAS , and deasserting WE at the same clock rising edge as described in the command truth table. The length of the
burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating
CS , RAS , CAS , and WE at the same clock rising edge as describe in the command truth table. The length of the burst will be
determined by the values programmed during the MRS command.
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by
asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCDRD from the bank
activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or
interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the
consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length
is completed.
<Burst Length = 4, CAS Latency = 3>
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock
(CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write
cycle. The first data of a burst write cycle must be applied on the DQ pins tDS prior to data strobe edge enabled after tDQSS from the
rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent
falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data
supplied to the DQ pins will be ignored.
<Burst Length = 4>
Note * 1: The specific requirement is that DQS be valid (High or Low) on or before this CLK edge. The case shown (DQS going from
High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS
could be High at this time, depending on tDQSS.
01 23 4 5 67 8
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP
CLK
CL K
CAS Latency=3
DQS
DQ's DOUT0 DOUT1 DOUT2 DOUT3
tRPRE tRPST
01 23 4 5 67 8
COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP
CLK
CLK
DQS
DQ's DIN 0
WRITE B
DIN1 DIN2 DIN3
tDQSS max
tWPRES *1
*1
*1
DIN 0 DIN1 DIN2 DIN3
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 19/48
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point
the data from the interrupting Read command appears. Read to Read interval is tCCD(min).
<Burst Length = 4, CAS Latency = 3>
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O bus
by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the beginning the
write operation, Burt stop command must be applied at least RU(CL) clocks [RU mean round up to the nearest integer] before the
Write command.
<Burst Length = 4, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP
D
OUT 0
Burst
Term i nat e
D
IN 0
D
OUT 1
D
IN 1
D
IN 2
D
IN 3
CLK
CLK
NOP WRITE
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the
DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write
command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
01 234 5678
COMMAND
DQS
DQ's
READ A NOP NOP NOP NOP NOP NOP NOP
DOUT A0
READ B
DOUT A1DOUT B2DOUT B3DOUT B0DOUT B1
CLK
CLK
tCCD(min)
Hi -Z
Hi- Z
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 20/48
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
READ NOP NOP NOP NOP NOP NOP
D
OUT 0
Precharge
1t
CK
NOP
Interrupted by precharge
CLK
CLK
D
OUT 1
D
OUT 2
D
OUT 3
D
OUT 4
D
OUT 5
D
OUT 6
D
OUT 7
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and
when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the
last data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same
bank after tRP.
3. For a Read with auto precharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals tRP / tCK (where tCK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless tRAS (min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with auto precharge commands where tRAS (min) must still be satisfied such that a Read with auto
precharge command has the same timing as a Read command followed by the earliest possible Precharge command which does
not interrupt the burst.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 21/48
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
NOP NOP NOP NOP NOP NO P N O P
DIN A0
WRITE A
DIN A1 DIN B2 DIN B3DIN B0 DIN B1
CLK
CLK
1tCK
Hi-Z
Hi- Z
WRITE B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 22/48
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock
cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any
residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tWTR) is required to
avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be
written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.
<Burst Length = 8, CAS Latency = 3>
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP READ NOP
t
DQSS(max
)
D
IN0
WRITE
t
DQSS(min)
DM
CLK
CLK
DM
NOP NOP
Hi-Z
Hi-Z
t
WPRES
t
WTR
*5
Hi-Z
Hi-Z
t
WTR
t
WPRES
*5
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
OUT0
D
OUT1
D
OUT0
D
OUT1
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into the
memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the
Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately precede
the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller)
in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the DDR SDRAM.
5. Refer to “Burst write operation”
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 23/48
Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access
is allowed. A write recovery time (tWR) is required from the last data to precharge command. When precharge command is asserted,
any residual data from the burst write cycle must be masked by DM.
<Burst Length = 8>
01 234 5678
COMMAND
DQS
DQ's
DQS
DQ's
NOP NOP NOP NOP NOP
D
INA0
WRITE A
DM
CLK
CLK
DM
Precharge A
Hi-Z
Hi-Z
t
WPRES *5
t
WR
Hi-Z
Hi-Z
t
WR
NOP WRITE B
t
WPRES *5
t
DQSS(max
)
t
DQSS(min)
D
INA1
D
INA2
D
INA3
D
INA4
D
INA5
D
INA6
D
INA7
D
INB0
D
INB0
D
INB1
D
INA0
D
INA1
D
INA2
D
INA3
D
INA4
D
INA5
D
INA6
D
INA7
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the time required by a DRAM
core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate
the required of time between the last valid write operation and a Precharge command to the same bank.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid and ends on the rising clock edge that
strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for write
recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time
between the last valid write data and the rising clock edge in which the Precharge command is given. During this time, the DQS input
is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR.
3. For a Write with auto precharge command, a new Bank Activate command may be issued to the same bank after tWR + tRP where tWR
+ tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank
Activate commands. During write with auto precharge, the initiation of the internal precharge occurs at the same time as the earliest
possible external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied.
This includes Write with auto precharge commands where tRAS(min) must still be satisfied such that a Write with auto precharge
command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt
the burst.
5. Refer to “Burst write operation”
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 24/48
Burst Terminate
The burst terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst terminate command has the fewest restrictions making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst terminate command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
01 234 5678
COMMAND READ A NOP NOP NOP NOP NOP NOP NOP
Burst
Te r mi n a t e
CLK
CLK
DQS
DQ's D
OUT 0
Hi-Z
Hi-Z
The burst read ends after a deley equal to the CAS lantency.
D
OUT 1
The Burst Terminate command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with auto precharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the clock
edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the data
mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
01 234 5678
COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP
CLK
CLK
NOP
DQS
DQ's
t
DQSS
DM
D
IN 0
Hi-Z
Hi-Z
mas
k
ed b
y
D
M
=H
D
IN 1
D
IN 2
D
IN 3
D
IN 4
D
IN 5
D
IN 6
D
IN 7
t
DS
t
DH
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 25/48
Read with Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later
from a read with auto precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be delayed
until tRAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not
be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 2 & 2.5>
01 234 56789
COMMAND Bank A
ACTIVE NOP NOP NOP NOP NOP NOP NOP
Read A
Auto Precharge
CLK
CLK
DQS
DQ's
CAS Latency = 2
CAS Latency = 2.5
D
OUT 0
t
RP
NOP
* Bank can be reactivated at
completion of precharge
Auto-Precharge starts
Hi-Z
Hi-Z
t
RAS (min)
D
OUT 1
D
OUT 2
D
OUT 3
DQS
DQ's D
OUT 0
Hi-Z
Hi-Z D
OUT 1
D
OUT 2
D
OUT 3
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
For the same bank For the different bank
Asserted
Command 4 5 6 4 5 6
READ READ Illegal Illegal Legal Legal Legal
READ with AP*1 READ with AP Illegal Illegal Legal Legal Legal
Active Illegal Illegal Illegal Legal Legal Legal
Precharge Legal Legal Illegal Legal Legal Legal
Note 1: AP = Auto Precharge
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 26/48
Write with Auto Precharge
If A8 is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same
bank should not be issued until the internal precharge is completed. The internal precharge begins at the rising edge of the CLK with
the tWR delay after the last data-in.
<Burst Length = 4>
01 234 5678
COMMAND
DQS
DQ's
Bank A
ACTIVE
NOP NOP NOP NOP NOP NOP NOP
D
IN 0
Write A
Auto Precharge
*Bank can be reactivated
at completion of t
RP
t
WR
t
RP
Internal precharge start
CLK
CLK
D
IN 1
D
IN 2
D
IN 3
At burst read / write with auto precharge, CAS interrupt of the same bank is illegal.
For the same bank For the different bank
Asserted
Command 4 5 6 7 8 4 5 6 7 8
WRITE WRITE WRITE Illegal Illegal Illegal Legal Legal Legal Legal Legal
WRITE with AP*1 WRITE
with AP
WRITE
with AP Illegal Illegal Illegal Legal Legal Legal Legal Legal
READ Illegal READ +
DM*2
READ+
DM READ Illegal Illegal Illegal Illegal Legal Legal
READ with AP Illegal READ
with AP+
DM
READ
with AP+
DM
READ
with AP Illegal Illegal Illegal Illegal Legal Legal
Active Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal
Precharge Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal
Note: 1. AP = Auto Precharge
2. DM: Refer to “Write Interrupted by a Read & DM“
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 27/48
Auto Refresh & Self Refresh
Auto Refresh
An auto refresh command is issued by having CS , RAS and CAS held low with CKE and WE high at the rising edge of the
clock (CLK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the
external address pins is requires once this cycle has started because of the internal address counter. When the refresh cycle has
completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or
subsequent auto refresh command must be greater than or equal to the tRFC(min).
A maximum of eight consecutive AUTO REFRESH commands (with tRFC(min)) can be posted to any given DDR SDRAM meaning
that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 x tREFI .
COMMAND
CKE = High
t
RP
PRE
Auto
Refresh
CMD
t
RFC
CLK
CLK
Self Refresh
A self refresh command is defines by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock
(CLK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self
refresh operation, all inputs except CKE are ignored. Since CKE is an SSTL_2 input, VREF must be maintained during self refresh.
The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tXSRD
for locking of DLL.
COMMAND
CKE
t
XSNR(min)
Self
Refresh
Auto
Refresh
NOP
t
IS
CLK
CLK
NOP NOP NOP NOP NOP
t
IS
Note: After self refresh exit, input an auto refresh command immediately.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 28/48
Power down
Power down is entered when CKE is registered Low (no accesses can be in progress). If power down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power down occurs when there is a row active in any bank, this mode is
referred to as active power-down.
Entering power down deactivates the input and output buffers, excluding CLK, CLK and CKE. In power down mode, CKE Low
must be maintained, and all other input signals are “Don’t Care”. The minimum power down duration is at least 1 tCK + tIS. However,
power down duration is limited by the refresh requirements of the device.
The power down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid
command may be applied 1 tCK + tIS after exit from power down.
COMMAND
CKE
CLK
CLK
Precharge Read
Enter Precharge
power-down
mode
t
IS
t
IS
t
IS
t
IS
Active
Exit Precharge
power-down
mode
Enter Active
power-down
mode
Exit Active
power-down
mode
t
RP
Functional Truth Table
Truth Table – CKE [Note 1~4, 6]
CKE n-1 CKE n Current State COMMAND n ACTION n NOTE
L L Power Down X Maintain Power Down
L L Self Refresh X Maintain Self Refresh 7
L H Power Down NOP or DESELECT Exit Power Down
L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7
H L All Banks Idle NOP or DESELECT Precharge Power Down Entry
H L Bank(s) Active NOP or DESELECT Active Power Down Entry
H L All Banks Idle AUTO REFRESH Self Refresh Entry
H H See the Truth Tables as follow
Notes:
1. CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT and NOP DESELECT or NOP commands should be issued on any clock edges occurring during the tXSNR or
tXSRD period. A minimum of 200 clock cycles is needed before applying any executable command, for the DLL to lock.
6. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
must be powered down and then restarted through the specified initialization sequence before normal operation can
continue.
7. VREF must be maintained during Self Refresh operation.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 29/48
Truth Table – Current State Bank n
Current State CS RAS CAS WE COMMAND / ACTION NOTE
Command to Bank n [Note 1~6,13]
H X X X DESELECT (NOP / continue previous operation)
Any L H H H
No Operation (NOP / continue previous operation)
L L H H
ACTIVE (select and activate row)
L L L H AUTO REFRESH 7
Idle
L L L L MODE REGISTER SET 7
L H L H READ (select column & start read burst) 10
L H L L WRITE (select column & start write burst) 10
Row Active
L L H L PRECHARGE (deactivate row in bank or banks) 8
L H L H READ (select column & start new read burst) 10
L H L L WRITE (select column & start write burst) 10, 12
L L H L PRECHARGE (truncate read burst, start precharge) 8
Read
(Auto Precharge
Disabled)
L H H L BURST TERMINATE 9
L H L H READ (select column & start read burst) 10, 11
L H L L WRITE (select column & start new write burst) 10
Write
(Auto Precharge
Disabled) L L H L PRECHARGE (truncate write burst, start precharge) 8, 11
Command to Bank m [Note 1~3, 6,13~15]
H X X X DESELECT (NOP / continue previous operation)
Any L H H H No Operation (NOP / continue previous operation)
Idle X X X X Any command allowed to bank m
L L H H ACTIVE (select and activate row)
L H L H READ (select column & start read burst) 10
L H L L WRITE (select column & start write burst) 10
Row Activating,
Active, or
Precharging
L L H L PRECHARGE
L L H H ACTIVE (select and activate row)
L H L H READ (select column & start new read burst) 10
L H L L WRITE (select column & start write burst) 10, 12
Read
(Auto Precharge
disabled)
L L H L PRECHARGE
L L H H ACTIVE (select and activate row)
L H L H READ (select column & start read burst) 10, 11
L H L L WRITE (select column & start new write burst) 10
Write
(Auto Precharge
disabled)
L L H L PRECHARGE
L L H H ACTIVE (select and activate row)
L H L H READ (select column & start new read burst) 3a, 10
L H L L WRITE (select column & start write burst) 3a, 10, 12
Read with
Auto Precharge
L L H L PRECHARGE
L L H H ACTIVE (select and activate row)
L H L H READ (select column & start read burst) 3a, 10
L H L L WRITE (select column & start new write burst) 3a, 10
Write with
Auto Precharge
L L H L PRECHARGE
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 30/48
Notes:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSNR or tXSRD has been met (if the previous state
was self refresh).
2. This table is bank - specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCDRD or tRCDWR has been met. No data bursts/accesses and
no register accesses are in progress.
Read / Write: A READ / WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet
terminated or been terminated.
Read / Write with Auto Precharge Enabled: See following text, notes 3a, 3b:
3a. For devices which do not support the optional “concurrent auto precharge” feature, the Read with Auto
Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if
the same burst was executed with Auto Precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the
precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access
period starts with registration of the command and ends where the precharge period (or tRP) begins. During
the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states,
ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the access
period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other
related limitations apply (e.g., contention between READ data and WRITE data must be avoided).
3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge
enabled, or a write with auto precharge enabled, may be followed by any command to the other banks, as
long as that command does not interrupt the read or write data transfer, and all other related limitations apply
(e.g., contention between READ data and WRITE data must be avoided.)
4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Truth Table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCDRD or tRCDWR is met. Once tRCDRD
or tRCDWR is met, the bank will be in the ”row active” state.
Read/ Write with Auto -
Precharge Enabled: Starts with registration of a READ / WRITE command with AUTO PRECHARGE enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once t
RFC is met, the DDR SDRAM will be in the ”all banks idle” state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has
been met. Once tMRD is met, the DDR SDRAM will be in the ”all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once t
RP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank - specific; requires that all banks are idle and no bursts are in progress.
8. May or may not be bank - specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank - specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with AUTO PRECHARGE enabled and
Reads or Writes with AUTO PRECHARGE disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst Terminate must be used to
end the READ prior to asserting a WRITE command,
13. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
must be powered down and then restarted through the specified initialization sequence before normal operation can
continue.
14. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
15. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 31/48
Timing Diagram
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=2)
CKE
CS
RAS
CAS
BA0,BA1
ADDR
(A0~An)
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
BAa BAb
Cb
Db0 Db1 Db3
Db2
t
CK
t
IS
t
IH
t
DQSCK
t
RPRE
t
DQSCK
Qa0 Qa1 Qa2 Qa3
t
RPST
Hi-Z
t
DQSS
t
WPRE
t
DQSH
t
DQSL
t
DS
t
DH
t
DS
t
DH
t
WPST
Hi-Z
Hi-Z
READ WRITE
CLK
CLK
t
CL
t
CH
t
CK
t
CL
t
CH
BAa
Ra
Ca
Ra
ACTIVE
t
DQSQ
t
QH
:Don’tcare
Hi-Z
t
LZ
t
AC
t
HZ
t
WPRES
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 32/48
Multi Bank Interleaving READ (@ BL=4, CL=2)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Qb0 Qb1 Qb3Qb2
ACTIVE
BAb BAa BAb
Ra Rb
Ra Ca Cb
Qa0 Qa1 Qa3
Qa2
ACTIVE READ
READ
Rb
CLK
CLK
t
CCD
: Don’t care
10122B32R.B1
t
RCDRD
t
RRD
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 33/48
Multi Bank Interleaving WRITE (@ BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A8/AP
ADDR
(A0~An)
BAa
Db0 Db1 Db3
Db2
ACTIVE
BAb BAa BAb
Ra Ca Cb
Da0 Da1 Da3
Da2
ACTIVE WRITE
tRCDWR
WRITE
tRRD
tCCD
Rb
CLK
CLK
Ra Rb
:Don’tcare
10122B32R.B1
tRCDWR
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 34/48
Read with Auto Precharge (@ BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=2)
DQ(CL=2)
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Qa4 Qa5 Qa7
Qa6
BAa
tRP
Qa0 Qa1 Qa3
Qa2
ACTIVE
READ
Ca
Auto precharge start
Note1
CLK
CLK
Ra
DQS(CL=2.5)
DQ(CL=2.5) Qa4 Qa5 Qa7
Qa6
Qa0 Qa1 Qa3Qa2
:Don’tcare
10122B32R.B
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 35/48
Write with Auto Precharge (@ BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Da4 Da5 Da7
Da6
t
RP
Da0 Da1 Da3
Da2
ACTIVE
WRITE
Ca
Auto precharge start
Note1
BAa
Ra
t
WR
CLK
CLK
t
DAL
:Don’tcare
10122B32R.B
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 36/48
Write followed by Precharge (@ BL=4)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa BAa
t
WR
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE
Ca
CLK
CLK
:Don’tcare
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 37/48
Write Interrupted by Precharge & DM (@ BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 012345
HIGH
DM
COMMAND
A8/AP
ADDR
(A0~An)
BAa BAa
Da0 Da1 Da3
Da2
PRE
CHARGE
WRITE WRITE WRITE
Ca
CLK
CLK
BAb BAc
Cb Cc
Db0 Db1 Dc1Dc0 Dc3Dc2
tCCD
Da4 Da5 Da7
Da6
:Don’tcare
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 38/48
Write Interrupted by a Read (@ BL=8, CL=2)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
t
WTR
Da0 Da1 Da3
Da2
WRITE READ
Ca
CLK
CLK
BAb
Cb
Da5
Da4 Qb1 Qb3
Qb2 Qb4 Qb5
A
8
/AP
ADDR
(A0~An)
Qb6Qb0 Qb6
:Don’tcare
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 39/48
Read Interrupted by Precharge (@ BL=8)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS(CL=2)
DQ(CL=2)
01 234 5678910
HIGH
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Qa0 Qa1
READ
BAb
Ca
PRE
CHARGE
CLK
CLK
Qa2 Qa3 Qa4 Qa5
DM
2t
CK
Vali d
DQS(CL=2.5)
DQ(CL=2.5) Qa0 Qa1 Qa2 Qa3 Qa4 Qa5
2.5 t
CK
Valid
:Don’tcare
10122B32R.B
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the Read
burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a
new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate
command may be issued to the same bank after tRP (RAS Precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data
word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after
tRP.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 40/48
Read Interrupted by a Write & Burst Terminate (@ BL=8, CL=2)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
BAa
Qa0 Qa1
READ
Db0 db5
Db1 Db4
Db3Db2 Db6
BAb
Cb
Burst
Te rm i n at e WRITE
Db7
CLK
CLK
A
8
/AP
ADDR
(A0~An) Ca
: Don’t care
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 41/48
Read Interrupted by a Read (@ BL=8, CL=2)
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Qb2 Qb3 Qb5
Qb4
Qa0 Qa1 Qb1
Qb0
READ
Ca
CLK
CLK
BAb
Cb
Qb7
Qb6
READ
t
CCD
:Don’tcare
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 42/48
DM Function (@ BL=8) only for write
CKE
CS
RAS
CAS
BA0,BA1
WE
DQS
DQ
01 234 5678910
HIGH
DM
COMMAND
A
8
/AP
ADDR
(A0~An)
BAa
Da4 Da5 Da7
Da6
Da0 Da1 Da3
Da2
WRITE
Ca
CLK
CLK
:Don’tcare
10122B32R.B
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 43/48
Power up & Initialization Sequence (based on DDR400)
V
DDQ
V
REF
A0-A7
A9-An
Power-up:
VDD and
CLK stable
BA0, BA1
Extended
Mode
Register
Set
COMMAND
DM
DQS
t
MRD
t
MRD
200 cycles of CLK**
Load
Mode
Register
Reset DLL
(with A8=H)
Load
Mode
Register
(with A8=L)
V
DD
A8
T=200us
V
TT
(system*)
t
VDT
>=0
CLK
CLK
CKE
NOP
t
CH
t
CL
t
CK
t
IS
t
IH
PRE EMRS MRS PRE AR AR MRS ACT
t
IH
t
IS
CODE
t
IH
t
IS
LVCOMS LOW LEVEL
CODE CODE RA
t
IH
t
IS
CODE CODE CODE RA
BA0=L,
BA1=L
BA
t
IH
t
IS
t
IH
t
IS
BA0=L,
BA1=L
High-Z
DQ High-Z
t
RP
t
RFC
t
MRD
ALL BANKS ALL BANKS
t
RFC
BA0=H,
BA1=L
t
IH
t
IS
:Don’tcare
10122B32R.B
Notes:
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable command
can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the second
PRECHARGE ALL command.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 44/48
Mode Register Set
CKE
CS
RAS
CAS
BA0,BA1
WE
DS
DQ
01 234 5678910
HIGH
DQS
A
8
/AP
ADDR
(A0~An)
t
RP
t
MRD
CLK
CLK
High-Z
High-Z
Precharge
Command
All Bank
Mode Register Set
Command
Any
Command
ADDRESS KEY
: Don’t care
10122B32R.B
Note: Power & Clock must be stable for 200us before precharge all banks.
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 45/48
Simplified State Diagram
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 46/48
PACKING DIMENSIONS
144-BALL FBGA DDR DRAM (12x12mm)
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A 1.14
1.40 0.049 0.055
A1 0.30 0.35 0.40 0.012 0.014 0.016
Φb 0.40 0.45 0.50 0.016 0.018 0.020
D 11.90 12.00 12.10 0.469 0.472 0.476
E 11.90 12.00 12.10 0.469 0.472 0.476
D1
8.80
0.346
E1
8.80
0.346
e 0.80
0.031
aaa 0.10 0.004
bbb 0.10 0.004
ddd 0.12 0.005
eee 0.15 0.004
fff 0.08 0.006
MD/ME 12/12 12/12
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 47/48
Revision History
Revision Date Description
1.0 2010.12.20 Original
ESMT
M13S128324A (2M)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2010
Revision : 1.0 48/48
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