2
1
3
4
7
8
6
5
FB
NC
GND
OUT
EN
NR/SS
DNC
IN
DGNPACKAGE
3mm 5mmMSOP-8PowerPAD
(TOPVIEW)
´
TPS7A49
IN
+18V OUT
EN GND
-18V
TPS7A30
IN OUT
EN GND
EVM
+15V
-15V
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
–
36V, –200mA, Ultralow-Noise, Negative LINEAR REGULATOR
1FEATURES DESCRIPTION
The TPS7A30xx series of devices are negative,
23•Input Voltage Range: –3V to –36V high-voltage (–36V), ultralow-noise (15.1μVRMS, 72dB
•Noise: PSRR) linear regulators capable of sourcing a
–14μVRMS (20Hz to 20kHz) maximum load of 200mA.
–15.1μVRMS (10Hz to 100kHz) These linear regulators include a CMOS
•Power-Supply Ripple Rejection: logic-level-compatible enable pin and
capacitor-programmable soft-start function that allows
–72dB (120Hz) for customized power-management schemes. Other
– ≥ 55dB (10Hz to 700kHz) features available include built-in current limit and
•Adjustable Output: –1.18V to –33V thermal shutdown protection to safeguard the device
and system during fault conditions.
•Maximum Output Current: 200mA
•Dropout Voltage: 216mV at 100mA The TPS7A30xx family is designed using bipolar
technology, and is ideal for high-accuracy,
•Stable with Ceramic Capacitors ≥2.2μFhigh-precision instrumentation applications where
•CMOS Logic-Level-Compatible Enable Pin clean voltage rails are critical to maximize system
•Built-In, Fixed, Current-Limit and Thermal performance. This design makes it an excellent
Shutdown Protection choice to power operational amplifiers,
analog-to-digital converters (ADCs), digital-to-analog
•Available in High Thermal Performance converters (DACs), and other high-performance
MSOP-8 PowerPAD™Package analog circuitry.
•Operating Tempature Range: –40°C to +125°CIn addition, the TPS7A30xx family of linear regulators
is suitable for post dc/dc converter regulation. By
APPLICATIONS filtering out the output voltage ripple inherent to dc/dc
•Supply Rails for Op Amps, DACs, ADCs, and switching conversion, maximum system performance
Other High-Precision Analog Circuitry is provided in sensitive instrumentation, test and
measurement, audio, and RF applications.
•Audio
•Post DC/DC Converter Regulation and Ripple For applications where positive and negative
Filtering high-performance rails are required, consider TI’s
TPS7A49xx family of positive high-voltage,
•Test and Measurement ultralow-noise linear regulators.
•RX, TX, and PA Circuitry
•Industrial Instrumention Typical Application
•Base Stations and Telecom Infrastrucure
• –12V and –24V Industrial Buses
Post DC/DC Converter Regulation for
High-Performace Analog Circuitry
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2010–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT
TPS7A30xx yyy z XX is nominal output voltage (01 = Adjustable).(2)
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) For fixed -1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). VALUE
MIN MAX UNIT
IN pin to GND pin –36 +0.3 V
OUT pin to GND pin –33 +0.3 V
OUT pin to IN pin –0.3 +36 V
FB pin to GND pin –2 +0.3 V
Voltage FB pin to IN pin –0.3 +36 V
EN pin to IN pin –0.3 +36 V
EN pin to GND pin –36 +36 V
NR/SS pin to IN pin –0.3 +36 V
NR/SS pin to GND pin –2 +0.3 V
Current Peak output Internally limited
Operating virtual junction, TJ–40 +125 °C
Temperature Storage, Tstg –65 +150 °C
Human body model (HBM) 1500 V
Electrostatic discharge rating Charged device model (CDM) 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TPS7A30xx
THERMAL METRIC(1) DGN UNITS
8 PINS
θJA Junction-to-ambient thermal resistance 55.09
θJC(top) Junction-to-case(top) thermal resistance 8.47
θJB Junction-to-board thermal resistance —°C/W
ψJT Junction-to-top characterization parameter 0.36
ψJB Junction-to-board characterization parameter 14.6
θJC(bottom) Junction-to-case(bottom) thermal resistance —
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS DERATING FACTOR TA≤+25°C POWER TA= +70°C POWER TA= +85°C POWER
BOARD PACKAGE RθJA RθJC ABOVE TA= +25°C RATING RATING RATING
High-K(1) DGN 55.09°C/W 8.47°C/W 16.6mW/°C 1.83W 1.08W 0.833W
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
D DV ( V )
OUT IN
VOUT(NOM)
D DV ( I )
OUT OUT
VOUT(NOM)
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
ELECTRICAL CHARACTERISTICS(1)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2µF, COUT = 2.2µF,
CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
TPS7A30xx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range –35.0 –3.0 V
VREF Internal reference TJ= +25°C, VNR/SS = VREF –1.202 –1.184 –1.166 V
Output voltage range(2) |VIN|≥|VOUT(NOM)| + 1.0V –33.0 VREF V
Nominal accuracy TJ= +25°C, |VIN| = |VOUT(NOM)| + 0.5V –1.5 +1.5 %VOUT
VOUT |VOUT(NOM)| + 1.0V ≤|VIN|≤35V
Overall accuracy –2.5 +2.5 %VOUT
1mA ≤IOUT ≤200mA
Line regulation TJ= +25°C, |VOUT(NOM)| + 1.0V ≤|VIN|≤35V 0.14 %VOUT
Load regulation TJ= +25°C, 1mA ≤IOUT ≤200mA 0.04 %VOUT
VIN = 95% VOUT(NOM), IOUT = 100mA 216 mV
|VDO| Dropout voltage VIN = 95% VOUT(NOM), IOUT = 200mA 325 600 mV
ILIM Current limit VOUT = 90% VOUT(NOM) 220 330 500 mA
IOUT = 0mA 55 100 μA
IGND Ground current IOUT = 100mA 950 μA
VEN = +0.4V 1.0 3.0 μA
|ISHDN| Shutdown supply current VEN =–0.4V 1.0 3.0 μA
IFB Feedback current(3) 14 100 nA
VEN = |VIN| = |VOUT(NOM)| + 1.0V 0.48 1.0 μA
|IEN| Enable current VIN = VEN =–35V 0.51 1.0 μA
VIN =–35V, VEN = +15V 0.50 1.0 μA
TJ=–40°C to +125°C +2.0 +15 V
V+EN_HI Positive enable high-level voltage TJ=–40°C to +85°C +1.8 +15
V+EN_LO Positive enable low- level voltage 0 +0.4 V
V–EN_HI Negative enable high-level voltage VIN –2.0 V
V–EN_LO Negative enable low- level voltage –0.4 0 V
VIN =–3V, VOUT(NOM) = VREF, COUT = 10μF, 15.1 μVRMS
CNR/SS = 10nF, BW = 10Hz to 100kHz
VNOISE Output noise voltage VIN =–6.2V, VOUT(NOM) =–5V, COUT = 10μF,
CNR/SS = CBYP(4) = 10nF, BW = 10Hz to 17.5 μVRMS
100kHz
VIN =–6.2V, VOUT(NOM) =–5V, COUT = 10μF,
PSRR Power-supply rejection ratio 72 dB
CNR/SS = CBYP(4) = 10nF, f = 120Hz
Shutdown, temperature increasing +170 °C
TSD Thermal shutdown temperature Reset, temperature decreasing +150 °C
Operating junction temperature
TJ–40 +125 °C
range
(1) At operating conditions, VIN ≤0V, VOUT(NOM) ≤VREF ≤0V. At regulation, VIN ≤VOUT(NOM) –|VDO|. IOUT >0 flows from OUT to IN.
(2) To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5μA is required.
(3) IFB >0 flows into the device.
(4) CBYP refers to a bypass capacitor connected to the FB and OUT pins.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Error
Amp
Enable
Anti-
saturation
Thermal
Shutdown
Current
Limit
Bandgap
FB
OUT
GND
IN
EN
NR/SS
Pass
Device
Where: VOUT
R +R
1 2
³5 A,andm
VOUT
VREF
-1R =R
1 2
TPS7A3001
OUT
FB
GND
C
10 F
IN
m
C
10nF
NR/SS
R1
R2
C
10nF
BYP
C
10 F
OUT
m
IN
EN
NR/SS
VIN VOUT
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION CIRCUIT
Maximize PSRR Performance and Minimize RMS Noise
4Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
2
1
3
4
7
8
6
5
FB
NC
GND
OUT
EN
NR/SS
DNC
IN
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
PIN CONFIGURATION
DGN PACKAGE
MSOP-8
(TOP VIEW)
PIN DESCRIPTIONS
TPS7A30xx
NAME NO. DESCRIPTION
OUT 1 Regulator output. A capacitor ≥2.2µF must be tied from this pin to ground to assure stability.
FB 2 This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device.
NC 3 Not internally connected. This pin must either be left open or tied to GND.
GND 4 Ground
This pin turns the regulator on or off. If VEN ≥V+EN_HI or VEN ≤V–EN_HI, the regulator is enabled.
EN 5 If V+EN_LO ≥VEN ≥V–EN_LO, the regulator is disabled. The EN pin can be connected to IN, if not used. |VEN|≤|VIN|.
Noise reduction pin. Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap.
NR/SS 6 This capacitor allows RMS noise to be reduced to very low levels and also controls the soft-start function.
DNC 7 DO NOT CONNECT. Do not route this pin to any electrical net, not even GND or IN.
IN 8 Input supply
PowerPAD Must either be left open or tied to GND. Solder to printed circuit board (PCB) plane to enhance thermal performance.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
-1.165
-1.17
-1.175
-1.18
-1.185
V (V)
FB
-40
V (V)
IN
0
+105 C°
+85 C°
+25 C°
- °40 C
-35 -30 -25 -20 -15 -10 -5
+125 C°
2500
2000
1500
1000
500
0
I ( A)m
GND
-40
V (V)
IN
0
-35 -30 -25 -20 -15 -10 -5
T =+25°C
J
10mA
50mA
100mA
200mA
0mA
1200
1000
800
600
400
200
0
I ( A)m
GND
-40
V (V)
IN
0
-35 -30 -25 -20 -15 -10 -5
I =100mA
OUT
+105°C
+85°C
+25°C
- °40 C
+125°C
2500
2000
1500
1000
500
0
I ( A)m
GND
0
I (mA)
OUT
200
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
20 40 60 80 100 120 140 160 180
-35
V (V)
EN
35
1000
800
600
400
200
0
200
400
600
800
1000
-
-
-
-
-
I (nA)
EN
-25 -15 -55 15 25
+25 C°
- °40 C
+125 C°
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
FEEDBACK VOLTAGE vs INPUT VOLTAGE FEEDBACK CURRENT vs TEMPERATURE
Figure 1. Figure 2.
GROUND CURRENT vs INPUT VOLTAGE GROUND CURRENT vs INPUT VOLTAGE
Figure 3. Figure 4.
GROUND CURRENT vs OUTPUT CURRENT ENABLE CURRENT vs ENABLE VOLTAGE
Figure 5. Figure 6.
6Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
-40
V (V)
IN
0
100
90
80
70
60
50
40
30
20
10
0
I ( A)m
Q
-35 -30 -25 -20 -15 -10 -5
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
I =0mA
OUT
3.5
3
2.5
2
1.5
1
0.5
0
I ( A)m
SHDN
-40
V (V)
IN
0
-35 -30 -25 -20 -15 -10 -5
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
V = 0.4V-
EN
450
400
350
300
250
200
150
100
50
0
V (mV)
DO
0
I (mA)
OUT
200
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
20 40 60 80 100 120 140 160 180
-40 -25 -10 5 20 35 50 65 80 95 110
Temperature( C)°
125
500
450
400
350
300
250
200
150
100
50
0
V (mV)
DO
10mA
50mA
100mA
200mA
-10
V (V)
IN
-3
450
400
350
300
250
200
150
100
50
0
I (mA)
LIM
-9-8-7-6-5-4
+105°C
+85°C
+25°C
- °40 C
+125°C
V =90%V
OUT OUT(NOM)
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
TYPICAL CHARACTERISTICS (continued)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
QUIESCENT CURRENT vs INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE
Figure 7. Figure 8.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 9. Figure 10.
CURRENT LIMIT vs INPUT VOLTAGE CURRENT LIMIT vs TEMPERATURE
Figure 11. Figure 12.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
10 100 100k 1M
Frequency(Hz)
10M
90
80
70
60
50
40
30
20
10
PSRR(dB)
V = 5V
V = 6.2V
I =200mA
C =10nF
C =0 F
OUT
IN
OUT
-
-
m
NR/SS
BYP
C =2.2 Fm
OUT
C =10 Fm
OUT
10k1k
-40
V (V)
IN
0
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
-
-
-
-
-
V (%)
OUT(NOM)
-35 -30 -25 -20 -15 -10 -5
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
10 100 100k 1M
Frequency(Hz)
10M
90
80
70
60
50
40
30
20
10
PSRR(dB)
V = 5V
V = 6.2V
I =200mA
C =10 F
C =0 F
OUT
IN
OUT
-
-
m
m
OUT
BYP
C =0nF
NR/SS
C =10nF
NR/SS
10k1k
1
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1
-
-
-
-
-
V (%)
OUT(NOM)
0
I (mA)
OUT
200
20 40 60 80 100 120 140 160 180
+105 C°
+85 C°
+25 C°
- °40 C
+125 C°
10 100 100k 1M
Frequency(Hz)
10M
90
80
70
60
50
40
30
20
10
PSRR(dB)
V = 5V
V = 6.2V
I =200mA
C =10nF
C =10 F
OUT
IN
OUT
-
-
m
NR/SS
OUT
C =0nF
BYP
10k1k
C =10nF
BYP
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
ENABLE THRESHOLD VOLTAGE vs TEMPERATURE POWER-SUPPLY REJECTION RATIO vs COUT
Figure 13. Figure 14.
LINE REGULATION POWER-SUPPLY REJECTION RATIO vs CNR/SS
Figure 15. Figure 16.
LOAD REGULATION POWER-SUPPLY REJECTION RATIO vs CBYP
Figure 17. Figure 18.
8Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
10 100 1k 10k
Frequency(Hz)
100k
10
1
0.1
0.01
OutputSpectralNoiseDensity( V/ )Öm Hz
V = 1.2V
V = 3V
C =10nF
C =10 F
-
OUT
IN
NR/SS
OUT
-
m
RMSNOISE
10Hzto100kHz 100Hzto100kHz
IOUT
1mA
200mA
15.13 14.73
17.13 16.71
I =200mA
OUT
I =1mA
OUT
10 100 1k 10k
Frequency(Hz)
100k
10
1
0.1
0.01
OutputSpectralNoiseDensity( V/ )m ÖHz
V = 1.2V
V = 3V
I =200mA
C =10 F
-
OUT
IN
OUT
OUT
-
m
RMSNOISE
10Hzto100kHz 100Hzto100kHz
CNR/SS
0nF
10nF
80.00 79.83
17.29 16.81
C =0nF
NR/SS
C =10nF
NR/SS
10 100 1k 10k
Frequency(Hz)
100k
10
1
0.1
0.01
OutputSpectralNoiseDensity( V/ )Öm Hz
I =1mA
C =10 F
OUT
C =10nF
C =10nF
NR/SS
BYP
OUT m
RMSNOISE
10Hzto100kHz 100Hzto100kHz
VOUT(NOM)
-5V
-1.2V
17.50 15.04
15.13 14.73
V = 5V-
OUT(NOM)
V =
OUT(NOM) -1.2V
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
TYPICAL CHARACTERISTICS (continued)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT CURRENT
Figure 19.
OUTPUT SPECTRAL NOISE DENSITY vs CNR/SS
Figure 20.
OUTPUT SPECTRAL NOISE DENSITY vs VOUT(NOM)
Figure 21.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Time(10 s/div)m
1V/div
V = 1.2V
V = 3V
I =1mA
C =C =2.2 F
C =0pF
-
-
m
OUT
OUT
IN
OUT
IN
NR/SS
VEN
VOUT
Time(20 s/div)m
1V/div
V = 1.2V
V = 3V
I =1mA
C =C =2.2 F
C =100pF
-
-
m
OUT
OUT
IN
OUT
IN
NR/SS
VEN
VOUT
Time(100 s/div)m
1V/div
V = 1.2V
V = 3V
I =1mA
C =C =2.2 F
C =1nF
-
-
m
OUT
OUT
IN
OUT
IN
NR/SS
VEN
VOUT
Time(1ms/div)
1V/div
V = 1.2V
V = 3V
I =1mA
C =C =2.2 F
C =10nF
-
-
m
OUT
OUT
IN
OUT
IN
NR/SS
VEN
VOUT
Time(10 s/div)m
20mV/div 5V/div
V = 20Vto
I =200mA
C =2.2 F
-
m
-4.3V
IN
OUT
OUT
VOUT
VIN
Time(10 s/div)m
20mV/div 5V/div
V = 4.3Vto
I =200mA
C =2.2 F
-
m
-20V
IN
OUT
OUT
VOUT
VIN
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
CAPACITOR-PROGRAMMABLE SOFT START CAPACITOR-PROGRAMMABLE SOFT START
Figure 22. Figure 23.
CAPACITOR-PROGRAMMABLE SOFT START CAPACITOR-PROGRAMMABLE SOFT START
Figure 24. Figure 25.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 26. Figure 27.
10 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
Time(100 s/div)m
50mV/div 200mA/div
V = 3.0V
I =1mAto200mA
C =2.2 F
-
m
IN
OUT
OUT
VOUT
IOUT
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
TYPICAL CHARACTERISTICS (continued)
At TJ=–40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0V or |VIN| = 3.0V (whichever is greater), VEN = VIN, IOUT = 1mA, CIN = 2.2μF,
COUT = 2.2μF, CNR/SS = 0nF, and the FB pin tied to OUT, unless otherwise noted.
LOAD TRANSIENT RESPONSE
Figure 28.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Time(20ms/div)
VIN
VEN
VOUT
TPS7A3001
OUT
FB
GND
C
10 F
IN
m
C
10nF
NR/SS
R1
R2
C
10nF
BYP
C
10 F
OUT
m
IN
EN
NR/SS
VIN VOUT
VOUT
VREF
-1
R =R
1 2
VOUT
R +R
1 2
³5 Am,where
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
THEORY OF OPERATION
GENERAL DESCRIPTION
The TPS7A30xx belongs to a family of new
generation linear regulators that use an innovative
bipolar process to achieve ultralow-noise and very
high PSRR levels at a wide input voltage range.
These features, combined with a high thermal
performance MSOP-8 with PowerPAD package make
this device ideal for high-performance analog
applications.
ADJUSTABLE OPERATION
The TPS7A3001 has an output voltage range
of –1.174 to –33V. The nominal output voltage of the
device is set by two external resistors, as shown in
Figure 29.Figure 30. Enable Pin Positive/Negative
Threshold
CAPACITOR RECOMMENDATIONS
Low ESR capacitors should be used for the input,
output, noise reduction, and bypass capacitors.
Ceramic capacitors with X7R and X5R dielectrics are
preferred. These dielectrics offer more stable
characteristics. Ceramic X7R capacitors offer
Figure 29. Adjustable Operation for Maximum AC improved over-temperature performance, while
Performance ceramic X5R capacitors are the most cost-effective
and are available in higher values.
R1and R2can be calculated for any output voltage Note that high ESR capacitors may degrade PSRR.
range using the formula shown in Equation 1. To
ensure stability under no load conditions, this INPUT AND OUTPUT CAPACITOR
resistive network must provide a current equal to or REQUIREMENTS
greater than 5μA. The TPS7A30xx family of negative, high-voltage
linear regulators achieve stability with a minimum
(1) input and output capacitance of 2.2μF; however, it is
highly recommended to use a 10μF capacitor to
If greater voltage accuracy is required, take into maximize ac performance.
account the output voltage offset contributions
because of the feedback pin current and use 0.1% NOISE REDUCTION AND BYPASS
tolerance resistors. CAPACITOR REQUIREMENTS
ENABLE PIN OPERATION Although noise reduction and bypass capacitors
(CNR/SS and CBYP, respectively) are not needed to
The TPS7A30xx provides a dual polarity enable pin achieve stability, it is highly recommended to use
(EN) that turns on the regulator when |VEN|>2.0V, 0.01μF capacitors to minimize noise and maximize ac
whether the voltage is positive or negative, as shown performance.
in Figure 30.
This functionality allows for different system power MAXIMUM AC PERFORMANCE
management topologies: In order to maximize noise and PSRR performance, it
•Connecting the EN pin directly to a negative is recommended to include 10μF or higher input and
voltage, such as VIN, or output capacitors, and 0.01μF noise reduction and
•Connecting the EN pin directly to a positive bypass capacitors, as shown in Figure 29. The
voltage, such as the output of digital logic circuitry. solution shown delivers minimum noise levels of
15.1μVRMS and power-supply rejection levels above
55dB from 10Hz to 700kHz; see Figure 18 and
Figure 19.
12 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
OUTPUT NOISE Additionally, ac performance can be maximized by
adding a 0.01μF bypass capacitor (CBYP) from the FB
The TPS7A30xx provides low output noise when a pin to the OUT pin. This capacitor greatly improves
noise reduction capacitor (CNR/SS) is used. power-supply rejection at lower frequencies, for the
band from 10Hz to 200kHz; see Figure 18.
The noise reduction capacitor serves as a filter for the
internal reference. By using a 0.01μF noise reduction The very high power-supply rejection of the
capacitor, the output noise is reduced by almost 80% TPS7A30xx makes it a good choice for powering
(from 80μVRMS to 17μVRMS); see Figure 20.high-performance analog circuitry, such as
operational amplifiers, ADCs, DACS, and audio
TPS7A30xx low output voltage noise makes it an amplifiers.
ideal solution for powering noise-sensitive circuitry.
TRANSIENT RESPONSE
POWER-SUPPLY REJECTION As with any regulator, increasing the size of the
The 0.01μF noise reduction capacitor greatly output capacitor reduces over/undershoot magnitude
improves TPS7A30xx power-supply rejection, but increases duration of the transient response.
achieving up to 20dB of additional power-supply
rejection for frequencies between 110Hz and
400KHz.
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
TPS7A49
IN
+18V OUT
EN GND
-18V
TPS7A30
IN OUT
EN GND
EVM
+15V
-15V
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
APPLICATION INFORMATION
POWER FOR PRECISION ANALOG The TPS7A30xx offers a wide-bandwidth, very-high
One of the primary TPS7A30xx applications is to power-supply rejection ratio. This specification makes
provide ultralow noise voltage rails to it ideal for post dc/dc converter filtering, as shown in
high-performance analog circuitry in order to Figure 31. It is highly recommended to use the
maximize system accuracy and precision. maximum performance schematic shown in
Figure 29. Also, verify that the fundamental frequency
In conjunction with its positive counterpart, the (and its first harmonic, if possible) is within the
TPS7A49xx family of positive high-voltage linear bandwidth of the regulator PSRR, shown in
regulators, the TPS7A30xx family of negative high Figure 18.
voltage linear regulators provides ultralow noise
positive and negative voltage rails to
high-performance analog circuitry, such as
operational amplifiers, ADCs, DACs, and audio
amplifiers.
Because of the ultralow noise levels at high voltages,
analog circuitry with high-voltage input supplies can
be used. This characteristic allows for
high-performance analog solutions to optimize the
voltage range, maximizing system accuracy.
POST DC/DC CONVERTER FILTERING
Most of the time, the voltage rails available in a
system do not match the voltage specifications
demanded by one or more of its circuits; these rails
must be stepped up or down, depending on specific
voltage requirements.
DC/DC converters are the preferred solution to step
up or down a voltage rail when current consumption
is not negligible. They offer high efficiency with Figure 31. Post DC/DC Converter Regulation to
minimum heat generation, but they have one primary High-Performance Analog Circuitry
disadvantage: they introduce a high-frequency
component, and the associated harmonics, on top of
the dc output signal. AUDIO APPLICATIONS
This high-frequency component, if not filtered Audio applications are extremely sensitive to any
properly, degrades analog circuitry performance, distortion and noise in the audio band from 20Hz to
reducing overall system accuracy and precision. 20kHz. This stringent requirement demands clean
voltage rails to power critical high-performance audio
systems.
The very-high power-supply rejection ratio (>55dB)
and low noise at the audio band of the TPS7A30xx
maximize performance for audio applications; see
Figure 18.
14 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
P =(V V )I-
D IN OUT OUT
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
LAYOUT
PACKAGE MOUNTING at least +35°C above the maximum expected ambient
condition of your particular application. This
Solder pad footprint recommendations for the configuration produces a worst-case junction
TPS7A30xx are available at the end of this product temperature of +125°C at the highest expected
datasheet and at www.ti.com.ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A30xx
BOARD LAYOUT RECOMMENDATIONS TO has been designed to protect against overload
IMPROVE PSRR AND NOISE PERFORMANCE conditions. It was not intended to replace proper
To improve ac performance such as PSRR, output heatsinking. Continuously running the TPS7A30xx
noise, and transient response, it is recommended that into thermal shutdown degrades device reliability.
the board be designed with separate ground planes
for IN and OUT, with each ground plane connected POWER DISSIPATION
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should The ability to remove heat from the die is different for
connect directly to the GND pin of the device. each package type, presenting different
considerations in the PCB layout. The PCB area
Equivalent series inductance (ESL) and equivalent around the device that is free of other components
series resistance (ESR) must be minimized in order moves the heat from the device to the ambient air.
to maximize performance and ensure stability. Every Performance data or JEDEC low- and high-K boards
capacitor (CIN, COUT, CNR/SS, CBYP) must be placed as are given in the Dissipation Ratings Table. Using
close as possible to the device and on the same side heavier copper increases the effectiveness in
of the printed circuit board (PCB) as the regulator removing heat from the device. The addition of plated
itself. through-holes to heat dissipating layers also improves
the heatsink effectiveness.
Do not place any of the capacitors on the opposite
side of the PCB from where the regulator is installed. Power dissipation depends on input voltage and load
The use of vias and long traces is strongly conditions. Power dissipation (PD) is equal to the
discouraged because they may impact system product of the output current times the voltage drop
performance negatively and even cause instability. across the output pass element, as shown in
Equation 2:
If possible, and to ensure the maximum performance
denoted in this product datasheet, use the same (2)
layout pattern used for TPS7A30 evaluation board,
available at www.ti.com.SUGGESTED LAYOUT AND SCHEMATIC
THERMAL PROTECTION Layout is a critical part of good power-supply design.
There are several signal paths that conduct
Thermal protection disables the output when the fast-changing currents or voltages that can interact
junction temperature rises to approximately +170°C, with stray inductance or parasitic capacitance to
allowing the device to cool. When the junction generate noise or degrade the power-supply
temperature cools to approximately +150°C, the performance. To help eliminate these problems, the
output circuitry is enabled. Depending on power IN pin should be bypassed to ground with a low ESR
dissipation, thermal resistance, and ambient ceramic bypass capacitor with a X5R or X7R
temperature, the thermal protection circuit may cycle dielectric.
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of The GND pin should be tied directly to the PowerPAD
overheating. under the IC. The PowerPAD should be connected to
any internal PCB ground planes using multiple vias
Any tendency to activate the thermal protection circuit directly under the IC.
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction It may be possible to obtain acceptable performance
temperature should be limited to a maximum of with alternate PCB layouts; however, the layout
+125°C. To estimate the margin of safety in a shown in Figure 32 and the schematic shown in
complete design (including heatsink), increase the Figure 33 have been shown to produce good results
ambient temperature until the thermal protection is and are meant as a guideline.
triggered; use worst-case loads and signal conditions.
For good reliability, thermal protection should trigger
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
EN
U1 TPS7A30XXDGN
PwPd
NR/SS
DNC
IN
4
3
2
1
GND
NC
FB
OUT
5
C4
C3
C2
R1
R3
J4
C1
J1
J1Vin
GNDJ7
6
7
8
9
TPS7A30xx
SBVS125A –AUGUST 2010–REVISED MARCH 2011
www.ti.com
Figure 32. PCB Layout Example
Figure 33. Schematic for PCB Layout Example
16 Submit Documentation Feedback Copyright ©2010–2011, Texas Instruments Incorporated
TPS7A30xx
www.ti.com
SBVS125A –AUGUST 2010–REVISED MARCH 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from the page numbers in the current version.
Changes from Original (August 2010) to Revision A Page
•Switched colors for 10mA and 200mA curves in Figure 10 .................................................................................................. 7
Copyright ©2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
PACKAGE OPTION ADDENDUM
www.ti.com 12-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS7A3001DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS7A3001DGNT ACTIVE MSOP-
PowerPAD DGN 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS7A3001DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS7A3001DGNT MSOP-
Power
PAD
DGN 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7A3001DGNR MSOP-PowerPAD DGN 8 2500 367.0 367.0 35.0
TPS7A3001DGNT MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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