Electrical Specifications Subject to Change
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
1
69931234p
Typical applicaTion
FeaTures DescripTion
TimerBlox: Monostable
Pulse Generator (One Shot)
The LTC
®
6993 is a monostable multivibrator (also known as
a “one-shot” pulse generator) with a programmable pulse
width of 1µs to 33.6 seconds. The LTC6993 is part of the
TimerBlox™ family of versatile silicon timing devices.
A single resistor, RSET
, programs the LTC6993’s internal
master oscillator frequency. The output pulse width is deter-
mined by this master oscillator and an internal clock divider,
NDIV
, programmable to eight settings from 1 to 221.
tN R
kµs
OUT DIV SET
=•• ,
50 1
ΩN = 1, 8, 64,...,2
DIV 21
The output pulse is initiated by a transition on the trigger
input (TRIG). Each part can be configured to generate posi-
tive or negative output pulses. The LTC6993 is available
in four versions to provide different trigger signal polarity
and retrigger capability.
DEVICE INPUT POLARITY RETRIGGER
LTC6993-1 Rising-Edge No
LTC6993-2 Rising-Edge Yes
LTC6993-3 Falling-Edge No
LTC6993-4 Falling-Edge Yes
The LTC6993 also offers the ability to dynamically adjust the
width of the output pulse via a separate control voltage.
The LTC6993 is available in the 6-lead SOT-23 (ThinSOT)
and 6-lead 2mm × 3mm DFN packages.
Envelope Detector
applicaTions
n Pulse Width Range: 1µs to 33.6 Seconds
n Configured with 1 to 3 Resistors
n Pulse Width Max Error:
– <2.3% for Pulse Width > 512µs
– <3.4% for Pulse Width of 8µs to 512µs
– <4.9% for Pulse Width of 1µs to 8µs
n Four LTC6993 Options Available:
– Rising-Edge or Falling-Edge Trigger
– Retriggerable or Non-Retriggerable
n Configurable for Positive or Negative Output Pulse
n Fast Recovery Time
n 2.25V to 5.5V Single Supply Operation
n 70µA Supply Current at 10µs Pulse Width
n 500µs Start-Up Time
n CMOS Output Driver Sources/Sinks 20mA
n –40°C to 125°C Operating Temperature Range
n Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
n Watchdog Timer
n Frequency Discriminators
n Missing Pulse Detection
n Envelope Detection
n High Vibration, High Acceleration Environments
n Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
69931234 TA01a
LTC6993-2
OUT
V+
DIV
TRIG
GND
SET
RSET
800k
3.3V
0.1µF
SIGNAL
ENVELOPE
MODULATED
CARRIER
TRIG
2V/DIV
OUT
2V/DIV
50µs/DIV 69931234 TA01b
80kHz CARRIER
16µs
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
2
69931234p
absoluTe MaxiMuM raTings
Supply Voltage (V+) to GND ........................................6V
Maximum Voltage
on Any Pin ................(GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6993C ............................................–40°C to 85°C
LTC6993I .............................................–40°C to 85°C
LTC6993H .......................................... –40°C to 125°C
(Note 1)
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6993CDCB-1#PBF LTC6993CDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6993IDCB-1#PBF LTC6993IDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6993HDCB-1#PBF LTC6993HDCB-1#TRPBF LDXH 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6993CDCB-2#PBF LTC6993CDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6993IDCB-2#PBF LTC6993IDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6993HDCB-2#PBF LTC6993HDCB-2#TRPBF LDXK 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6993CDCB-3#PBF LTC6993CDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6993IDCB-3#PBF LTC6993IDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6993HDCB-3#PBF LTC6993HDCB-3#TRPBF LFMJ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LTC6993CDCB-4#PBF LTC6993CDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN 0°C to 70°C
LTC6993IDCB-4#PBF LTC6993IDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 85°C
LTC6993HDCB-4#PBF LTC6993HDCB-4#TRPBF LFMM 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
TOP VIEW
OUT
GND
TRIG
V+
DIV
SET
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
4
5
7
6
3
2
1
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
TRIG 1
GND 2
SET 3
6 OUT
5 V+
4 DIV
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 230°C/W, θJC = 51°C/W
pin conFiguraTion
Specified Temperature Range (Note 3)
LTC6993C ................................................ 0°C to 70°C
LTC6993I .............................................–40°C to 85°C
LTC6993H .......................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
S6 Package .......................................................300°C
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
3
69931234p
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6993CS6-1#PBF LTC6993CS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6993IS6-1#PBF LTC6993IS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6993HS6-1#PBF LTC6993HS6-1#TRPBF LTDXG 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6993CS6-2#PBF LTC6993CS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6993IS6-2#PBF LTC6993IS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6993HS6-2#PBF LTC6993HS6-2#TRPBF LTDXJ 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6993CS6-3#PBF LTC6993CS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6993IS6-3#PBF LTC6993IS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6993HS6-3#PBF LTC6993HS6-3#TRPBF LTFMH 6-Lead Plastic TSOT-23 –40°C to 125°C
LTC6993CS6-4#PBF LTC6993CS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 0°C to 70°C
LTC6993IS6-4#PBF LTC6993IS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 85°C
LTC6993HS6-4#PBF LTC6993HS6-4#TRPBF LTFMK 6-Lead Plastic TSOT-23 –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
orDer inForMaTion
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tOUT Output Pulse Width 1µ 33.55 sec
∆tOUT Pulse Width Accuracy (Note 4) NDIV ≥ 512
l
±1.7 ±2.3
±3.0
%
%
8 ≤ NDIV ≤ 64
l
±2.4 ±3.4
±4.4
%
%
NDIV = 1 (LTC6993-1 or LTC6993-2)
l
±3.6 ±4.9
±6.0
%
%
NDIV = 1 (LTC6993-3 or LTC6993-4)
l
±4.0 ±5.3
±6.4
%
%
∆tOUT/∆TPulse Width Drift Over Temperature NDIV ≥ 512
NDIV ≤ 64
l
l
±0.006
±0.008
%/°C
%/°C
Pulse Width Change With Supply NDIV ≥ 512 V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
l
l
–0.6
–0.4
–0.2
–0.1
%
%
8 ≤ NDIV ≤ 64 V+ = 4.5V to 5.5V
V+ = 2.7V to 4.5V
V+ = 2.25V to 2.7V
l
l
l
–0.9
–0.7
–1.1
–0.2
–0.2
–0.1
0.4
0.9
%
%
%
Pulse Width Jitter (Note 10) NDIV = 1 V+ = 5.5V
V+ = 2.25V
0.85
0.45
%P-P
%P-P
NDIV = 8 0.20 %P-P
NDIV = 64 0.05 %P-P
NDIV = 512 0.20 %P-P
NDIV = 4096 0.03 %P-P
tSPulse Width Change Settling Time (Note 9) tMASTER = tOUT/NDIV 6 • tMASTER µs
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
4
69931234p
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V+Operating Supply Voltage Range l2.25 5.5 V
Power-On Reset Voltage l1.95 V
IS(IDLE) Supply Current (Idle) RL = ∞, RSET = 50k, NDIV ≤ 64 V+ = 5.5V
V+ = 2.25V
l
l
165
125
200
160
µA
µA
RL = ∞, RSET = 50k, NDIV ≥ 512 V+ = 5.5V
V+ = 2.25V
l
l
135
105
175
140
µA
µA
RL = ∞, RSET = 800k, NDIV ≤ 64 V+ = 5.5V
V+ = 2.25V
l
l
70
60
110
95
µA
µA
RL = ∞, RSET = 800k, NDIV ≥ 512 V+ = 5.5V
V+ = 2.25V
l
l
65
55
100
90
µA
µA
Analog Inputs
VSET Voltage at SET Pin l0.97 1.00 1.03 V
∆VSET/∆TVSET Drift Over Temperature l±75 µV/°C
RSET Frequency-Setting Resistor l50 800 kΩ
VDIV DIV Pin Voltage l0 V+V
∆VDIV/∆V+DIV Pin Valid Code Range (Note 5) Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
l±1.5 %
DIV Pin Input Current l±10 nA
Digital I/O
TRIG Pin Input Capacitance 2.5 pF
TRIG Pin Input Current TRIG = 0V to V+±10 nA
VIH High Level TRIG Pin Input Voltage (Note 6) l0.7 • V+V
VIL Low Level TRIG Pin Input Voltage (Note 6) l0.3 • V+V
IOUT(MAX) Output Current V+ = 2.7V to 5.5V ±20 mA
VOH High Level Output Voltage (Note 7) V+ = 5.5V IOUT = –1mA
IOUT = –16mA
l
l
5.45
4.84
5.48
5.15
V
V
V+ = 5.5V IOUT = –1mA
IOUT = –16mA
l
l
3.24
2.75
3.27
2.99
V
V
V+ = 2.25V IOUT = –1mA
IOUT = –8mA
l
l
2.17
1.58
2.21
1.88
V
V
VOL Low Level Output Voltage (Note 7) V+ = 5.5V IOUT = 1mA
IOUT = 16mA
l
l
0.02
0.26
0.04
0.54
V
V
V+ = 3.3V IOUT = 1mA
IOUT = 10mA
l
l
0.03
0.22
0.05
0.46
V
V
V+ = 2.25V IOUT = 1mA
IOUT = 8mA
l
l
0.03
0.26
0.07
0.54
V
V
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
5
69931234p
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6993C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6993C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6993C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6993I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6993H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using:
VTRIG(RISING) ≈ 0.55 • V+ + 185mV and
VTRIG(FALLING) ≈ 0.48 • V+ – 155mV
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final pulse width after a 0.5× or 2× change in ISET
.
Note 10: Jitter is the ratio of the deviation of the output pulse width to the
mean of the pulse width. This specification is based on characterization
and is not 100% tested.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tPD Trigger Propagation Delay V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
11
17
28
ns
ns
ns
tWIDTH Minimum Recognized TRIG Pulse Width V+ = 3.3V 5 ns
tARM Recovery Time (LTC6993-1/LTC6993-3) –4 ns
tRETRIG Time Between Trigger Signals
(LTC6993-2/LTC6993-4)
NDIV = 1 V+ = 3.3V
NDIV > 1 V+ = 3.3V
10
50
ns
ns
trOutput Rise Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
ns
ns
tfOutput Fall Time (Note 8) V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
ns
ns
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
6
69931234p
Typical perForMance characTerisTics
tOUT Error vs Temperature
(8 ≤ NDIV ≤ 64)
tOUT Error vs Temperature
(8 ≤ NDIV ≤ 64)
tOUT Error vs Temperature
(8 ≤ NDIV ≤ 64)
tOUT Error vs Temperature
(NDIV ≥ 512)
tOUT Error vs Temperature
(NDIV ≥ 512)
tOUT Error vs Temperature
(NDIV ≥ 512)
tOUT Error vs Temperature
(NDIV = 1)
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
tOUT Error vs Temperature
(NDIV = 1)
tOUT Error vs Temperature
(NDIV = 1)
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
7
69931234p
Typical perForMance characTerisTics
tOUT Error vs RSET (NDIV = 1) tOUT Error vs RSET (8 ≤ NDIV ≤ 64) tOUT Error vs RSET (NDIV ≥ 512)
tOUT Drift vs Supply Voltage
(NDIV = 1)
tOUT Drift vs Supply Voltage
(8 ≤ NDIV ≤ 64)
tOUT Drift vs Supply Voltage
(NDIV ≥ 512)
tOUT Error vs DIVCODE
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
tOUT Error vs DIVCODEtOUT Error vs DIVCODE
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
8
69931234p
Typical perForMance characTerisTics
Typical VSET Distribution Supply Current vs Supply Voltage Supply Current vs Temperature
Supply Current
vs TRIG Pin Voltage Supply Current vs tOUT (5V)
VSET Drift vs ISET VSET Drift vs Supply VSET vs Temperature
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
ISET (µA)
0
–1.0
0
0.4
0.2
0.6
0.8
1.0
10 15 20
–0.4
–0.2
–0.6
–0.8
5
69931234 G19
VSET (mV)
REFERENCED TO ISET = 10µA
SUPPLY (V)
2
–1.0
0
0.4
0.2
0.6
0.8
1.0
456
–0.4
–0.2
–0.6
–0.8
3
69931234 G20
DRIFT (mV)
REFERENCED TO V+ = 4V
VSET (V)
0.98
0
100
50
150
200
250
0.996 1.004 1.012 1.02
0.988
69931234 G22
NUMBER OF UNITS
2 LOTS
DFN AND SOT-23
1274 UNITS
Supply Current vs tOUT (2.5V)
tOUT (ms)
50
POWER SUPPLY CURRENT (µA)
100
150
200
250
0.001 0.1 1 100
69931234 G26
0
0.01 10
ACTIVE
IDLE
V+ = 5V
CLOAD = 5pF
RLOAD = d
ACTIVE CURRENT MEASURED
WITH TRIGGER PERIOD = 2 • tOUT
(50% DUTY CYCLE)
÷1
÷8
÷64
÷512
tOUT (ms)
50
POWER SUPPLY CURRENT (µA)
100
150
200
250
0.001 0.1 1 100
69931234 G27
0
0.01 10
ACTIVE
IDLE
V+ = 2.5V
CLOAD = 5pF
RLOAD = d
ACTIVE CURRENT MEASURED
WITH TRIGGER PERIOD = 2 • tOUT
(50% DUTY CYCLE)
÷1 ÷8 ÷64 ÷512
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
9
69931234p
Typical ISET Current Limit vs V+
Trigger Propagation Delay (tPD)
vs Supply Voltage
TRIG Threshold Voltage
vs Supply Voltage Peak-to-Peak Jitter vs tOUT
tOUT (ms)
0.001
0.4
JITTER (%P-P)
0.5
0.6
0.7
0.8
0.01 0.1 1 10 100
69931234 G29
0.3
0.2
0.1
0
0.9
1.0
÷1, 5.5V
÷1, 2.25V
÷8, 2.25V
÷8, 5.5V
÷64
÷512
÷4096
PEAK-TO-PEAK tOUT
VARIATION
MEASURED OVER
30s INTERVALS
SUPPLY VOLTAGE (V)
RST PIN VOLTAGE (V)
69931234 G28
3.5
1.0
2.0
3.0
0.5
1.5
2.5
02 43 5 6
POSITIVE GOING
NEGATIVE GOING
SUPPLY VOLTAGE (V)
ISET (µA)
69931234 G30
1000
400
800
200
600
02 43 5 6
SET PIN SHORTED TO GND
Rise and Fall Time
vs Supply Voltage
Output Resistance vs Supply
Voltage
SUPPLY VOLTAGE (V)
2
0
PROPAGATION DELAY (ns)
5
10
15
20
25
30
3 4 5 6
69931234 G31
CLOAD = 5pF
SUPPLY VOLTAGE (V)
RISE/FALL TIME (ns)
6990 G32
3.0
1.5
2.5
1.0
0.5
2.0
02 43 5 6
CLOAD = 5pF
tRISE
tFALL
SUPPLY VOLTAGE (V)
OUTPUT RESISTANCE (Ω)
69931234 G33
50
25
20
35
45
5
10
15
30
40
02 43 5 6
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
10
69931234p
pin FuncTions
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This sup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (VDIV) is internally converted
into a 4-bit result (DIVCODE). VDIV may be generated by
a resistor divider between V+ and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that VDIV settles quickly. The MSB of
DIVCODE (POL) determines the polarity of the OUT pins.
When POL = 0 the output produces a positive pulse. When
POL = 1 the output produces a negative pulse.
SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) pro-
grams the master oscillator frequency. The ISET current
range is 1.25µA to 20µA. The output pulse will continue
indefinitely if ISET drops below approximately 500nA,
and will terminate when ISET increases again. A resistor
connected between SET and GND is the most accurate
way to set the pulse width. For best performance, use
a precision metal or thin film resistor of 0.5% or better
tolerance and 50ppm/°C or better temperature coefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
69931234 PF
LTC6993
TRIG
GND
SET
OUT
V+
DIV
C1
0.1µF
RSET R2
R1
V+
V+
TRIG (Pin 4/Pin 1): Trigger Input. Depending on the ver-
sion, a rising or falling edge on TRIG will initiate the output
pulse. LTC6993-1 and LTC6993-2 are rising-edge sensitive.
LTC6993-3 and LTC6993-4 are falling-edge sensitive.
The LTC6993-2 and LTC6993-4 are retriggerable, allowing
the pulse width to be extended by additional trigger signals
that occur while the output is active. The LTC6993-1/
LTC6993-3 will ignore additional trigger inputs until the
output pulse has terminated.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
GND to V+ with an output resistance of approximately
30Ω. When driving an LED or other low impedance load a
series output resistor should be used to limit source/sink
current to 20mA.
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
11
69931234p
block DiagraM
(S6 package pin numbers shown)
69931234 BD
PROGRAMMABLE DIVIDER
÷1, 8, 64, 512, 4096,
215, 218, 221
MASTER OSCILLATOR
POR
DIGITAL
FILTER
4-BIT A/D
CONVERTER
POL
R1
R2
DIV
V+
OUT
5
4
TRIG
1
6
HALT OSCILLATOR
IF ISET < 500nA
MCLK
+
–
ISET
ISET
VSET = 1V
+
–
1V
3 22
GND
SET
RSET
tOUT
TRIGGER/
RETRIGGER
LOGIC
tMASTER = •
1µs
50kΩ
VSET
ISET
S
R
QOUTPUT
POLARITY
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
12
69931234p
operaTion
The LTC6993 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (ISET) and voltage (VSET), with a 1µs/50kΩ
conversion factor that is accurate to ±1.7% under typical
conditions.
tµs
k
V
I
MASTER SET
SET
=1
50 Ω•
A feedback loop maintains VSET at 1V ±30mV, leaving
ISET as the primary means of controlling the pulse width.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET
.
The master oscillator equation reduces to:
t µs R
k
MASTER SET
=150
•Ω
From this equation, it is clear that VSET drift will not affect
the pulse width when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and the
inherent pulse width accuracy ∆tOUT of the LTC6993.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
A trigger signal (rising or falling edge on TRIG pin) latches
the output to the active state, beginning the output pulse.
At the same time, the master oscillator is enabled to time
the duration of the output pulse. When the desired pulse
width is reached, the master oscillator resets the output
latch.
The LTC6993 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 215, 218 or 221. This extends the pulse width
duration by those same factors. The divider ratio NDIV is
set by a resistor divider attached to the DIV pin.
tN
k
V
Iµs
OUT DIV SET
SET
=50 1
Ω• •
With RSET in place of VSET/ISET the equation reduces to:
tN R
kµs
OUT DIV SET
=••
50 1
Ω
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6993:
1. DIVCODE determines the frequency divider setting,
NDIV
.
2. DIVCODE determines the polarity of OUT pin, via the
POL bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
Figure 1. Simple Technique for Setting DIVCODE
69931234 F01
LTC6993
V+
DIV
GND
R1
R2
2.25V TO 5.5V
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects).
2. The driving impedance (R1||R2) does not exceed
500kΩ.
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
V
V
DIVCODE
DIV
+=+±
0 5
16 1 5
.. %
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing that
NDIV is symmetric around the DIVCODE midpoint.
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
13
69931234p
operaTion
Table 1. DIVCODE Programming
DIVCODE POL NDIV Recommended tOUT R1 (k) R2 (k) VDIV/V+
0 0 1 1µs to 16µs Open Short ≤ 0.03125 ±0.015
1 0 8 8µs to 128µs 976 102 0.09375 ±0.015
2 0 64 64µs to 1.024ms 976 182 0.15625 ±0.015
3 0 512 512µs to 8.192ms 1000 280 0.21875 ±0.015
4 0 4,096 4.096ms to 65.54ms 1000 392 0.28125 ±0.015
5 0 32,768 32.77ms to 524.3ms 1000 523 0.34375 ±0.015
6 0 262,144 262.1ms to 4.194ms 1000 681 0.40625 ±0.015
7 0 2,097,152 2.097sec to 33.55sec 1000 887 0.46875 ±0.015
8 1 2,097,152 2.097sec to 33.55sec 887 1000 0.53125 ±0.015
9 1 262,144 262.1ms to 4.194ms 681 1000 0.59375 ±0.015
10 1 32,768 32.77ms to 524.3ms 523 1000 0.65625 ±0.015
11 1 4,096 4.096ms to 65.54ms 392 1000 0.71875 ±0.015
12 1 512 512µs to 8.192ms 280 1000 0.78125 ±0.015
13 1 64 64µs to 1.024ms 182 976 0.84375 ±0.015
14 1 8 8µs to 128µs 102 976 0.90625 ±0.015
15 1 1 1µs to 16µs Short Open ≥ 0.96875 ±0.015
0.5•V+
tOUT (ms)
69931234 F02
1000
10000
100
10
1
0.001
0.1
0.01
INCREASING VDIV
V+
0V
POL BIT = 0
0
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
POL BIT = 1
Figure 2. Pulse Width Range and POL Bit vs DIVCODE
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
14
69931234p
operaTion
Monostable Multivibrator (One Shot)
The LTC6993 is a monostable multivibrator. A trigger
signal on the TRIG input will force the output to the active
(unstable) state for a programmable duration. This type
of circuit is commonly referred to as a one-shot pulse
generator.
Figures 3 details the basic operation. A rising edge on
the TRIG pin initiates the output pulse. The pulse width
(tOUT) is determined by the NDIV setting and by the resis-
tor (RSET) connected to the SET pin. Subsequent rising
edges on TRIG have no affect until the completion of the
one shot and for a short rearming time (tARM) thereafter.
To ensure proper operation, positive and negative TRIG
pulses should be at least tWIDTH wide.
The LTC6993-2 and LTC6993-4 allow the output pulse to
be “retriggered”. As shown in Figure 4, the output pulse
will stay high until tOUT after the last rising-edge on TRIG.
Successive trigger signals can extend the pulse width in-
definitely. Consequtive trigger signals must be separated
by tRETRIG to be recognized.
Negative Trigger Versions
In addition to the retrigger option, the LTC6993 family also
includes negative input (falling-edge) versions. These four
combinations are detailed in Table 2.
Table 2. Retrigger and Input Polarity Options
DEVICE INPUT POLARITY RETRIGGER
LTC6993-1 Rising-Edge No
LTC6993-2 Rising-Edge Yes
LTC6993-3 Falling-Edge No
LTC6993-4 Falling-Edge Yes
Output Polarity (POL Bit)
Each variety of LTC6993 also offers the ability to invert
the output, producing negative pulses. This option is
programmed, along with NDIV
, by the choice of DIVCODE.
(The previous section describes how to program DIVCODE
using the DIV pin).
Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0)
Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0)
tPD
tWIDTH tRETRIG
TRIG
OUT
tOUT
tPD tPD tPD
tOUT tOUT
69931234 F04
tPD
TRIG
OUT
tPD tARM
tWIDTH
tOUT tOUT tOUT
69931234 F03
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
15
69931234p
operaTion
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6993 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER
A change in DIVCODE will not be recognized until it is stable,
and will not pass through intermediate codes. A digital
filter is used to guarantee the DIVCODE has settled to a
new value before making changes to the output. However,
if the output pulse is active during the transition, the pulse
width can take on a value between the two settings.
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART
. The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of NDIV):
tSTART(TYP) = 500 • tMASTER
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before an output pulse can be
generated. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
pin so it will properly track V+. Less than 100pF will not
extend the start-up time.
The DIVCODE setting is recognized at the end of the startup
up. If POL = 1, the output will transition high. Otherwise
(if POL = 0) OUT simply remains low. At this point, the
LTC6993 is ready to respond to rising/falling edges on
the TRIG input.
Figure 5a. DIVCODE Change from 0 to 2
Figure 5b. DIVCODE Change from 2 to 0
Figure 6. Start-Up Timing Diagram
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200µs/DIV 69931234 F05a
512µs
256µs
4µs
DIV
500mV/DIV
TRIG
2V/DIV
OUT
2V/DIV
LTC6993-1
V+ = 3.3V
RSET = 200k
200µs/DIV 69931234 F05b
512µs
256µs
4µs
TRIG
V+
OUT
tSTART
(TRIG IGNORED)
tOUT
POL = 1
69931234 F06
POL = 0
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
16
69931234p
applicaTions inForMaTion
Basic Operation
The simplest and most accurate method to program the
LTC6993 is to use a single resistor, RSET
, between the
SET and GND pins. The design procedure is a four step
process.
Step 1: Select the POL Bit Setting.
The LTC6993 can generate positive or negative output
pulses, depending on the setting of the POL bit. The POL
bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1
and produces active-low pulses.
Step 2: Select LTC6993 Version.
Two input-related choices dictate the proper LTC6993 for
a given application:
• Is TRIG a rising or falling-edge input?
• Should retriggering be allowed?
Use Table 2 to select a particular variety of LTC6993.
Step 3: Select the NDIV Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the NDIV
value. For a given output pulse width (tOUT), NDIV should
be selected to be within the following range:
t
µs Nt
µs
OUT DIV OUT
16 1
≤ ≤
(1)
To minimize supply current, choose the lowest NDIV value.
However, in some cases a higher value for NDIV will provide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate NDIV
values for the desired tOUT
.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 4: Calculate and Select RSET
.
The final step is to calculate the correct value for RSET
using the following equation:
Rk
µs
t
N
SET OUT
DIV
=50
1•
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a one-shot circuit that satisfies the fol-
lowing requirements:
• tOUT = 100µs
• Negative Output Pulse
• Rising-Edge Trigger Input
• Retriggereable Input
• Minimum power consumption
Step 1: Select the POL Bit Setting.
For inverted (negative) output pulse, choose POL = 1.
Step 2: Select the LTC6993 Version.
A rising-edge retriggerable input requires the LTC6993-2.
Step 3: Select the NDIV Frequency Divider Value.
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 100µs:
6.25 ≤ NDIV ≤ 100
Potential settings for NDIV include 8 and 64. NDIV = 8 is
the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 1 and NDIV = 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and
R2 = 976k values to program DIVCODE = 14.
Step 4: Select RSET
.
Calculate the correct value for RSET using Equation (2):
Rk
µs
µs k
SET = =
50
1
100
8625•
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
17
69931234p
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in tOUT is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 7.
applicaTions inForMaTion
Figure 7. 100µs Negative Pulse Generator
LTC6993-2
TRIG
GND
SET
OUT
V+
DIV
R1
102k
DIVCODE = 14
69931234 F07
2.25V TO 5.5V
R2
976k
RSET
625k
Figure 8. Voltage-Controlled Pulse Width
LTC6993
TRIG
GND
SET
OUT
V+
DIV
R1
C1
0.1µF
69931234 F08
V+
R2
RSET
RMOD
VCTRL
69931234 F09
LTC6993
TRIG
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
V+
RMOD
RSET
–
+
V+
1/2
LTC6078
LTC1659
V+
VCC REF
GND
VOUT
µP
DIN
CLK
CS/LD
NDIV • RMOD
50kΩ
tOUT =
DIN = 0 TO 4095
•
–
1+ RMOD
RSET
DIN
4096
1µs
Voltage-Controlled Pulse Width
With one additional resistor, the LTC6993 output pulse width
can be manipulated by an external voltage. As shown in
Figure 8, voltage VCTRL sources/sinks a current through
RMOD to vary the ISET current, which in turn modulates
the pulse width as described in Equation (3).
tN R
k
µs
R
R
V
V
OUT DIV MOD
MOD
SET
CTRL
SET
=
+
••
–
50
1
1
Ω
(3)
Digital Pulse Width Control
The control voltage can be generated by a DAC (digital-to-
analog converter), resulting in a digitally-controlled pulse
width. Many DACs allow for the use of an external refer-
ence. If such a DAC is used to provide the VCTRL voltage,
the VSET dependency can be eliminated by buffering VSET
and using it as the DAC’s reference voltage, as shown in
Figure 9. The DAC’s output voltage now tracks any VSET
variation and eliminates it as an error source. The SET pin
cannot be tied directly to the reference input of the DAC
because the current drawn by the DAC’s REF input would
affect the pulse width.
Figure 9. Digitally Controlled Pulse Width
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
18
69931234p
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET < 1.25µA. At approximately 500nA, the oscillator will
stop. Under this condition, the output pulse can still be
initiated, but will not terminate until ISET increases and
the master oscillator starts again.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Settling Time
Following a 2× or 0.5× step change in ISET
, the output
pulse width takes approximately six master clock cycles
(6 • tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 10, using the circuit in
Figure 8.
SET that can affect fast output pulses. Additional error is
included in the specified accuracy for NDIV = 1 to account
for this.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
TRIG (or any other fast-edge, wide-swing signal).
Power Supply Current
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting to be triggered).
IS(IDLE) varies with the programmed tOUT and the supply
voltage. Once triggered, the supply current increases while
the timing circuit is active:
IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE)
Using the following equations, the typical supply current
can be calculated under any conditions. The increase in
current ∆IS(ACTIVE) depends on the output loading and the
percentage of time that the circuit is active, which can be
expressed as a duty cycle. For example, if tOUT = 1µs and
the input is triggered every 2µs, the output duty cycle will
be 50%, which is the same amount of time the LTC6993 is
active. Note that these equations account for load capaci-
tance, but ignore resistive loads for simplicity.
If NDIV ≤ 64 (DIVCODE = 0-2, 13-15):
IV
tpF V
tpF V
k
S IDLE MASTER OUT
( ) • •
. •
= + +
+
+ + +
7 4 500
2 2
Ω
II µA
I DutyCycle
V
tpF V
SET
S ACTIVE
MASTER
+
≅
+
+
50
5
∆( )
• •
++ +
( )
tpF C
OUT LOAD
• 20
If NDIV ≥ 512 (DIVCODE = 3-12):
IV
tpF V
kI µA
I
S IDLE MASTER SET( ) • . •= + + +
+ +
7500 1 8 50
Ω
∆SS ACTIVE OUT LOAD
DutyCycle V
tC
( ) • •≅+
applicaTions inForMaTion
Figure 10. Typical Settling Time
VCTRL
2V/DIV
TRIG
5V/DIV
OUT
5V/DIV
PULSE WIDTH
2µs/DIV
LTC6993-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3µs AND 6µs
20µs/DIV 69931234 F10
Coupling Error
The current sourced by the SET pin is used to bias the in-
ternal master oscillator. The LTC6993 responds to changes
in ISET almost immediately, which provides excellent
settling time. However, this fast response also makes the
SET pin sensitive to coupling from digital signals, such
as the TRIG input.
Even an excellent layout (examples are provided in the
next section) will allow some coupling between TRIG and
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
19
69931234p
Supply Bypassing and PCB Layout Guidelines
The LTC6993 is an accurate monostable multivibrator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 11 shows example PCB layouts for both the SOT-23
and DCB packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6993. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
applicaTions inForMaTion
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a cur-
rent summing node and currents injected into this pin
directly modulate the output pulse width. Having a short
connection minimizes the exposure to signal pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
69931234 F11
LTC6993
TRIG
GND
SET
OUT
V+
DIV
C1
0.1µF R1
R2
RSET
V+
V+
DIV
SET
OUT
GND
TRIG
C1R1
R2
V+
RSET
DCB PACKAGE
TRIG
GND
SET
OUT
V+
DIV
R2
V+
RSET
TSOT-23 PACKAGE
R1
C1
Figure 11. Supply Bypassing and PCB Layout
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
20
69931234p
Typical applicaTions
Missing Pulse Detector
LTC6993-2
TRIG
GND
SET
OUT
V+
DIV
R1
102k
DIVCODE = 14
(NDIV = 8, POL = 1)
69931234 TA02a
3.3V 0.1µF
R2
976k
RSET
402k
TRIG
2V/DIV
OUT
2V/DIV
50µs/DIV 69931234 TA02b
25kHz INPUT
64µs
Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within tOUT = 64µs.
RESET = OPEN
RUN = GND (CLOSED)
20ms
FRAME RATE
GENERATOR
1.5ms
REFERENCE
PULSE
5V
20ms PERIOD
5V
R4
976k
R7
10k
C1
0.01µF
R5
102k
R3
121k
5V
R1
1M
C2
0.01µF
1.5ms PULSE
1.5ms CAL TRIM
69931234 TA03
R2
280k
R8
143k
R6
10k
LTC6991
OUT
V+
DIV
RST
GND
SET
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
1.5ms Radio Control Servo Reference Pulse Generator
PULSE IN
10µs
OUTPUT PULSE
GENERATOR
100µs
DELAY
GENERATOR
5V
R4
182k
C1
0.01µF
C2
0.1µF
R5
976k
R6
78.7k
10µs PULSE IN
10µs PULSE OUT
100µs DELAY
OUT
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
5V
R1
976k
R2
102k
R3
61.9k
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
Pulse Delay Generator
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
21
69931234p
Typical applicaTions
TRIGGER
1.5ms
PULSE
GENERATOR
20ms
RETRIGGER
LOCKOUT INTERVAL
5V
R1
1M
C2
0.1µF
0.1µF
PULSE OUT
R2
280k
R3
147k
R9
10k
R5
100k
M1
2N7002 TRIGGER PULSE IN
20ms RETRIGGER LOCKOUT RETRIGGER LOCKOUT TIME
1.5ms PULSE OUT
R4
243k
69931234 TA05
R7
392k
R6
1M
5V
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
LTC6993-1
TRIG
GND
SET
OUT
V+
DIV
RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval
RETRIGGERABLE
STAIRCASE RESET
PULSE GENERATOR
5V
R1
280k
C2
0.1µF
C1
1µF
R6
20k
R2
1M
R9
100k
R10
10k
R11
2k
D1
1N4148
R7
10k
STAIRCASE
OUT
R8
4.99k
5V 0.1µF
VOUT
R3
147k
U4
2N7002
–
+
U3
LT1490
5V
PULSES IN
0.1µF
PULSE FREQUENCY-TO-VOLTAGE CONVERTER
–
+
U2
LT1490
RESET
STAIRCASE RESET
STAIRCASE OUT
PULSES IN
RESET
69931234 TA06
MEASURE
RESETS AFTER 1.5ms IF NO PULSES APPLIED
LTC6993-2
OUT
V+
DIV
TRIG
GND
SET
Pulse Frequency-to-Voltage Converter
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
22
69931234p
5V
VOLTAGE VARIABLE
OUTPUT PULSE WIDTH
RAMP
0.1µF
Q4
2N2219A
Q2
2N2907
R6
10k
PULSE IN
Q1
2N2907
5V
R14
976k
C4
0.1µF
PULSE OUT
STRECTCHED
PULSE OUT
R15
102k
R13
113k
R16
140k
1µs TO 10µs INPUT
PULSE WIDTH
R2
182k
C2
0.1µF
R5
976k
69931234 TA07
R3
392k
5V
–
+
Q3
2N2219A
C1
2200pF
R7
10k
RAMP VOLTAGE PROPORTIONAL
TO INPUT PULSE WIDTH
500µs RAMP RESET TIMER
U4
LT1638
R1
10k
5V
R4
4.99k
U2
LT1009
2.5V
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
LTC6993-3
OUT
V+
DIV
TRIG
GND
SET
R1
1M
R4
2k
5 SECONDS ON
OFFTRIGGER IN
D1
1N4004
24V
C2
0.1µF
Q1
2N2219A
100mA
SOLENOID
DANFOSS 042 N024D
TYPE AK024D
R2
887k
69931234 TA08
R3
118k
5V
TRIGGER
LTC6993-1
OUT
V+
DIV
TRIG
GND
SET
R1
1M
R4
15k
RUN
RESET
TIMED (5s) TURN-OFF AFTER
LOSS OF INPUT PULSES
D1
1N4148
12V
NO
COTO 1022 RELAY
9001-12-01
L
C2
0.1µF
Q1
2N2219A
R2
887k
69931234 TA09
R3
118k
5V
ENABLE PULSES
C
1
LTC6993-2
OUT
V+
DIV
TRIG
GND
SET
Pulse Stretcher
On-Time Programmable Pulsed Solenoid Driver Safety Time-Out Relay Driver
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
23
69931234p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
package DescripTion
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
3.00 p0.10
(2 SIDES)
2.00 p0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 p0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 p 0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
s 45o CHAMFER
0.25 p 0.05
1.35 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)
2.15 p0.05
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.50 BSC
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
24
69931234p
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0810 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC1799 1MHz to 33MHz ThinSOT Silicon Oscillator Wide Frequency Range
LTC6900 1MHz to 20MHz ThinSOT Silicon Oscillator Low Power, Wide Frequency Range
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Micropower, ISUPPLY = 35µA at 400kHz
LTC6930 Fixed Frequency Oscillator, 32.768kHz to 8.192MHz 0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
LTC6990 TimerBlox: Voltage-Controlled Silicon Oscillator Fixed-Frequency or Voltage-Controlled Operation
LTC6991 TimerBlox: Resettable Low Frequency Oscillator Clock Periods up to 9.5 hours
LTC6992 TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) Simple PWM with Wide Frequency Range
LTC6994 TimerBlox: Delay Block/Debouncer Delay Rising Edge, Falling Edge or Both Edges
Consecutive Test Sequencer
LTC6994-1
GND
SET
30s
2s
R2
1000k
0.1µF
R3
887k
R1
63.4k
R10
25k
DELAY
ADJUST
R9
274k
5V
V+
5V
DELAY
2s TO 30s
DELAY
START
TEST
SEQUENCE
TRIG OUT
DIV
LTC6993-1
GND
SET
0.1µF
R6
191k
V+
5V
TEST 1
TRIG OUT
DIV
LTC6993-3
ONE SECOND DURATION SEQUENTIAL TEST PULSES
AFTER AN ADJUSTABLE DELAY TIME
GND
SET
0.1µF
R7
191k
V+
5V
TEST 2
TEST 3
SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS
TRIG OUT
DIV
LTC6993-3
GND
SET
R8
191k
R5
1000k
R4
681k
69931234 TA10
V+
5V
TEST 3
TRIG OUT
DIV
0.1µF
TEST 2
TEST 1
START
DELAY