DNU-1N4471JANTX - SENSITRON SEMICONDUCTOR

CY7C1441KV33

Military Temperature, 36-Mbit (1M × 36)

Flow-Through SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 002-12701 Rev. *A Revised February 7, 2018

Military Temperature, 36- Mbit (1M × 3 6) Flow-Through SRAM

Features

■Supports 133 MHz bus operations

■1M × 36 common I/O

■3.3 V core power supply

■2.5 V or 3.3 V I/O power supply

■Fast clock-to-output times

❐6.5 ns (133 MHz version)

■Provide high-performance 2-1-1-1 access rate

■User-selectable burst counter supporting interleaved or linear

burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed write

■Asynchronous output enable

■CY7C1441KV33 is available in JEDEC-standard 100-pin

TQFP and 165-ball FBGA Pb-free packages.

■IEEE 1149.1 JTAG-Compatible Boundary Scan

■“ZZ” Sleep Mode option

■Available in Military Temperature Range

Functional Description

The CY7C1441KV33 is 3.3 V, 1M × 36 synchronous

flow-through SRAMs, respectively designed to interface with

high-speed microprocessors with minimum glue logic. Maximum

access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers controlled

by a positive-edge-triggered Clock (CLK) input. The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE1), depth-expansion Chip

Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and

ADV), Write Enables (BWx, and BWE), and Global Write (GW).

Asynchronous inputs include the Output Enable (OE) and the ZZ

pin.

The CY7C1441KV33 allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses can be initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address Strobe

(ADSC) inputs. Address advancement is controlled by the

Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

The CY7C1441KV33 operates from a +3.3 V core power supply

while all outputs may operate with either a +2.5 V or +3.3 V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

Description 133 MHz Unit

Maximum access time 6.5 ns

Maximum operating current × 36 180 mA

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 2 of 31

Logic Block Diagram – CY7C1441KV33

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

A[1:0]

DQ s

DQP

A0, A1, A

ADV

CLK

ADSP

ADSC

BWE

CE1

CE2

CE3

SLEEP

CONTROL

DQPA

BYTE

WRITE REGISTER

DQP B

BYTE

WRITE REGISTER

DQP C

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQP D

BYTE

WRITE REGISTER

DQP D

BYTE

WRITE REGISTER

DQP C

BYTE

WRITE REGISTER

DQP B

BYTE

WRITE REGISTER

DQP A

BYTE

WRITE REGISTER

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 3 of 31

Contents

Pin Configurations ........................................................... 4

Pin Definitions .................................................................. 6

Functional Overview ........................................................ 7

Single Read Accesses ................................................ 7

Single Write Accesses Initiated by ADSP ...................7

Single Write Accesses Initiated by ADSC ................... 8

Burst Sequences ......................................................... 8

Sleep Mode ................................................................. 8

Interleaved Burst Address Table ................................. 8

Linear Burst Address Table ......................................... 8

ZZ Mode Electrical Characteristics .............................. 8

Truth Table ........................................................................ 9

Partial Truth Table for Read/Write ................................ 10

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11

Disabling the JTAG Feature ...................................... 11

Test Access Port (TAP) ............................................. 11

PERFORMING A TAP RESET .................................. 11

TAP REGISTERS ...................................................... 11

TAP Instruction Set ................................................... 12

TAP Controller State Diagram ....................................... 13

TAP Controller Block Diagram ...................................... 13

TAP Timing ...................................................................... 13

TAP AC Switching Characteristics ...............................14

3.3 V TAP AC Test Conditions ....................................... 14

3.3 V TAP AC Output Load Equivalent ......................... 14

2.5 V TAP AC Test Conditions ....................................... 14

2.5 V TAP AC Output Load Equivalent ......................... 14

TAP DC Electrical Characteristics

and Operating Conditions .............................................15

Identification Register Definitions ................................ 16

Scan Register Sizes ....................................................... 16

Identification Codes ....................................................... 16

Boundary Scan Order .................................................... 17

Maximum Ratings ........................................................... 18

Operating Range ............................................................. 18

Neutron Soft Error Immunity ......................................... 18

Electrical Characteristics ............................................... 18

DC Characteristics .................................................... 18

Capacitance .................................................................... 20

Thermal Resistance ........................................................ 20

AC Test Loads and Waveforms ..................................... 20

Switching Characteristics .............................................. 21

Timing Diagrams ............................................................ 22

Ordering Information ...................................................... 26

Ordering Code Definitions ......................................... 26

Package Diagrams .......................................................... 27

Acronyms ........................................................................ 29

Document Conventions ................................................. 29

Units of Measure ....................................................... 29

Document History Page ................................................. 30

Sales, Solutions, and Legal Information ...................... 31

Worldwide Sales and Design Support ....................... 31

Products .................................................................... 31

PSoC® Solutions ...................................................... 31

Cypress Developer Community ................................. 31

Technical Support ..................................................... 31

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 4 of 31

Pin Configurations

Figure 1. 100-pin TQFP pinout

NC/72M

VSS

VDD

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1441KV33

(1M × 36)

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 5 of 31

Figure 2. 165-ball FBGA pinout

Pin Configurations (continued)

CY7C1441KV33 (1M × 36)

234 5671

TDO

NC/288M

NC/144M

DQPC

DQC

DQPD

DQD

CE1BWB CE3

BWCBWE

ACE2

DQC

DQD

MODE

DQC

DQD

NC/72M

VDDQ

BWDBWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCK

VSS

TDI

DQCVSS

DQC

VSS

DQD

VDDQ

VSS

TMS

891011

ADV AADSC NC

OE ADSP ANC/576M

VSS VDDQ NC/1G DQPB

VDDQ

VDD DQB

DQB

DQA

VDD VDDQ

VDD VDDQ DQB

VDD

DQA

VDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ DQA

VDDQ

VSS

DQB

DQA

DQPA

DQA

VDDQ

VSS

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 6 of 31

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the

CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit

counter.

BWA, BWB,

BWC, BWD

Input-

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global

write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

CE1Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a

new external address is loaded.

CE2Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

loaded.

CE3Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE2 to select/deselect the device. CE3 is assumed active throughout this document for BGA. CE3

is sampled only when a new external address is loaded.

OE Input-

Asynchronous

Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input

data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV Input-

Synchronous

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically

increments the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous

Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized.

BWE Input-

Synchronous

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

ZZ Input-

Asynchronous

ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ

pin has an internal pull down.

DQsI/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by

the addresses presented during the read cycle. The direction of the pins is controlled by OE. When

OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tristate

condition.The outputs are automatically tristated during the data portion of a write sequence, during

the first clock when emerging from a deselected state, and when the device is deselected, regardless

of the state of OE.

DQPXI/O-

Synchronous

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write

sequences, DQPx is controlled by BW[A:H] correspondingly.

MODE Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or l eft f lo ati ng

selects interleaved burst sequence. This is a strap pin and should remain static during device

operation. Mode Pin has an internal pull up.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 7 of 31

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. Maximum access delay from the

clock rise (tCDV) is 6.5 ns (133 MHz device).

The CY7C1441KV33 supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium processors. The burst

order is user-selectable, and is determined by sampling the

MODE input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound burst

counter captures the first address in a burst sequence and

automatically increments the address for the rest of the burst

access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWx) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to all

four bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tristate control. ADSP is ignored if CE1 is

HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted

active, and (2) ADSP or ADSC is asserted LOW (if the access is

initiated by ADSC, the write inputs must be deasserted during

this first cycle). The address presented to the address inputs is

latched into the address register and the burst counter/control

logic and presented to the memory core. If the OE input is

asserted LOW, the requested data is available at the data

outputs a maximum to tCDV after clock rise. ADSP is ignored if

CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,

and (2) ADSP is asserted LOW. The addresses presented are

loaded into the address register and the burst inputs (GW, BWE,

and BWX)are ignored during this first clock cycle. If the write

inputs are asserted active (see Write Cycle Descriptions table for

appropriate states that indicate a write) on the next clock rise, the

appropriate data is latched and written into the device. Byte

writes are allowed. All I/Os are tristated during a byte write.Since

this is a common I/O device, the asynchronous OE input signal

must be deasserted and the I/Os must be tristated prior to the

presentation of data to DQs. As a safety precaution, the data

lines are tristated once a write cycle is detected, regardless of

the state of OE.

VDD Power Supply Power Supply Inputs to the Core of the Device.

VDDQ I/O Power

Supply

Power Supply for the I/O Circuitry.

VSS Ground Ground for the Core of the Device.

VSSQ I/O Ground Ground for the I/O Circuitry.

TDO JTAG serial

output

Synchronous

Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature

is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.

TDI JTAG serial

input

Synchronous

Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not

being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is

not available on TQFP packages.

TMS JTAG serial

input

Synchronous

Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is not

being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP

packages.

TCK JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin must be

connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die. 72M, 144M and 288M are address expansion pins

are not internally connected to the die.

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

–No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M and

NC/1G are address expansion pins are not internally connected to the die.

Pin Definitions (continued)

Name I/O Description

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 8 of 31

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted

active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input signals (GW, BWE, and BWX)

indicate a write access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the memory

core. The information presented to DQS is written into the

specified address location. Byte writes are allowed. All I/Os are

tristated when a write is detected, even a byte write. Since this

is a common I/O device, the asynchronous OE input signal must

be deasserted and the I/Os must be tristated prior to the

presentation of data to DQs. As a safety precaution, the data

lines are tristated once a write cycle is detected, regardless of

the state of OE.

Burst Sequences

The CY7C1441KV33 provide an on-chip two-bit wraparound

burst counter inside the SRAM. The burst counter is fed by A[1:0],

and can follow either a linear or interleaved burst order. The burst

order is determined by the state of the MODE input. A LOW on

MODE selects a linear burst sequence. A HIGH on MODE

selects an interleaved burst order. Leaving MODE unconnected

causes the device to default to a interleaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the “sleep” mode. CE1,

CE2,CE3, ADSP, and ADSC must remain inactive for the

duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 110 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns

tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 9 of 31

Truth Table

The truth table for CY7C1441KV33 is as follows. [1, 2, 3, 4, 5]

Cycle Description Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power down None H X X L X L X X X L–H Tristate

Deselected Cycle, Power down None L L X L L X X X X L–H Tristate

Deselected Cycle, Power down None L X H L L X X X X L–H Tristate

Deselected Cycle, Power down None L L X L H L X X X L–H Tristate

Deselected Cycle, Power down None X X H L H L X X X L–H Tristate

Sleep Mode, Power down None X X X H X X X X X X Tristate

Read Cycle, Begin Burst External L H L L L X X X L L–H Q

Read Cycle, Begin Burst External L H L L L X X X H L–H Tristate

Write Cycle, Begin Burst External L H L L H L X L X L–H D

Read Cycle, Begin Burst External L H L L H L X H L L–H Q

Read Cycle, Begin Burst External L H L L H L X H H L–H Tristate

Read Cycle, Continue Burst Next X X X L H H L H L L–H Q

Read Cycle, Continue Burst Next X X X L H H L H H L–H Tristate

Read Cycle, Continue Burst Next H X X L X H L H L L–H Q

Read Cycle, Continue Burst Next H X X L X H L H H L–H Tristate

Write Cycle, Continue Burst Next X X X L H H L L X L–H D

Write Cycle, Continue Burst Next H X X L X H L L X L–H D

Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tristate

Read Cycle, Suspend Burst Current H X X L X H H H L L–H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tristate

Write Cycle, Suspend Burst Current X X X L H H H L X L–H D

Write Cycle, Suspend Burst Current H X X L X H H L X L–H D

Notes

1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care

for the remainder of the write cycle.

5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive

or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 10 of 31

Partial Truth Table for Read/Write

The partial truth table for read/write for CY7C1441KV33 is as follows. [6, 7, 8]

Function (CY7C1441KV33) GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HL HHHH

Write Byte A (DQA, DQPA)HLHHHL

Write Byte B (DQB, DQPB)HLHHLH

Write Bytes A, B (DQA, DQB, DQPA, DQPB)HLHHLL

Write Byte C (DQC, DQPC)HLHLHH

Write Bytes C, A (DQC, DQA, DQPC, DQPA)HLHLHL

Write Bytes C, B (DQC, DQB, DQPC, DQPB)HLHLLH

Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,

DQPA)

HLHLLL

Write Byte D (DQD, DQPD)HLLHHH

Write Bytes D, A (DQD, DQA, DQPD, DQPA)HLLHHL

Write Bytes D, B (DQD, DQA, DQPD, DQPA)HLLHLH

Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,

DQPA)

HLLHLL

Write Bytes D, B (DQD, DQB, DQPD, DQPB) HLLLHH

Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,

DQPA)

HLLLHL

Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,

DQPA)

HLLLLH

Write All Bytes H L L L L L

Write All Bytes L X X X X X

Notes

6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

7. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active.

8. BWx represents any byte write signal BW[A..H].To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be

enabled at the same time for any given write.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 11 of 31

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1441KV33 incorporates a serial boundary scan test

access port (TAP). This part is fully compliant with 1149.1. The

TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic

levels.

The CY7C1441KV33 contains a TAP controller, instruction

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternately be connected to VDD through a pull up resistor. TDO

should be left unconnected. Upon power up, the device comes

up in a reset state which does not interfere with the operation of

the device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this ball unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. TDI is internally pulled

up and can be unconnected if the TAP is unused in an

application. TDI is connected to the most significant bit (MSB) of

any register (see TAP Controller Block Diagram on page 13).

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine. The output changes on the falling edge

of TCK. TDO is connected to the least significant bit (LSB) of any

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

At power up, the TAP is reset internally to ensure that TDO

comes up in a High Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

scan data into and out of the SRAM test circuitry. Only one

Data is serially loaded into the TDI ball on the rising edge of TCK.

Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

and TDO balls as shown in the TAP Controller Block Diagram on

page 13. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This shifts data through the SRAM with

minimal delay. The bypass register is set LOW (VSS) when the

BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR state

and is then placed between the TDI and TDO balls when the

controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used to

capture the contents of the I/O ring.

The Boundary Scan Order on page 17 show the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the Identification Register Definitions on

page 16.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 12 of 31

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the Instruction

Codes table. Three of these instructions are listed as

RESERVED and should not be used. The other five instructions

are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction once it is shifted in, the TAP controller must be

moved into the Update-IR state.

IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO balls and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a High Z state until the next command is given during the

“Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output undergoes a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This does not harm the device, but

there is no guarantee as to the value that is captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture setup plus hold

times (tCS and tCH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the clock captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells prior to the selection

of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required – that is, while data captured

is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRISTATE

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tristate mode.

The boundary scan register has a special bit located at bit #89

(for 165-FBGA package). When this scan cell, called the “extest

output bus tristate”, is latched into the preload register during the

“Update-DR” state in the TAP controller, it directly controls the

state of the output (Q-bus) pins, when the EXTEST is entered as

the current instruction. When HIGH, it enables the output buffers

to drive the output bus. When LOW, this bit places the output bus

into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the “Shift-DR” state. During “Update-DR”, the value

loaded into that shift-register cell latches into the preload

controls the output Q-bus pins. Note that this bit is pre-set HIGH

to enable the output when the device is powered-up, and also

when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 13 of 31

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

TAP Controller State Diagram

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

TAP Controller Block Diagram

Bypass Register

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

Selection

Circuitry

TCK

TMS TAP CONTROLLER

TDI TDO

TAP Timing

tTL

Test Clock

(TCK)

123456

est Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 14 of 31

3.3 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 3.3 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ......................................... 1.5 V

Output reference levels ................................................ 1.5 V

Test load termination supply voltage ............................ 1.5 V

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 2.5 V

Input rise and fall times (Slew Rate) ........................... 2 V/ns

Input timing reference levels ................. ......................1.25 V

Output reference levels ................ ..............................1.25 V

Test load termination supply voltage .................. ........1.25 V

TAP AC Switching Characteristics

Over the Operating Range

Parameter [9, 10] Description Min Max Unit

Clock

tTCYC TCK Clock Cycle Time 50 –ns

tTF TCK Clock Frequency –20 MHz

tTH TCK Clock HIGH time 20 –ns

tTL TCK Clock LOW time 20 –ns

Output Times

tTDOV TCK Clock LOW to TDO Valid –10 ns

tTDOX TCK Clock LOW to TDO Invalid 0 – ns

Setup Times

tTMSS TMS Setup to TCK Clock Rise 5 – ns

tTDIS TDI Setup to TCK Clock Rise 5 – ns

tCS Capture Setup to TCK Rise 5 – ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 5 – ns

tTDIH TDI Hold after Clock Rise 5 – ns

tCH Capture Hold after Clock Rise 5 – ns

3.3 V TAP AC Output Load Equivalent

1.5V

20p

Z = 50Ω

50Ω

2.5 V TAP AC Output Load Equivalent

TDO

1.25V

20pF

Z = 50Ω

50Ω

Notes

9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 2 V/ns (Slew Rate).

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 15 of 31

TAP DC Electrical Characteristics and Operating Conditions

(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)

Parameter [11] Description Description Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = –4.0 mA VDDQ = 3.3 V 2.4 – V

IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V

VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V

VDDQ = 2.5 V 2.1 – V

VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V

IOL = 1.0 mA VDDQ = 2.5 V – 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V

VDDQ = 2.5 V – 0.2 V

VIH Input HIGH Voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V

VDDQ = 2.5 V 1.7 VDD + 0.3 V

VIL Input LOW Voltage VDDQ = 3.3 V –0.3 0.8 V

VDDQ = 2.5 V –0.3 0.7 V

IXInput Load Current GND < VIN < VDDQ –5 5 µA

Note

11. All voltages referenced to VSS (GND).

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 16 of 31

Identification Register Definitions

Instruction Field CY7C1441KV33

(1M × 36) Description

Revision Number (31:29) 000 Describes the version number.

Device Depth (28:24) 01011 Reserved for Internal Use

Architecture/Memory Type(23:18)[12] 000001 Defines memory type and architecture

Bus Width/Density(17:12) 100111 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence Indicator (0) 1 Indicates the presence of an ID register.

Scan Register Sizes

Instruction Bypass 3

Bypass 1

ID 32

Boundary Scan Order (165-ball FBGA package) 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a High Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does

not affect SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

12. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 17 of 31

Boundary Scan Order

165-ball FBGA [13, 14]

CY7C1441KV33 (1M × 36)

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1N6 26 E11 51 A3 76 N1

2N7 27 D11 52 A2 77 N2

3N10 28G10 53B2 78P1

4P11 29F10 54C2 79R1

5 P8 30 E10 55 B1 80 R2

6 R8 31 D10 56 A1 81 P3

7R9 32C11 57C1 82R3

8P9 33A11 58D1 83P2

9P10 34B11 59E1 84R4

10 R10 35 A10 60 F1 85 P4

11 R11 36 B10 61 G1 86 N5

12H11 37A9 62D2 87P6

13 N11 38 B9 63 E2 88 R6

14 M11 39 C10 64 F2 89 Internal

15 L11 40 A8 65 G2

16 K11 41 B8 66 H1

17 J11 42 A7 67 H3

18 M10 43 B7 68 J1

19 L10 44 B6 69 K1

20 K10 45 A6 70 L1

21 J10 46 B5 71 M1

22 H9 47 A5 72 J2

23 H10 48 A4 73 K2

24 G11 49 B4 74 L2

25 F11 50 B3 75 M2

Notes

13. Balls which are NC (No Connect) are preset LOW.

14. Bit# 89 is preset HIGH.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 18 of 31

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage Temperature ............................... –65 C to +150C

Case Temperature

with Power Applied .................................. –55C to +125 C

Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V

Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD

DC Voltage Applied to Outputs

in Tristate ..........................................–0.5 V to VDDQ + 0.5 V

DC Input Voltage ................................ –0.5 V to VDD + 0.5 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(per MIL-STD-883, Method 3015) ......................... > 2001 V

Latch-up Current ................................................... > 200 mA

Operating Range

Range Case

Temperature VDD VDDQ

Military –55 °C to +125 °C 3.3 V– 5% /

+ 10%

2.5 V – 5% to

VDD

Neutron Soft Error Immunity

Parameter Description Test

Conditions Typ Max* Unit

LSBU Logical

Single-Bit

Upsets

25 °C <5 5 FIT/

LMBU (All

Devices)

Logical

Multi-Bit

Upsets

25 °C 0 0.01 FIT/

SEL (All

Devices)

Single Event

Latch up

85 °C 0 0.1 FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

statistical 2, 95% confidence limit calculation. For more details refer to Application

Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial

Failure Rates”

Electrical Characteristics

Over the Operating Range

DC Characteristics

Over the Operating Range

Parameter [15, 16] Description Test Conditions Min Max Units

VDD Power supply voltage – 3.135 3.6 V

VDDQ I/O supply voltage for 3.3 V I/O 3.135 VDD V

for 2.5 V I/O 2.375 2.625 V

VOH Output HIGH voltage for 3.3 V I/O, IOH = -4.0 mA 2.4 – V

for 2.5 V I/O, IOH = -1.0 mA 2.0 – V

VOL Output LOW voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V

for 2.5 V I/O, IOL = 1.0 mA – 0.4 V

VIH Input HIGH voltage [15] for 3.3 V I/O 2.0 VDD + 0.3 V V

for 2.5 V I/O 1.7 VDD + 0.3 V V

VIL Input LOW voltage [15] for 3.3 V I/O -0.3 0.8 V

for 2.5 V I/O -0.3 0.7 V

Notes

15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 19 of 31

IXInput leakage current except ZZ

and MODE

GND  VI  VDDQ –5 5 A

Input current of MODE Input = VSS –30 – A

Input = VDD –5A

Input current of ZZ Input = VSS –5 – A

Input = VDD –30A

IOZ Output leakage current GND  VI  VDDQ, Output Disabled –5 5 A

IDD VDD operating supply current VDD = Max.,

IOUT = 0 mA,

f = fMAX = 1/tCYC

7.5-ns cycle,

133 MHz

× 36 – 180 mA

ISB1 Automatic CE power down

current – TTL inputs

Max. VDD,

Device Deselected,

VIN  VIH or VIN  VIL,

f = fMAX,

inputs switching

7.5-ns cycle,

133 MHz

× 36 – 120 mA

ISB2 Automatic CE power down

current – CMOS inputs

Max. VDD,

Device Deselected,

VIN  VDD – 0.3 V or

VIN  0.3 V,

f = 0,

inputs static

7.5-ns cycle,

133 MHz

× 36 – 110 mA

ISB3 Automatic CE power down

current – CMOS inputs

Max. VDD,

Device Deselected,

VIN  VDDQ – 0.3 V or

VIN  0.3 V,

f = fMAX,

inputs switching

7.5-ns cycle,

133 MHz

× 36 – 120 mA

ISB4 Automatic CE power down

current – TTL inputs

Max. VDD,

Device Deselected,

VIN  VDD – 0.3 V or

VIN  0.3 V,

f = 0,

inputs static

7.5-ns cycle,

133 MHz

× 36 – 110 mA

Electrical Characteristics (continued)

Over the Operating Range

DC Characteristics (continued)

Over the Operating Range

Parameter [15, 16] Description Test Conditions Min Max Units

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 20 of 31

Capacitance

Parameter [17] Description Test Conditions 100-pin TQFP

Max

165-ball FBGA

Max Unit

CIN Input capacitance TA = 25C, f = 1 MHz,

VDD = 3.3V, VDDQ = 2.5 V

5 5 pF

CCLK Clock input capacitance 5 5 pF

CIO Input/output capacitance 5 5 pF

Thermal Resistance

Parameter [17] Description Test Conditions 100-pin TQFP

Package

165-ball FBGA

Package Unit

JC Thermal resistance

(junction to case)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51.

7.52 3.92 °C/W

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms

OUTPUT

R = 317



R = 351



5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

= 50



= 50



= 1.5V

3.3V ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

2 V/ns



1 ns

(c)

OUTPUT

R = 1667



R = 1538



5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

= 50



= 50



= 1.25V

2.5V ALL INPUT PULSES

DDQ

GND

90%

10%

90%

10%

2 V/ns



1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

Note

17. Tested initially and after any design or process change that may affect these parameters.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 21 of 31

Switching Characteristics

Over the Operating Range

Parameter [18, 19] Description –133 Unit

Min Max

tPOWER VDD (Typical) to the first Access[20] 1 – ms

Clock

tCYC Clock cycle time 7.5 –ns

tCH Clock HIGH 2.5 –ns

tCL Clock LOW 2.5 –ns

Output Times

tCDV Data Output Valid After CLK Rise –6.5 ns

tDOH Data Output Hold After CLK Rise 2.5 –ns

tCLZ Clock to Low Z[21, 22, 23] 2.5 –ns

tCHZ Clock to High Z[21, 22, 23] –3.8 ns

tOEV OE LOW to Output Valid –3.0 ns

tOELZ OE LOW to Output Low Z[21, 22, 23] 0 – ns

tOEHZ OE HIGH to Output High Z[21, 22, 23] –3.0 ns

Setup Times

tAS Address setup before CLK Rise 1.5 –ns

tADS ADSP, ADSC setup before CLK Rise 1.5 –ns

tADVS ADV setup before CLK Rise 1.5 –ns

tWES GW, BWE, BWX setup before CLK Rise 1.5 –ns

tDS Data input setup before CLK Rise 1.5 –ns

tCES Chip Enable setup 1.5 –ns

Hold Times

tAH Address Hold After CLK Rise 0.5 –ns

tADH ADSP, ADSC Hold After CLK Rise 0.5 –ns

tWEH GW, BWE, BWX Hold After CLK Rise 0.5 –ns

tADVH ADV Hold after CLK Rise 0.5 –ns

tDH Data Input Hold after CLK Rise 0.5 –ns

tCEH Chip Enable Hold after CLK Rise 0.5 –ns

Notes

18. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

20. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be

initiated.

21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 20. Transition is measured ± 200 mV from steady-state voltage.

22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z prior to Low Z under the same system conditions.

23. This parameter is sampled and not 100% tested.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 22 of 31

Timing Diagrams

Figure 4. Read Cycle Timing [24]

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Data Out (Q) High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ

BURST

READ

tOEV tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

ADV suspends burst

Deselect Cycle

DON’T CARE UNDEFINED

ADSP

ADSC

W, BWE,BW

ADV

Note

24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 23 of 31

Figure 5. Write Cycle Timing [25, 26]

Timing Diagrams (continued)

tCYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A1) D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for rst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

ADV

Data in (D)

ata Out (Q)

Notes

25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

26. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 24 of 31

Figure 6. Read/Write Cycle Timing [27, 28, 29]

Timing Diagrams (continued)

CYC

tCL

CLK

tADH

tADS

ADDRESS

tCH

tAH

tAS

tCEH

tCES

Single WRITE

D(A3)

A3 A4

BURST READ

Back-to-Back READs

High-Z

Q(A2) Q(A4) Q(A4+1)

Q(A4+2)

Q(A4+3)

tWEH

tWES

tOEHZ

tDH

tDS

tCDV

tOELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW X

ADV

Data In (D)

ata Out (Q)

Notes

27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

28. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.

29. GW is HIGH.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 25 of 31

Figure 7. ZZ Mode Timing [30, 31]

Timing Diagrams (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Notes

30. Device must be deselected when entering ZZ mode. See the Cycle Descriptions table for all possible signal conditions to deselect the device.

31. DQs are in high Z when exiting ZZ sleep mode.

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 26 of 31

Ordering Information

Tab le 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking

for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the

product summary page at http://www.cypress.com/products.

Ordering Code Definitions

Table 1. Ordering Information

Speed

(MHz) Ordering Code Package

Diagram Part and Package Type Operating

Range

133 CY7C1441KV33-133AXM 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Military

CY7C1441KV33-133BZM 51-85195 165-ball FBGA (15 × 17 × 1.4 mm)

Temperature range: X = M

M = Military Temp = –55 °C to +125 °C

X = Pb-free; X Absent = Leaded

Package Type: XX = A or BZ

A = 100-pin TQFP

BZ = 165-ball FBGA

Speed Grade: XXX = 133 MHz

33 = 3.3 V VDD

Process Technology: KV =65 nm

Part Identifier: 14XX = 1441

1441 = FT, 1M × 36 (36-Mbit)

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

C14XX XXX XXX

- X

CY 7KV 33

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 27 of 31

Package Diagrams

Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050

ș1

ș2

NOTE:

3. JEDEC SPECIFICATION NO. REF: MS-026.

2. BODY LENGTH DIMENSION DOES NOT

MOLD PROTRUSION/END FLASH SHALL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

BODY SIZE INCLUDING MOLD MISMATCH.

L11.00 REF

0.45 0.60 0.75

0.20

NOM.MIN.

0°

0.08

1.35 1.40

SYMBOL MAX.

7°

0.20

1.45

1.60

0.15

b0.22 0.30 0.38

e0.65 TYP

DIMENSIONS

R0.08

L20.25 BSC

0.05

0.20

INCLUDE MOLD PROTRUSION/END FLASH.

15.80 16.00 16.20

13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC

21.80 22.00 22.20

19.90 20.00 20.10

L30.20

0°ș1

11° 13°ș212°

51-85050 *G

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 28 of 31

Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195

Package Diagrams (continued)

51-85195 *D

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 29 of 31

Acronyms Document Conventions

Units of Measure

Table 2. Acronyms Used in this Document

Acronym Description

CE Chip Enable

CMOS Complementary Metal Oxide Semiconductor

FBGA Fine-Pitch Ball Grid Array

I/O Input/Output

JTAG Joint Test Action Group

NoBL No Bus Latency

OE Output Enable

SRAM Static Random Access Memory

TCK Test Clock

TDI Test Data-In

TDO Test Data-Out

TMS Test Mode Select

TQFP Thin Quad Flat Pack

WE Write Enable

Table 3. Units of Measure

Symbol Unit of Measure

°C degree Celsius

MHz megahertz

µA microampere

mA milliampere

ms millisecond

mm millimeter

ns nanosecond

pF picofarad

Vvolt

Wwatt

CY7C1441KV33

Document Number: 002-12701 Rev. *A Page 30 of 31

Document History Page

Document Title: CY7C1441KV33, Military Temperature, 36-Mbit (1M × 36) Flow-Through SRAM

Document Number: 002-12701

Revision ECN Orig. of

Change

Submission

Date Description of Change

** 5358795 PRIT 07/19/2016 New data sheet.

*A 6062265 CNX 02/07/2018 Updated Package Diagrams:

spec 51-85050 – Changed revision from *E to *G.

Updated to new template.

Document Number: 002-12701 Rev. *A Revised February 7, 2018 Page 31 of 31

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.

CY7C1441KV33

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

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