April 2016
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This is information on a product in full production.
www.st.com
STL33N65M2
N-channel 650 V, 0.124 Ω typ., 20 A MDmesh™ M2
Power MOSFET in a PowerFLAT™ 8x8 HV package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code
RDS(on)max
ID
STL33N65M2
650 V
0.154 Ω
20 A
Extremely low gate charge
Excellent output capacitance (COSS) profile
100% avalanche tested
Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET
developed using MDmesh™ M2 technology.
Thanks to its strip layout and an improved vertical
structure, the device exhibits low on-resistance
and optimized switching characteristics,
rendering it suitable for the most demanding high
efficiency converters.
Table 1: Device summary
Order code
Marking
Package
Packing
STL33N65M2
33N65M2
PowerFLAT™ 8x8 HV
Tape and reel
5
1
2
3
4
PowerFLAT™ 8x8 HV
Contents
STL33N65M2
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Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 PowerFLAT™ 8x8 HV package information .................................... 10
4.2 PowerFLAT™ 8x8 HV packing information ..................................... 12
5 Revision history ............................................................................ 14
STL33N65M2
Electrical ratings
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1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VGS
Gate-source voltage
± 25
V
ID
Drain current (continuous) at TC = 25 °C
20
A
ID
Drain current (continuous) at TC = 100 °C
12.6
A
IDM (1)
Drain current (pulsed)
80
A
PTOT
Total dissipation at TC = 25 °C
150
W
dv/dt (2)
Peak diode recovery voltage slope
15
V/ns
dv/dt (3)
MOSFET dv/dt ruggedness
50
V/ns
Tstg
Storage temperature range
- 55 to 150
°C
Tj
Operating junction temperature range
°C
Notes:
(1)Pulse width limited by safe operating area.
(2)ISD ≤ 20 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V.
(3)VDS ≤ 520 V.
Table 3: Thermal data
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case max
0.83
°C/W
Rthj-pcb (1)
Thermal resistance junction-pcb max
45
°C/W
Notes:
(1)When mounted on FR-4 board of inch², 2oz Cu.
Table 4: Avalanche characteristics
Symbol
Parameter
Value
Unit
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tjmax)
2.2
A
EAS
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V)
600
mJ
Electrical characteristics
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2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 5: On /off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 1 mA
650
V
IDSS
Zero gate voltage
drain current
VGS = 0 V, VDS = 650 V
1
µA
VGS = 0 V,
VDS = 650 V, TC=125 °C (1)
100
µA
IGSS
Gate-body leakage
current
VDS = 0 V, VGS = ± 25 V
±10
µA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
2
3
4
V
RDS(on)
Static drain-source
on- resistance
VGS = 10 V, ID = 10 A
0.124
0.154
Ω
Notes:
(1)Defined by design, not subject to production test.
Table 6: Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Input capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0
-
1790
-
pF
Coss
Output capacitance
-
75
-
pF
Crss
Reverse transfer
capacitance
-
2
-
pF
Coss eq.(1)
Equivalent output
capacitance
VDS = 0 to 520 V, VGS = 0
-
380
-
pF
Qg
Total gate charge
VDD = 520 V, ID = 24 A
VGS = 10 V
(see Figure 15: "Gate charge
test circuit")
-
41.5
-
nC
Qgs
Gate-source charge
-
6.8
-
nC
Qgd
Gate-drain charge
-
18
-
nC
Notes:
(1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS.
Table 7: Switching times
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
VDD = 325 V, ID = 12 A
RG = 4.7 Ω, VGS = 10 V
(see Figure 14: "Switching times
test circuit for resistive load" and
Figure 19: "Switching time
waveform")
-
13.5
-
ns
tr
Voltage rise time
-
11.5
-
ns
td(off)
Turn-off delay time
-
72.5
-
ns
tf
Current fall time
-
11.5
-
ns
STL33N65M2
Electrical characteristics
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Table 8: Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
ISD
Source-drain current
-
20
A
ISDM (1)
Source-drain current
(pulsed)
-
80
A
VSD (2)
Forward on voltage
ISD = 24 A, VGS = 0 V
-
1.6
V
trr
Reverse recovery
time
ISD = 24 A, di/dt = 100 A/µs
VDD = 60 V (see Figure 16: " Test
circuit for inductive load switching
and diode recovery times")
-
426
ns
Qrr
Reverse recovery
charge
-
7
µC
IRRM
Reverse recovery
current
-
33.5
A
trr
Reverse recovery
time
ISD = 24 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 16: " Test circuit for
inductive load switching and diode
recovery times")
-
544
ns
Qrr
Reverse recovery
charge
-
10
µC
IRRM
Reverse recovery
current
-
36.5
A
Notes:
(1)Pulse width limited by safe operating area.
(2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
Electrical characteristics
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2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
STL33N65M2
Electrical characteristics
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Figure 8: Capacitance variations
Figure 9: Output capacitance stored energy
Figure 10: Normalized gate threshold voltage vs
temperature
Figure 11: Normalized on-resistance vs temperature
Figure 12: Source-drain diode forward
characteristics
Figure 13: Normalized V(BR)DSS vs temperature
Test circuits
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3 Test circuits
Figure 14: Switching times test circuit for
resistive load
Figure 15: Gate charge test circuit
Figure 16: Test circuit for inductive load
switching and diode recovery times
Figure 17: Unclamped inductive load test
circuit
Figure 18: Unclamped inductive waveform
Figure 19: Switching time waveform
VGS
PW
VD
RG
RL
D.U.T.
2200
µF 3.3
µF VDD
GND2
(power)
GND1
(driver signal)
+
A
D
D.U.T.
SB
G
25Ω
AA
BB
RG
G
FAST
DIODE
D
S
L=100µH
µF
3.3 1000
µF VDD
GND1 GND2
D.U.T.
+
AM15858v1
Vi
Pw
VD
ID
D.U.T.
L
2200
µF 3.3
µF VDD
GND1 GND2
+
STL33N65M2
Package information
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4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package information
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4.1 PowerFLAT™ 8x8 HV package information
Figure 20: PowerFLAT™ 8x8 HV package outline
8222871_Rev_3_ A
STL33N65M2
Package information
DocID026089 Rev 3
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Table 9: PowerFLAT™ 8x8 HV mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.75
0.85
0.95
A1
0.00
0.05
A3
0.10
0.20
0.30
b
0.90
1.00
1.10
D
7.90
8.00
8.10
E
7.90
8.00
8.10
D2
7.10
7.20
7.30
E1
2.65
2.75
2.85
E2
4.25
4.35
4.45
e
2.00
L
0.40
0.50
0.60
Figure 21: PowerFLAT™ 8x8 HV footprint
All dimensions are in millimeters.
Package information
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4.2 PowerFLAT™ 8x8 HV packing information
Figure 22: PowerFLAT™ 8x8 HV tape
All dimensions are in millimeters.
Figure 23: PowerFLAT™ 8x8 HV package orientation in carrier tape
STL33N65M2
Package information
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Figure 24: PowerFLAT™ 8x8 HV reel
All dimensions are in millimeters.
Revision history
STL33N65M2
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5 Revision history
Table 10: Document revision history
Date
Revision
Changes
26-Jun-2013
1
First release.
23-Jul-2014
2
Text edits throughout document.
On cover page, updated title, features and description.
Updated Table 2: Absolute maximum ratings.
Updated Table 3: Thermal data.
Added Table 4: Avalanche characteristics.
Updated Table 5: On /off states.
Updated Table 6: Dynamic.
Updated Table 7: Switching times.
Updated Table 8: Source drain diode.
13-Apr-2016
3
Updated cover image and Figure 1: "Internal schematic diagram".
Updated Section 3: "Test circuits".
Added footnote in Table 5: "On /off states".
Removed footnote in Table 8: "Source drain diode".
Updated Section 4: "Package information".
Minor text changes.
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