RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
PACKAGE
•Single +5V power supply
•No clocks, no refresh
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prevents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current .......... 0.05µA(typ.)
APPLICATION
Small capacity memory units
DESCRIPTION
The M5M5256DFP,VP is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is fabricated using
high-performance 3 polysilicon CMOS technology. The use of
resistive load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough for battery back-up application. It is ideal for the memory
systems which require simple interface.
Especially the M5M5256DVP are packaged in a 28-pin thin small
outline package.
FEATURE
PIN CONFIGURATION (TOP VIEW)
1
20µA
(Vcc=5.5V)
(Vcc=5.5V)
5µA
(max) Stand-by
(max)
Active
(max)
Power supplycurrent
Type Access
time
50mA
M5M5256DFP,VP-55LL
M5M5256DFP,VP-70LL
55ns
70ns
M5M5256DFP,VP-55XL
M5M5256DFP,VP-70XL
55ns
70ns
(Vcc=3.0V,
Typical)
0.05µA
(Vcc=5.5V)
Outline 28P2C-A (VP)
Outline 28P2W-C (FP)
M5M5256DFP : 28 pin 450 mil SOP
M5M5256DVP : 28pin 8 X 13.4 mm TSOP
2
Oprating
Temperature
M5M5256DFP,VP-70LLI 70ns
0~70°C
-40~85°C
0~70°C
40µA
(Vcc=5.5V)
A14
A12
A6
A5
A4
A3
A2
A1
A0
A7
DQ1
DQ2
DQ3
GND
Vcc
A13
A8
A9
A11
A10
DQ8
DQ7
DQ6
DQ5
DQ4
/W
/OE
/S
28
26
25
24
23
21
18
17
16
15
27
22
20
19
1
2
4
5
6
7
8
9
10
3
11
12
13
14
M5M5256DVP
A14
A12
A6
A5
A4
A3
A7
A2
A1
A0
DQ1
DQ2
DQ3
GND
Vcc
A13
A8
A9
A11
/W
/OE A10
DQ7
DQ6
DQ5
DQ4
/S
DQ8
8
9
10
11
12
13
14
21
18
17
16
15
20
19
1
2
4
5
6
7
3
23
22
24
25
26
27
28
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
FUNCTION
FUNCTION TABLE
The operation mode of the M5M5256DFP,VP is
determined by a combination of the device control inputs
/S, /W and /OE. Each mode is summarized in the function
table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set
up before the write cycle and must be stable during the
entire cycle. The data is latched into a cell on the trailing
edge of /W, /S, whichever occurs first, requiring the set-
up and hold time relative to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high level,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cycle is eliminated.
Mode DQ Icc
/S /W /OE
Non selection
Write
Read
Stand-by
Active
Active
Active
High-impedance
DIN
DOUT
XX
L
L
L
LX
L
H
H
H
H
High-impedance
2
A read cycle is executed by setting /W at a high level
and /OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at
+2V power supply, enabling battery back-up operation
during power failure or power-down operation in the non-
selected mode.
VCC
(5V)
GND
(0V)
27
20
22
2
3
4
6
5
7
25
26
1
8
9
10
21
23
24
2
12
11
13
15
16
17
18
19
(512 ROWS X
512 COLUMNS)
32768 WORD
X 8BIT
GENERATOR
CLOCK
A 14
A 13
A 8
A 12
A 6
A 7
A 10
A 0
A 1
A 2
A 3
A 4
A 5
A 11
A 9
/W
/OE
/S
28
14
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
ADDRESS
INPUT
DATA I/O
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
CHIP SELECT
INPUT
BLOCK DIAGRAM
Note • "H" and "L" in this table mean VIH and VIL, respectively.
• "X" in this table should be "H" or "L".
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
3
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE ( Vcc=5V±10%, unless otherwise noted)
Symbol Parameter
Test conditions
pF
pF
Unit
Max
6
8
TypMin
Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance
Output capacitance
CI
CO
DC ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted)
Symbol Parameter
V
V
V
Limits
Test conditions
Unit
V
Note 0: Direction for current flowing into an IC is positive (no mark).
1: Typical value is one at Ta = 25°C.
2: CI, C O are periodically sampled and are not 100% tested.
mA
mA
V
Active supply current
(AC, MOS level )
Icc1
Icc2
Stand-by currentIcc4
VIH High-level input voltage
VIL Low-level input voltage
IOOutput current in off-state
Icc3Stand-by current
VOH1 High-level output voltage 1 IOH=-1mA
VOH2 High-level output voltage 2 IOH=-0.1mA
VOL Low-level output voltage IOL=2mA
IIInput current VI=0~Vcc
Vcc
+0.3
0.8
2.2
-0.3*
2.4
3
0.4
2
Vcc
-0.5
±1
4025
-LL,-LLI
-XL
MaxTypMin
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Unit
V
V
V
mW
Conditions
With respect to GND
Ta=25°C 700
0~70
-65~150
Ratings
Symbol
Vcc
VI
VO
Pd
Topr
Tstg
-0.3*~7.0
-0.3*~Vcc+0.3
0~Vcc
(Max 7.0)
/S=VIH,other inputs=0~Vcc
/S>Vcc-0.2V,
other inputs=0~Vcc
/S=VIH or or /OE=VIH, VI/O=0~Vcc
70ns
4530
55ns
mA
4525
/S=VIL,
70ns
5030
55ns
Active supply current
(AC, TTL level )
°C
±1
* -3.0V in case of AC ( Pulse width < 30ns )
_
/S<0.2V,
_
* -3.0V in case of AC ( Pulse width < 30ns )
_
_
°C
-LL,-XL
-LLI -40~85
Other inputs<0.2V or >Vcc-0.2V
Output-open
Output-open
other inputs=VIH or VIL
~25°C
1MHz
1MHz
µA
µA
µA
0.4
6-LL,-LLI
-XL
~40°C 1.2
20
-LLI
-XL
~70°C 5
~85°C
-LL,-LLI
40
0.1
42
84
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
4
(1) READ CYCLE
(2) WRITE CYCLE
Symbol Parameter
tCR Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
ta(A)
-70LL,-70LLI,
-70 XL
AC ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted )
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
MaxMin
55
5
5
10
Min
55
55
30
20
20
Max
-55LL, 55XL
70
5
5
10
70
70
35
25
25
Symbol Parameter Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
MaxMin
-70LL,-70LLI,
-70 XL
-55LL, -55XL
MaxMin
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
55
40
0
50
50
25
0
0
5
5
20
20
70
50
0
65
65
30
0
0
5
5
25
25
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
ten (W)
5
Read cycle
Write cycle (/W control mode)
(3) TIMING DIAGRAMS
DATA VALID
(Note 3) (Note 3)
ta(A)
ta (S)
tv (A)
tdis (S)
ta (OE)
ten (OE)
tdis (OE)
(Note 3) (Note 3)
tCR
th (D)tsu (D)
DQ1~8
/S tsu (S)
/OE
tsu (A-WH)
ten(OE)
tdis (OE)
(Note 3) (Note 3)
/W
tw (W) trec (W)tsu (A)
tdis (W)
tCW
ten (S)
/W = "H" level
A0~14
DQ1~8
/S
/OE
A0~14
DATA IN
STABLE
(Note 3) (Note 3)
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
6
Write cycle ( /S control mode)
tsu (S) trec (W)
th (D)
tCW
(Note 5)
(Note 3) (Note 3)
tsu (A)
(Note 4)
tsu (D)
DATA IN
STABLE
DQ1~8
/S
/W
A0~14
Note 3 : Hatching indicates the state is "don't care".
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
4 : Writing is executed in overlap of /S and /W low.
7 : ten, tdis are periodically sampled and are not 100% tested.
(4) MEASUREMENT CONDITIONS
Input pulse level .............. V IH=2.4V,VIL=0.6V
Input rise and fall time ..... 5ns
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.1 CL=50pF (-55LL,-55XL )
CL=100pF (-70LL,-70LLI,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Vcc
DQ
C
L
Fig.1 Output load
1.8kΩ
990Ω
(Including
scope and JIG)
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
7
(3) POWER DOWN CHARACTERISTICS
/S control mode
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted)
Power down set up time
Power down recovery time
(2) TIMING REQUIREMENTS ( Vcc=5V±10%, unless otherwise noted )
tsu (PD)
trec (PD)
Symbol
Parameter
ns
MaxTyp
Limits
Min
Test conditions
Unit
0
tCR ns
2.2V
tsu (PD) 4.5V
2.2V
trec (PD)
/S > Vcc-0.2V
Vcc
/S
Symbol
Parameter
V
V
MaxTyp
Limits
Min
Test conditions
Unit
V
2
1
-XL
Vcc (PD)
Icc (PD)
Power down supply voltage
Power down supply current
2.2
VI (/S) Chip select input /S
-LL,-LLI
4.5V
2.2V < VCC(PD)
2V< VCC(PD) < 2.2V VCC(PD)
_
_
_
Vcc = 3V, /S > Vcc-0.2V,
Other inputs=0~Vcc
_
_
0.2
µA
~25°C
3
-LL,-LLI 0.6
~40°C -XL 10
-LL,-LLI 2
~70°C -XL
-LLI
~85°C 20
0.05
RENESAS LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
REJ03C0055 © 2003 Renesas Technology Corp.
New publication, effective Feb 2004.
Specifications subject to change without notice
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