©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
RFD16N05L, RFD16N05LSM
16A, 50V, 0.047 Ohm, Logic Level,
N-Channel P ower MOSFETs
These are N-Channel logic level power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. Th ey were designed
for use with logic level (5V) driving sources in applications
such as programmable controllers, automotive switching,
s w it chi ng regu la tors, switchi ng co nverters, motor relay
drivers and emi tter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
Formerly developmental type TA09871.
Features
• 16A, 50V
•r
DS(ON) = 0.047Ω
• UIS SOA Rating Curve (Single Pulse)
• Design Optimized for 5V Gate Drives
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• Compatible with Automotive Drive Requirements
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linea r Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
RFD16N05L TO-251AA RFD16N05L
RFD16N05LSM TO-252AA RFD16N05LSM
NOTE: When ordering, include the entire part number . Add the suffix 9A
to obt ain th e TO-252AA variant in tape and reel, i.e . RF D16N 05LSM9A
G
D
S
JEDEC TO-251AA JEDEC TO-252AA
SOURCE
DRAIN (FLANGE)
GATE
DRAIN
GATE
SOURCE
DRAIN (FLANGE)
Data Sheet December 2003
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©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD16N05L,
RFD16N05LSM UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 50 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 50 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 16
45 A
A
Gate to Sou rc e Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
0.48 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Solder ing
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250mA, VGS = 0V, Figure 10 50 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250mA, Figure 9 1 - 2 V
Zero Gate Voltage Drain Current IDSS VDS = 40V, VGS = 0V - - 1 µA
TC = 150oC --50µA
Gate to Source Leakage Current IGSS VGS = ±10V, VDS = 0V - - 100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 16A, VGS = 5V - - 0.047 Ω
ID = 16A, VGS = 4V - - 0.056 Ω
Turn-On Time t(ON) VDD = 25V, ID = 8 A,
VGS = 5V, RGS = 12.5Ω
Figures 15, 16
--60ns
Turn-On Delay Time td(ON) -14 - ns
Rise Time tr-30 - ns
Turn-Off Delay Time td(OFF) -42 - ns
Fall Ti me tf-14 - ns
Turn-Off Time t(OFF) --100ns
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 40V,
ID = 16A,
RL = 2.5 Ω
Figures 17, 18
--80nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - - 45 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - - 3 nC
Thermal Resistance Junction to Case RθJC - - 2.083 oC/W
Thermal Resistance Junction to Ambient RθJA --100
oC/W
Sour ce to Drain Diode Specificatio ns
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 16A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 16A, dISD/dt = 100A/µs - - 125 ns
NOTES:
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
RFD16N05 L, RFD16N05LSM
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©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED PO WER DISSIP ATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA
(SING L E PULSE UIS SOA)
FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 TC, CASE TEMPERATURE (oC)
ID, DRAIN CURRENT (A)
025 50 75 100 150
5
10
20
125
15
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
0.1
102
1
ID, DRAIN CURRENT (A)
102
10
DC
1
OPERATION IN THIS AREA
LIMITED BY rDS(ON)
ID MAX CONTINUOUS
TC = 25oC
TJ = MAX RATED
10
102
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
1100.01 0.10
tAV = (L)( IAS)/(1.3 RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
Idm
0
15
30
0 1.5 3.0 4.5 7.5
45
IDS, DRAIN TO SOURCE CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 2V
VGS = 3V
VGS = 10V PULSE DURATION = 80µs
VGS = 5V
VGS = 4V
6.0
TC = 25oC
DUTY CYCLE = 0.5% MAX.
0 3.0 4.5 6.01.5
0
15
30
45
IDS(ON), DRAIN TO SOURCE ON CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE ( V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDS = 15V
RFD16N05 L, RFD16N05LSM
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©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
FIGURE 7. DRAIN TO SOURCE ON RESIST ANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION
TEMPERATURE FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERAT URE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. NORMALIZED SWITCHI NG W A VEF ORMS FOR
CONSTANT GATE CURRENT
Typical Performance Curves Unless Otherwise Specified (Continued)
V
GS
, GATE TO SOURCE VOLTA G E (V)
547
1.4
1.1
1.0
0.7
0.9
0.8
0.6
6
0.5
I
D
= 16V
1.2
1.3
NORMALIZED DRAIN TO SOURCE
V
DS
= 15V
ON RESISTANCE
PULSE DURATION = 80
µ
s
DUT Y CY CLE = 0.5% M AX.
0
2.5
1.5
0.5
-50 TJ, JUNCTION TEMPERATURE (oC)
2.0
1.0
050
NORMALIZED DRAIN TO SOURCE
100 200
ID = 16A
150
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
1.1
0.9
0.7
-50
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED GAT E
1.0
0.8
0.6 0 200
THRESHOLD VOLTAGE
50 100 150
1.2
1.3
1.4 ID = 250µA
VGS = VDS
1.4
1.0
0.8
50-50
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
1.2
0100 200
BREAKDOWN VOLTAGE
0150
ID = 250µA
0.6
0 10152025
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
2000
1600
1200
05
800
400
CISS
CRSS
COSS
VGS = 0V
f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
50
37.5
12.5
0
20IGREF()
IGACT()
-------------------------t, TI ME (µs) 80IGREF()
IGACT()
-------------------------
10
8
6
2
0
VDS, DRAIN T O SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE ( V)
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
DESCENDING ORDER:
RL = 3.125Ω, VGS = 5V
IG(REF) = 0.60mA
25
4
DRAIN SOURCE VOLTAGE
PLATEAU VOLTAGES IN
SOURCE
VOLTAGE
GATE
VDD = BVDSS VDD = BVDSS
RFD16N05 L, RFD16N05LSM
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©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
Test Circuits and Waveforms
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
FIGURE 15. SWITCHING TIME TEST CIRCUIT FIGURE 16. RESISTIVE SWITCHING WAV EFORMS
FIGURE 17. GATE CHARGE TEST CIRCUIT FIGURE 18. GATE CHARGE WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
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©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1
PSPICE Electrical Model
.SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92
Ca 12 8 3.33e-9
Cb 15 14 3.11e-9
Cin 6 8 1.21e-9
Dbody 7 5 DBDMOD
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD
Ebreak 11 7 17 18 70.9
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evto 20 6 18 8 1
IT 8 17 1
Lgate 1 9 1.38e-9
Ldrain 2 5 1.0e-12
Lsource 3 7 1.0e-9
Mos1 16 6 8 8 MOSMOD M=0.99
Mos2 16 21 8 8 MOSMOD M=0.01
Rin 6 8 1e9
Rbreak 17 18 RBKMOD 1
Rdrain 5 16 RDSMOD 27.38e-3
Rgate 9 20 2.98
Rsource 8 7 RDSMOD 0.614e-3
Rvto 18 19 RVTOMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 8 19 DC 1
Vto 21 6 0.448
.MODEL DBDMOD D (IS=1.34e-13 RS=1.21e-2 TRS1=1.64e -3 TRS2 =2.59e-6
+CJO=1.13e-9 TT=4.14e-8)
.MODEL DBKMOD D (RS=8.82e-2 TRS1=-2.01e-3 TRS2=7.32e-10)
.MODEL DPLCAPMOD D (CJO=0.522e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMO S (VTO=2. 054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.01e-3 TC 2=5.21e-8)
.MODEL RDSMOD RES (T C1=3.6 6e-3 TC2=1.46e-5)
.MODEL RVTOMOD RES (TC1=-1.81e-3 TC2=1.41e-6)
.MODEL S1AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25)
.MODEL S1BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25)
.MODEL S2AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35)
.MODEL S2BMOD VS WITCH(RO N=1e-5 ROF F=0.1 VON=4.35 VOFF =-0.65)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPI CE Sub-Circuit for the Power MOSFE T Fe a t uring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatle y.
EVTO
+
13
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
DPLCAP
6
10 5
16
21
8
14
73
17 18
19
2
+
+
+
RDRAIN
ESCL
RSCL1
RSCL2 51
50
+
S1A S2A
S2BS1B
12 15
13
814
13
6
8
+
-
5
8
-
-
18
8
RGATE
GATE
LGATE
209
1
ESG +
-6
811 +
-
17
18
5
51
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS P ATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF F AIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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