36-Mbit QDR-II™ SRAM 2-Word Burst
Architecture
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05615 Rev. *C Revised June 26, 2006
Features
• Separate Independent Read and Write data ports
— Supports concurrent transactions
• 250-MHz clock for hig h ba ndwid th
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output dat a (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
•Core V
DD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non lead-free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1410AV18 – 4M x 8
CY7C1425AV18 – 4M x 9
CY7C1412AV18 – 2M x 18
CY7C1414AV18 – 1M x 36
Functional Description
The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and
CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of the K clock. Accesses to the QDR-II Read
and Write ports are completely independent of one another . In
order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (D DR) interfaces. Each
address location is associated with two 8-bit words
(CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit
words (CY7C1412AV18) or 36-bit words (CY7C1414AV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clo ck
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Operating Frequency 250 200 167 MHz
Maximum Operating Current 1065 870 740 mA
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 2 of 25
Logic Block Diagram (CY7C1410AV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
21
8
16
8
NWS[1:0]
VREF
Write Add. Decode
8
A(20:0)
21
C
C
8
2M x 8 Array
2M x 8 Array
Write
Reg Write
Reg
CQ
CQ
8
DOFF
Logic Block Diagram (CY7C1425AV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Da ta Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
9
18
9
BWS[0]
VREF
Write Add. Decode
9
A(20:0)
21
C
C
9
2M x 9 Array
2M x 9 Array
Write
Reg Write
Reg
CQ
CQ
9
DOFF
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 3 of 25
Logic Block Diagram (CY7C1412AV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
18
36
18
BWS[1:0]
VREF
Write Add. Decode
18
A(19:0)
20
C
C
18
1M x 18 Array
1M x 18 Array
Write
Reg Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1414AV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
36
72
36
BWS[3:0]
VREF
Write Add. Decode
36
A(18:0)
19
C
C
36
512K x 36 Array
512K x 36 Array
Write
Reg Write
Reg
CQ
CQ
36
DOFF
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 4 of 25
Pin Configurations
CY7C14 10 AV18 (4 M x 8)
234567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M ANWS1 K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC A NC/288M KNWS0
VSS AAA
NC VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q4
NC
VDDQ
NC
NC
NC
NC
Q7
A
VDDQ VSS
VDDQ VDD VDD
Q5 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
C
VSS
A A
A
D4 VSS
NC VSS
NC
NC VREF
VSS VDD
VSS VSS
A
VSS
C
NC Q6
NC D7
D6
VDD
A
891011
NC
AA
RPS CQ
A NC NC Q3
VSS NC NC D3
NC
VSS NC Q2
NC
NC
NC
VREF
NC NC
VDDQ NC
VDDQ NC NC
VDDQ VDDQ
VDDQ D1VDDQ NC Q1
NC
VDDQ
VDDQ NC
VSS NC D0
NC
TDITMS
VSS
ANC
A
NC
D2
NC ZQ
NC Q0
NC
NC
NC
NC
A
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1425AV18 (4M x 9)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M
ANCKWPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D6
NC
NC
NC
TCK
NC
NC A NC/288M KBWS0
VSS AAA
NC VSS
VSS VSS VSS
VDD
A
VSS
VSS
VSS
VDD
Q5
NC
VDDQ
NC
NC
NC
NC
Q8
A
VDDQ VSS
VDDQ VDD VDD
Q6 VDDQ VDD
VDDQ VDD
VDDQ VDD VSS
VDD
VDDQ
VDDQ VSS
VSS VSS VSS
A
A
C
VSS
A A
A
D5 VSS
NC VSS
NC
NC VREF
VSS VDD
VSS VSS
A
VSS
C
NC Q7
NC D8
D7
VDD
A
891011
Q0
AARPS CQ
A NC NC Q4
VSS NC NC D4
NC
VSS NC Q3
NC
NC
NC
VREF
NC NC
VDDQ NC
VDDQ NC NC
VDDQ VDDQ
VDDQ D2VDDQ NC Q2
NC
VDDQ
VDDQ NC
VSS NC D1
NC
TDITMS
VSS
ANC
A
NC
D3
NC ZQ
NC Q1
NC
NC
D0
NC
A
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 5 of 25
Pin Configurations (continued)
CY7C1412AV18 (2M x 18)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M A BWS
1
KWPS NC/288M
Q9 D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10 A NC KBWS
0
V
SS
AAA
Q10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q11
D12
V
DDQ
D14
Q14
D16
Q16
Q17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
C
V
SS
A A
A
D11 V
SS
NC V
SS
Q12
NC V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
NC Q15
NC D17
D15
V
DD
A
891011
Q0
A NC/72MRPS CQ
A NC NC Q8
V
SS
NC Q7 D8
NC
V
SS
NC Q6
D5
NC
NC
V
REF
NC Q3
V
DDQ
NC
V
DDQ
NC Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
NC Q4
NC
V
DDQ
V
DDQ
NC
V
SS
NC D2
NC
TDITMS
V
SS
ANC
A
D7
D6
NC ZQ
D3 Q2
D1
Q1
D0
NC
A
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
234567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
NC/288M NC/72M BWS
2
KWPS BWS
1
Q18 D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19 A BWS
3
KBWS
0
V
SS
AAA
Q19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q20
D21
V
DDQ
D23
Q23
D25
Q25
Q26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
C
V
SS
A A
A
D20 V
SS
Q29 V
SS
Q21
D30 V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
C
Q32 Q24
Q35 D26
D24
V
DD
A
891011
Q0
A NC/144MRPS CQ
A D17 Q17 Q8
V
SS
D16 Q7 D8
Q16
V
SS
D15 Q6
D5
D9
Q14
V
REF
Q11 Q3
V
DDQ
Q15
V
DDQ
D14 Q5
V
DDQ
VDDQ
V
DDQ
D4V
DDQ
D12 Q4
Q12
V
DDQ
V
DDQ
D11
V
SS
D10 D2
Q10
TDITMS
V
SS
AQ9
A
D7
D6
D13 ZQ
D3 Q2
D1
Q1
D0
Q13
A
CY7C1414AV18 (1M x 36)
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 6 of 25
Pin Definitions
Pin Name I/O Pin Description
D[x:0] Input-
Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1410AV18 - D[7:0]
CY7C1425AV18 - D[8:0]
CY7C1412AV18 - D[17:0]
CY7C1414AV18 - D[35:0]
WPS Input-
Synchronous Write Port Select, active LOW. Sampled on the rising edge of the K cloc k. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
NWS0,NWS1Nibble Write Select 0, 1 − active LOW. (CY7C1410A V18 Only) Sampled on the rising
edge of the K and K clocks during Write operations. Used to select which nibble is written
into the device during the curre nt portion of the Write operations.Nibbles not written
remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selects
are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause
the corresponding nibble of data to be ignored and not written into the device.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous Byte Wri te Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1425AV18 − BWS0 controls D[8:0]
CY7C1412AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9].
CY7C1414AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18]
and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A Input-
Synchronous Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write
address) clocks during active Read and Write operations. These address inputs are
multiplexed for both Read and Write operations. Internally , the device is organized as 4M
x 8 (2 arrays each of 2M x 8) for CY7C1410AV18, 4M x 9 (2 arrays each of 2M x 9) for
CY7C1425AV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412AV18 and 1M x 36
(2 arrays each of 512K x 36) for CY7C1414A V18. Therefore, only 21 address inputs are
needed to access the entire memory array of CY7C1410A V18 and CY7C1425AV18, 20
address inputs for CY7C1412AV18 and 19 address inputs for CY7C1414AV18. These
inputs are ignored when the appropriate port is deselected.
Q[x:0] Outputs-
Synchronous Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically tri-stated.
CY7C1410AV18 − Q[7:0]
CY7C1425AV18 − Q[8:0]
CY7C1412AV18 − Q[17:0]
CY7C1414AV18 − Q[35:0]
RPS Input-
Synchronous Read Port Select, a ctive LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two seque nt i al tra nsf ers.
C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller . See application example for further
details.
CInput-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the
Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller . See application example for further
details.
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 7 of 25
Functional Overview
The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18 and
CY7C1414AV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1410AV18, two 9-bit data transfers in the case of
CY7C1425AV18,two 18-bit data transfers in the case of
CY7C1412AV18 and two 36-bit data transfers in the case of
CY7C1414AV18, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the in put clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1412AV18 is described in the following sections. The
same basic descriptions apply to CY7C1410AV18,
CY7C1425AV18, and CY7C1414AV18.
K Input-Clock Positive Input Cloc k Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
KInput-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[x:0] when in single clock mode.
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are s hown in the AC Timing
table.
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized
to the Input clock for output data (C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K. The timings for the echo clocks are shown in the AC T iming
table.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ , and Q[x:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected be tween ZQ and ground. Alternately, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin
cannot be connected directly to GND or left unconnected.
DOFF Input DLL T urn Off, active LOW . Connecting this pin to ground will turn off the DLL inside the
device. The timings in the DLL turned off operation will be different from those listed in
this data sheet.
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
VREF Input-
Reference Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name I/O Pin Description
[+] Feedback
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 8 of 25
Read Operations
The CY7C1412AV18 is organized internally as 2 arrays of
1Mx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Po sitive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corre-
sponding lowest order 18-bit word of data is driven onto the
Q[17:0] usin g C as the output timing refe rence. On the subse-
quent rising edge of C, the next 18-bit data word is driven onto
the Q[17:0]. The requested data will be valid 0.45 ns from the
rising edge of the output clock (C and C or K and K wh en in
single clock mode).
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the infor-
mation presented to D[17:0] is stored into the Write Data
register provided BWS[1:0] are both asserted active. The 36
bits of data are then written into the memory array at the
specified location. When desele cted, the w r ite port will ignore
all inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1412AV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each 18-bit data
word. Asserting the appropriate Byte Write Select input during
the data portion of a Write will allow the data being presented
to be latched and written into the device. Deasserting the Byte
Write Select input during the data portion of a write will al low
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify Read/Modify/Write opera-
tions to a Byte Write operation.
Single Clock Mode
The CY7C1412AV18 can be used with a single clock that
controls both the i nput and o utput registers. In thi s mode, the
device will recogn ize only a singl e pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same i n thi s mo de . To use this mode of op e r a ti on,
the user must tie C and C HIGH a t power on. This fu nction is
a strap option and not alterable during device operation.
Concurrent Transaction s
The Read and Write ports on the CY7C1412AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Depth Expansion
The CY7C1412AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V.The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respe ct to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
(C/C) of the QDR-II. In the single clock mode, CQ is generated
with respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency . During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
[+] Feedback
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CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
Document #: 38-05615 Rev. *C Page 9 of 25
Application Example[1]
Truth Table[2, 3, 4, 5, 6, 7]
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K clock; input
write data on K and K rising edges.
L-H X L D(A + 0) at K(t) ↑D(A + 1) at K(t) ↑
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
L-H L X Q(A + 0) at C(t + 1) ↑Q(A + 1) at C(t + 2) ↑
NOP: No Operation L-H H H D = X
Q = High-Z D = X
Q = High-Z
Standby: Clock S topped Stopped X X Previous State Previous State
Write Cycle Descriptions (CY7C1410AV18 and CY7C14 12AV18) [2, 8]
BWS0/NWS0BWS1/NWS1KK Comments
L L L-H – During the Data portion of a Write sequence:
CY7C1410AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1412AV18 − both bytes (D[17:0]) are written into the device.
L L – L-H During the Data portion of a Write sequence:
CY7C1410AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1412AV18 − both bytes (D[17:0]) are written into the device.
L H L-H – During the Data portion of a Write sequence:
CY7C1410AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1412AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address locat i on latched by the devices when transaction was initiated. A + 00, A + 01 represents th e i nternal address sequence in the burst.
5. “t” represents the cycl e at which a Read/Writ e operation is started. t + 1 and t + 2 are the first and secon d clock cycles respectively succee ding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode .
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcomin g transmission line
charging symmetrically.
8. Assumes a Write cycl e was initiated per the W rite Port Cycl e Description T rut h Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be al tered on dif ferent
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Vt = Vddq/2
CC#
D
AKCC#
D
AK
BUS
MASTER
(CPU
or
ASIC)
SRAM #1 SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K# R = 50οηµσ
R = 250οηµσ
R = 250οηµσ
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#
[+] Feedback
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CY7C1425AV18
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Document #: 38-05615 Rev. *C Page 10 of 25
L H – L-H During the Data portion of a Write sequence:
CY7C1410AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1412AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
H L L-H – During the Data portion of a Write sequence:
CY7C1410AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1412AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H L – L-H During the Data portion of a Write sequence:
CY7C1410AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1412AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H H L-H – No data is written into the devices during this portion of a Write operation.
H H – L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions (CY7C1414AV18) [2, 8]
BWS0BWS1BWS2BWS3KK Comments
L L L L L-H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L L L L – L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L H H H L-H – During the Data portion of a Write sequence, only the lower byte (D[8:0])
is written into the device. D[35:9] will remain unaltered.
L H H H – L-H During the Data portion of a Write sequence, only the lower byte (D[8:0])
is written into the device. D[35:9] will remain unaltered.
H L H H L-H – During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltere d.
H L H H – L-H During the Data portion of a Wri te sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltere d.
H H L H L-H – During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H H L H – L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H H H L L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H H H L – L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H H H H L-H – No data is written into the device during this portion of a Write operation.
H H H H – L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions (CY7C1425AV18)
BWS0KK Comments
L L-H – During the Data portion of a Write sequence:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
L – L-H During the Data portion of a Write sequence:
CY7C1425AV18 - the single byte (D[8:0]) is written into the device
H L-H – No data is written into the devices during this portion of a Write operation.
H – L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions (CY7C1410AV18 and CY7C1412AV18 ) (contin ued)[2, 8]
BWS0/NWS0BWS1/NWS1KK Comments
[+] Feedback
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CY7C1425AV18
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CY7C1414AV18
Document #: 38-05615 Rev. *C Page 11 of 25
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected i f the TAP is n ot used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loa ded into th e TAP instruction register. Fo r
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internall y pulled up and can
be unconnected if the TAP is unused in an a ppli cation. TDI i s
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected betwe en the TDI and TD O pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one registe r can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Da ta is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed be tween the
TDI and TDO pins as shown in T AP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level seri al test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is mo ved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
[+] Feedback
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CY7C1425AV18
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CY7C1414AV18
Document #: 38-05615 Rev. *C Page 12 of 25
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the T AP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the T AP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during th e Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee th at the boundary scan regi ster will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's ca pture set-up plus
hold times (tCS and tCH). The SR AM clock input migh t not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still p ossible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register .
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit
#108. When this scan cell, called the “extest output bus
tri-state,” is latched into the preload register during the
“Update-DR” state in the TAP controller, it will directly control
the state of the output (Q-bus) pins, when the EXTEST is
entered as the current instruction. When HIGH, it will enable
the output buffers to drive the output bus. When LOW, this bit
will place the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desire d bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST i nstruction is en tered, thi s bit will
directly control the output Q-bus pins. Note that this bit is
pre-set LOW to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
[+] Feedback
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CY7C1414AV18
Document #: 38-05615 Rev. *C Page 13 of 25
Note:
9. The 0/1 next to each state re presents the value at TMS at the rising edge of TCK.
TAP Controller State Diagram[9]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
01
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
[+] Feedback
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Document #: 38-05615 Rev. *C Page 14 of 25
TAP Controller Block Diagram
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.
106
012
Instruction Register
Bypass Register
Selection
Circuitry Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
TAP Electrical Characteristics Over the Operating Range[15, 18, 10]
Parameter Description Test Conditi on s Min. Max. Unit
VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V
VOH2 Output HIGH Voltage IOH = −100 µA1.6 V
VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V
VOL2 Output LOW Voltage IOL = 100 µA0.2V
VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V
VIL Input LOW Voltage –0.3 0.35VDD V
IXInput and OutputLoad Current GND ≤ VI ≤ VDD −55µA
Note:
10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Chara cteristics table.
[+] Feedback
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Document #: 38-05615 Rev. *C Page 15 of 25
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter Description Min. Max. Unit
tTCYC TCK Clock Cycle Time 50 ns
tTF TCK Clock Frequency 20 MHz
tTH TCK Clock HIGH 20 ns
tTL TCK Clock LOW 20 ns
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise 5 ns
tTDIS TDI Set-up to TCK Clock Rise 5 ns
tCS Capture Set-up to TCK Rise 5 ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 ns
tTDIH TDI Hold after Clock Rise 5 ns
tCH Capture Hold after Clock Rise 5 ns
Output Times
tTDOV TCK Clock LOW to TDO Valid 10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 ns
TAP Timing and Test Conditions[12]
Notes:
11. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
12.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
(a)
TDO
CL= 20 pF
Z0= 50Ω
GND
0.9V
50Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data-In
TDI
Test Data-Out
tTCYC
tTMSH
tTL
tTH
tTMSS
tTDIS tTDIH
tTDOV tTDOX
TDO
[+] Feedback
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Document #: 38-05615 Rev. *C Page 16 of 25
Identification Register Definitions
Instruction Field Value DescriptionCY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18
Revision Number
(31:29) 000 000 00 0 000 Version number.
Cypress Device ID
(28:12) 11010011010000111 11010011010001111 11010011010010111 11010011010100111 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1) 00000110100 00000110100 00000110100 00000110100 Unique identifi-
cation of SRAM
vendor.
ID Register Presence
(0) 1 1 1 1 Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan Cells 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan regi ster
between TDI and TDO. Fo rces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Doe s not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
[+] Feedback
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Document #: 38-05615 Rev. *C Page 17 of 25
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P 29 9G 57 5B 85 2J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N329F605C882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H
[+] Feedback
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Document #: 38-05615 Rev. *C Page 18 of 25
Power-Up Sequence in QDR-II SRAM[13, 14 ]
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-Up Sequence
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
—Apply V
DD before VDDQ
—Apply V
DDQ before VREF or at the same time as VREF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock.
DLL Constraints
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var.
• The DLL will function at frequencies down to 80MHz.
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior.
Notes:
13.It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
14.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Power-up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stable(< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
K
K
DDQ
DD
VV
/DDQ
DD
VV
/
Clock Start (Clock Starts after Stable)
DDQ
DD
VV
/
~
~
~
~
Unstable Clock
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Document #: 38-05615 Rev. *C Page 19 of 25
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...........................................––55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND......–0.5V to +VDD
DC Voltage Applied to Outputs
in High-Z State.................................... –0.5V to VDDQ + 0.3V
DC Input V oltage[18]...............................–0.5V to VDD + 0.3V
Current into Outputs (LOW).........................................20 mA
Static Discharge V o ltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current............... ... ... ................. ... ... ........ > 200 mA
Operating Range
Range Ambient
Temperatu r e (TA)V
DD[19] VDDQ[19]
Com’l 0°C to +70°C 1.8 ± 0.1V 1.4V to VDD
Ind’l –40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 19]
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VDD Power Supply Voltage 1.7 1.8 1.9 V
VDDQ I/O Supply Voltage 1.4 1.5 VDD V
VOH Output HIGH Voltage Note 16 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOL Output LOW Voltage Note 17 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V
VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VSS 0.2 V
VIH Input HIGH Voltage[18] VREF + 0.1 VDDQ+0.3 V
VIL Input LOW Voltage[18] –0.3 VREF – 0.1 V
IXInput Leakage Current GND ≤ VI ≤ VDDQ −55µA
IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −55µA
VREF Input Reference Voltage[20] Typical Value = 0.75V 0.68 0.75 0.95 V
IDD VDD Operating Supply VDD = Max., IOUT = 0
mA, f = fMAX = 1/tCYC 167 MHz 740 mA
200 MHz 870 mA
250 MHz 1065 mA
ISB1 Automatic Power-down
Current Max. VDD, Both Ports
Deselected, VIN ≥ VIH
or VIN ≤ VIL, f = fMAX =
1/tCYC, Inputs Static
167 MHz 270 mA
200 MHz 300 mA
250 MHz 350 mA
AC Input Requirements Over the Operating Range
Parameter Description Test Conditions Min. Typ. Max. Unit
VIH Input High (Logic 1) Voltage VREF + 0.2 – – V
VIL Input Low (Log ic 0) Voltage – – VREF – 0.2 V
Capacitance[21]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK Clock Input Capacitance 4 pF
COOutput Capacitance 5 pF
Notes:
15.All voltage referenced to Ground.
16.Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) fo r values of 175Ω <= RQ <= 350Ωs.
17.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
18.Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undersh oot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
19.Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH< VDD and VDDQ< VDD.
20.VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
21.Tested initially and after any design or process change that may affect these parameters.
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Document #: 38-05615 Rev. *C Page 20 of 25
Thermal Resistance[21]
Parameter Description Test Conditions 165 FBGA
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
17.2 °C/W
ΘJC Thermal Resistance
(Junction to Case) 3.2 °C/W
AC Test Loads and Waveforms
Note:
22.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of t he specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
1.25V
0.25V
R = 50Ω
5pF
ALL INPUT PULSES
Device RL= 50Ω
Z0= 50Ω
VREF = 0.75V
VREF = 0.75V
[22]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
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Document #: 38-05615 Rev. *C Page 21 of 25
Switching Characteristics Over the Operating Range [22, 23]
Cypress
Parameter Consortium
Parameter Description
250 MHz 200 MHz 167 MHz
UnitMin. Max. Min. Max. Min. Max.
tPOWER VDD(Typical) to the first Access [26] 111ms
tCYC tKHKH K Clock and C Clock Cycle T ime 4.0 6.3 5.0 7.9 6.0 8.4 ns
tKH tKHKL Input Clock (K/K and C/C) HIGH 1.6 – 2.0 – 2.4 – ns
tKL tKLKH Input Clock (K/K and C/C) LOW 1.6 – 2.0 – 2.4 – n s
tKHKHtKHKHK Clock Rise to K Clock Rise and C to C Rise
(rising edge to rising edge) 1.8 – 2.2 – 2.7 – ns
tKHCH tKHCH K/K Clock Rise to C/C Clock Rise (rising edge
to rising edge) 0.0 1.8 0.0 2.2 0.0 2.7 ns
Set-up Times
tSA tAVKH Address Set-up to K Clock Rise 0.35 – 0.4 – 0.5 – ns
tSC tIVKH Control Set-up to K Clock Rise (RPS, WPS) 0.35 – 0.4 – 0.5 – ns
tSCDDR tIVKH Double Data Rate Control Set-up to Clock
(K, K) Rise (BWS0, BWS1, BWS3, BWS4)0.35 – 0.4 – 0.5 – ns
tSD tDVKH D[X:0] Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Hold Times
tHA tKHAX Address Hold after K Clock Rise 0.35 – 0.4 – 0.5 – ns
tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.35 – 0.4 – 0.5 – ns
tHCDDR tKHIX Double Data Rate Control Hold after Clock
(K, K) Rise (BWS0, BWS1, BWS3, BWS4)0.35 – 0.4 – 0.5 – ns
tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Output Times
tCO tCHQV C/C Clock Rise (or K/K in Single Clock Mode)
to Data Valid –0.45–0.45–0.50ns
tDOH tCHQX Data Output Hold after Output C/C Clock Rise
(Active to Active) –0.45 – –0.45 – -0.50 – ns
tCCQO tCHCQV C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.50 ns
tCQOH tCHCQX Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – –0.50 – ns
tCQD tCQHQV Echo Clock High to Data Valid – 0.30 – 0.35 – 0.40 ns
tCQDOH tCQHQX Echo Clock High to Data Invalid –0.30 – –0.35 – –0.40 – ns
tCHZ tCHQZ Clock (C/C) Rise to High-Z
(Active to High-Z)[24,25] –0.45–0.45–0.50ns
tCLZ tCHQX1 Clock (C/C) Rise to Low-Z[24,25] –0.45 – –0.45 – –0.50 – ns
DLL Timing
tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock DLL Lock Time (K, C) 1024 – 1024 – 1024 – cycles
tKC Reset tKC Reset K Static to DLL Reset 30 – 30 – 30 – ns
Notes:
23.All devices can operate at clock frequencies as low as 119 MHz. When a p art with a maximum freq uency above 133 MHz is operatin g at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
25.At any given voltage and te mperature tCHZ is less than tCLZ and tCHZ less than tCO.
26.This part has a volt age r egul ato r in ternally; tPOWER is th e time that the power needs to be su pplied above VDD minimum initiall y before a read or write operation
can be initiated.
27.For D2 data signal on CY7C1425AV18 device, tSD is 0.5 ns for 200 MHz, and 250 MHz frequencies.
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Document #: 38-05615 Rev. *C Page 22 of 25
Switching Waveforms[28, 29, 30]
Read/Write/Deselect Sequence
Notes:
28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29.Output are disabled (High-Z) one clock cycle after a NOP.
30.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
K
12
34 58
10
67
K
RPS
WPS
A
D
READ READ WRITE WRITEWRITE NOPREAD WRITE NOP
9
A0
tKH tKHKH
tKL tCYC
tt
HC
tSA tHA
tSD tHD
SC t
tSA tHA
tSD tHD
A6A5
A3 A4
A1 A2
D30 D50 D51 D61
D31
D11D10 D60
Q
C
C
DON’T CARE UNDEFINED
t
CQ
CQ
tKHCH
tCO
tKHCH
tCLZ CHZ
tKH
tKL
Q00 Q01 Q20
tKHKH tCYC
Q21 Q40 Q41
tCQD
tDOH
tCCQO
tCQOH
tCCQO
tCQOH
tCQDOH
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Document #: 38-05615 Rev. *C Page 23 of 25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
167 CY7C1410AV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1425AV18-167BZC
CY7C1412AV18-167BZC
CY7C1414AV18-167BZC
CY7C1410AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-167BZXC
CY7C1412AV18-167BZXC
CY7C1414AV18-167BZXC
CY7C1410AV18-167BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1425AV18-167BZI
CY7C1412AV18-167BZI
CY7C1414AV18-167BZI
CY7C1410AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-167BZXI
CY7C1412AV18-167BZXI
CY7C1414AV18-167BZXI
200 CY7C1410AV18-200BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1425AV18-200BZC
CY7C1412AV18-200BZC
CY7C1414AV18-200BZC
CY7C1410AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-200BZXC
CY7C1412AV18-200BZXC
CY7C1414AV18-200BZXC
CY7C1410AV18-200BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1425AV18-200BZI
CY7C1412AV18-200BZI
CY7C1414AV18-200BZI
CY7C1410AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-200BZXI
CY7C1412AV18-200BZXI
CY7C1414AV18-200BZXI
250 CY7C1410AV18-250BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1425AV18-250BZC
CY7C1412AV18-250BZC
CY7C1414AV18-250BZC
CY7C1410AV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-250BZXC
CY7C1412AV18-250BZXC
CY7C1414AV18-250BZXC
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Document #: 38-05615 Rev. *C Page 24 of 25
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wit hou t n otice. Cypress Semiconductor Corporation assumes no responsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT , NEC, and Samsung
technology. All product and company names mentioned in this document are the trademarks of their respective holders.
250 CY7C1410AV18-250BZI 51-85195 165-ball Fi ne Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1425AV18-250BZI
CY7C1412AV18-250BZI
CY7C1414AV18-250BZI
CY7C1410AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1425AV18-250BZXI
CY7C1412AV18-250BZXI
CY7C1414AV18-250BZXI
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please cont act your local sales represent ative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
Package Diagram
!
0).#/2.%2
¼
¼
8
-#!"
-#
"
!
8
¼
-!8
3%!4).'0,!.%
¼
#
#
0).#/2.%2
4/06)%7 "/44/-6)%7
"
#
$
%
&
'
(
*
+
,
-
.
0
2
0
2
+
-
.
,
*
(
'
&
%
$
#
"
!
#
3/,$%20!$490%./.3/,$%2-!3+$%&).%$.3-$
./4%3
0!#+!'%7%)'(4G
*%$%#2%&%2%.#%-/$%3)'.#
0!#+!'%#/$%""!$
165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)
51-85195-*A
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Document #: 38-05615 Rev. *C Page 25 of 25
Document History Page
Document Title: CY7C1410AV18/CY7C1425AV18/CY7C1412AV18/CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word
Burst Architecture
Document Number: 38-05615
REV. ECN No. Issue Date Orig. of
Change Description of Cha nge
** 247331 See ECN SYT New Data Sheet
*A 326519 See ECN SYT Removed CY7C1425AV18 from the title
Included 300 MHz Speed grade
Replaced TBDs with their respective va lues for IDD and ISB1
Added Industrial temperature grade
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W
and ΘJC = 3.2°C/W
Replaced TBDs in the Capacitance Table to their respective values for the
165 FBGA Package
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS
TRI-STATE on Page 16
Added lead-free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B 413953 See ECN NXR Converted from preliminary to final.
Added CY7C1425AV18 part number to title.
Removed 300-MHz speed Bin.
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C, C Description in Featu re Section and Pin Description.
Added Power-up sequence and Wave form on page# 19
Added foot notes # 13, 14, 15 on page# 19
Replaced Three-state with Tri-state.
Changed the description of IX from Input Loa d Current to Input Leakage
Current on page# 20
Modified the IDD and ISB values.
Modified test condition in Footnote # 20 on page# 20 from VDDQ < VDD to
VDDQ < VDD.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated Ordering Information Table.
*C 468029 See ECN NXR Modified the ZQ Definition from Alternately , this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ.
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,
tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP
AC Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Changed the tSC and tHC value for 250 MHz from 0.5 ns to 0.35 ns,
for 200 MHz from 0.6 ns to 0.4 ns, and for 167 MHz from 0.7 ns to 0.5 ns.
Modified AC Switching Waveform.
Corrected the typo In the AC Switching Characteristics Table.
Updated the Ordering Information Table.
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