ADL5331ACPZ-R7 - Analog Devices - Datasheet.Directory

1 MHz to 1.2 GHz VGA with

30 dB Gain Control Range

ADL5331

Rev. 0

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FEATURES

Voltage-controlled amplifier/attenuator

Operating frequency: 1 MHz to 1.2 GHz

Optimized for controlling output power

High linearity: OIP3 47 dBm @ 100 MHz

Output noise floor: −149 dBm/Hz @ maximum gain

Input impedance: 50 Ω

Output impedance: 20 Ω

Wide gain-control range: 30 dB

Linear-in-dB gain control function: 40 mV/dB

Single-supply voltage: 4.75 V to 5.25 V

APPLICATIONS

Transmit and receive power control at RF and IF

CATV distribution

FUNCTIONAL BLOCK DIAGRAM

INLO

VPS1

COM1

INHI

COM2

OPLO

OPHI

IPBS

GAIN

CONTROL

BIAS

AND

VREF

GAIN

COM2

RFOUT

COM2

VPS2

COM1

VPS1

VPS2VPS2

COM2COM2OPBS

ENBL VPS2

RFIN

07593-001

INPUT

STAGE

OUTPUT

(TZ)

STAGE

CONTINUOUSLY

VARIABLE

ATTENUATO R

ADL5331

Figure 1.

GENERAL DESCRIPTION

The ADL5331 is a high performance, voltage-controlled

variable gain amplifier/attenuator for use in applications with

frequencies up to 1.2 GHz. The balanced structure of the signal

path maximizes signal swing, eliminates common-mode noise

and minimizes distortion while it also reduces the risk of spu-

rious feed-forward at low gains and high frequencies caused by

parasitic coupling.

The 50 Ω differential input system converts the applied

differential voltage at INHI and INLO to a pair of differential

currents with high linearity and good common-mode rejection.

The signal currents are then applied to a proprietary voltage-

controlled attenuator providing precise definition of the overall

gain under the control of the linear-in-dB interface. The GAIN

pin accepts a voltage from 0 V at a minimum gain to 1.4 V at a

full gain with a 40 mV/dB scaling factor over most of the range.

The output of the high accuracy wideband attenuator is applied

to a differential transimpedance output stage. The output stage

provides a differential output at OPHI and OPLO, which must be

pulled up to the supply with RF chokes or a center-tapped balun.

The ADL5331 consumes 240 mA of current including the out-

put pins and operates off a single supply ranging from 4.75 V

to 5.25 V. A power-down function is provided by applying a

logic low input on the ENBL pin. The current consumption in

power-down mode is 250 µA.

The ADL5331 is fabricated on an Analog Devices, Inc., pro-

prietary high performance, complementary bipolar IC process.

The ADL5331 is available in a 24-lead (4 mm × 4 mm), Pb-free

LFCSP_VQ package and is specified for operation from ambient

temperatures of −40°C to +85°C. An evaluation board is also

available.

ADL5331

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation .........................................................................9

Applications Information .............................................................. 10

Basic Connections ...................................................................... 10

Gain Control Input .................................................................... 11

CMTS Transmit Application .................................................... 13

Interfacing to an IQ Modulator ................................................ 14

Soldering Information ............................................................... 14

Evaluation Board Schematic ......................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

5/09—Revision 0: Initial Version

ADL5331

Rev. 0 | Page 3 of 16

SPECIFICATIONS

VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.

Table 1.

Parameter Conditions Min Typ Max Unit

GENERAL

Usable Frequency Range 0.001 1.2 GHz

Nominal Input Impedance 50 Ω

Nominal Output Impedance 20 Ω

FREQUENCY INPUT = 100 MHz

Gain Control Span ±3 dB gain law conformance 30 dB

Minimum Gain VGAIN = 0.1 V −14 dB

Maximum Gain VGAIN = 1.4 V 17 dB

Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB

Gain Control Slope 40 mV/dB

Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 700 mV

Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 47 dBm

Output Noise Floor VGAIN = 1.4 V −149 dBm/Hz

Noise Figure VGAIN = 1.4 V 9 dB

FREQUENCY INPUT = 400 MHz

Gain Control Span ±3 dB gain law conformance 30 dB

Minimum Gain VGAIN = 0.1 V −15 dB

Maximum Gain VGAIN = 1.4 V 15 dB

Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB

Gain Control Slope 39.5 mV/dB

Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 730 mV

Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 39 dBm

Output Noise Floor 20 MHz carrier offset, VGAIN = 1.4 V −150 dBm/Hz

Noise Figure VGAIN = 1.4 V 9 dB

FREQUENCY INPUT = 900 MHz

Gain Control Span ±3 dB gain law conformance 35 dB

Minimum Gain VGAIN = 0.1 V −18 dB

Maximum Gain VGAIN = 1.4 V 15 dB

Gain Flatness vs. Frequency ±30 MHz around center frequency, VGAIN = 1.0 V (differential output) 0.09 dB

Gain Control Slope 37 mV/dB

Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 800 mV

Third-Order Harmonic −8 dBm output at 900 MHz fundamental −75 dBc

Output IP3 VGAIN = 1.4 V, input −13 dBm per tone, two tone measurement 32 dBm

Output Noise Floor 20 MHz carrier offset, VGAIN = 1.4 V −150 dBm/Hz

Noise Figure VGAIN = 1.4 V 9 dB

GAIN CONTROL INPUT Pin GAIN

Gain Control Voltage Range1 0.1 1.4 V

Incremental Input Resistance Pin GAIN to Pin COM1 1 MΩ

Response Time Full scale, to within 1 dB of final gain 380 ns

3 dB gain step, POUT to within 1 dB of final gain 20 ns

ADL5331

Rev. 0 | Page 4 of 16

Parameter Conditions Min Typ Max Unit

POWER SUPPLIES Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL

Voltage 4.75 5 5.25 V

Current, Nominal Active 240 mA

ENBL, Logic 1, Device Enabled 2.3 V

ENBL, Logic 0, Device Disabled 0.8 V

Current, Disabled ENBL = Logic 0 250 μA

1 Minimum gain voltage varies with frequency (see , Figure , and ). Figure 3 4 Figure 5

ADL5331

Rev. 0 | Page 5 of 16

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VPS1 5.5 V

Supply Voltage VPS2 5.5 V

VPS2 to VPS1 ±200 mV

RF Input Power 5 dBm at 50 Ω

OPHI, OPLO 5.5 V

ENBL VPS1

GAIN VPS1

Internal Power Dissipation 1.2 W

θJA (with Pad Soldered to Board) 56.1°C/W

Maximum Junction Temperature 150°C

Operating Temperature Range −40°C to +85°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ADL5331

Rev. 0 | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GAIN

ENBL

VPS2

COM2

OPLO

OPHI

COM2

VPS2

COM2

OPBS

IPBS

VPS1

COM1

INLO

INHI

COM1

VPS1

ADL5331

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

07593-002

NOTES

1. NC = NO CONNECT.

2. CONNECT THE EXPOSED PAD

TO COM1 AND COM2.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1, 6 VPS1 Positive Supply. Nominally equal to 5 V.

2, 5 COM1 Common for the Input Stage.

3, 4 INHI, INLO Differential Inputs, AC-Coupled.

7 NC No Connect.

8 IPBS Input Bias. Normally ac-coupled to VPS1. A 10 nF capacitor is recommended.

9 OPBS Output Bias. Internally compensated, do not connect externally.

10 to 12, 14, 17 COM2 Common for the Output Stage.

13, 18 to 22 VPS2 Positive Supply. Nominally equal to 5 V.

15, 16 OPLO, OPHI Differential Outputs. Bias to VPOS with RF chokes.

23 ENBL Device Enable. Apply logic high for normal operation.

24 GAIN Gain Control Voltage Input. Nominal range is 0 V to 1.4 V.

25 (EPAD) EP (EPAD) Exposed Paddle.

ADL5331

Rev. 0 | Page 7 of 16

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.

–5

–10

–15

–20

–1

–2

–3

–4

0.1 0.3 0.5 0.7 0.9 1.1 1.3

GAIN

(V)

GAIN (dB)

ERROR (dB)

07593-003

Figure 3. Gain and Gain Law Conformance vs. VGAIN

over Temperature at 100 MHz

–5

–10

–15

–20

–1

–2

–3

–4

0.1 0.3 0.5 0.7 0.9 1.1 1.3

GAIN

(V)

GAIN (dB)

ERROR (dB)

07593-004

Figure 4. Gain and Gain Law Conformance vs. VGAIN

over Temperature at 400 MHz

–5

–10

–15

–20

–1

–2

–3

–4

0.1 0.3 0.5 0.7 0.9 1.1 1.3

GAIN

(V)

GAIN (dB)

ERROR (dB)

07593-005

Figure 5. Gain and Gain Law Conformance vs. VGAIN

over Temperature at 900 MHz

07593-006

FREQUENCY (MHz)

1k0.1 1 10 100

SLOPE (mV/dB)

Figure 6. Gain Slope vs. Frequency, RFIN = −20 dBm @ 500 MHz, VGAIN = 1 V

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

GAIN

(V)

OIP3 (dBm)

07593-007

Figure 7. Output IP3 vs. VGAIN at 100 MHz

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

GAIN

(V)

OIP3 (dBm)

07593-008

Figure 8. Output IP3 vs. VGAIN at 400 MHz

ADL5331

Rev. 0 | Page 8 of 16

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

GAIN

(V)

OIP3 (dBm)

07593-009

Figure 9. Output IP3 vs. VGAIN at 900 MHz

07593-010

CH3 200mV Ω

CH2 500mV M 2.0µs 25.0MS/s 40.0ns/pt

A CH1 150mV

t1: 2.24µs

t2: 1.2µs

Δt: –1.04µs

1/Δt: –961.5kHz

MEAN(C1) 1.358V

AMPL(C1) 3.36V

AMPL(C2) 900mV

Figure 10. Step Response of Gain Control Input

–5

–10

–15

–20

–25

–30

50 500 1000

FREQUENCY (MHz)

GAIN (dB), 50Ω DIFFERENTIAL

SOURCE AND LOAD

07593-011

VGAIN = 1.4V

VGAIN = 1.2V

VGAIN = 1.0V

VGAIN = 0.8V

VGAIN = 0.6V

VGAIN = 0.4V

VGAIN = 0.2V

VGAIN = 0V

Figure 11. Gain vs. Frequency (Differential 50 Ω

Output Load)

–5

–10

–15

–20

–25

50 500 1000

FREQUENCY (MHz)

GAIN (dB), 50Ω DIFFERENTIAL

SOURCE AND LOAD

07593-012

GAIN

= 1.4V

GAIN

= 1.2V

GAIN

= 1.0V

GAIN

= 0.8V

GAIN

= 0.6V

GAIN

= 0.4V

GAIN

= 0.2V

GAIN

= 0V

Figure 12. Gain vs. Frequency (Differential 100 Ω

Output Load)

–

148

–150

–152

–154

–156

–158

–160

0.1 0.3 0.5 0.7 0.9 1.1 1.3

GAIN

(V)

NOISE (dBm/Hz)

07593-028

100MHz

400MHz

900MHz

Figure 13. Output Noise Spectral Density vs. VGAIN

ADL5331

Rev. 0 | Page 9 of 16

THEORY OF OPERATION

The ADL5331 is a high performance, voltage-controlled

variable gain amplifier/attenuator for use in applications

with frequencies up to 1.2 GHz. This device is intended to

serve as an output variable gain amplifier (OVGA) for applica-

tions where a reasonably constant input level is available and

the output level adjusts over a wide range. One aspect of an

OVGA is that the output metrics, OIP3 and OP1dB, decrease

with decreasing gain.

The signal path is fully differential throughout the device to

provide the usual benefits of differential signaling, including

reduced radiation, reduced parasitic feedthrough, and reduced

susceptibility to common-mode interference with other circuits.

Figure 14 provides a simplified schematic of the ADL5331.

GAIN

CONTROL

07593-016

OPHI

OPLO

INHI

INLO

TRANSIMPEDANCE

AMPLIFIER

Gm STAGE

Figure 14. Simplified Schematic

A controlled input impedance of 50 Ω is achieved through

a combination of passive and active (feedback-derived)

termination techniques in an input Gm stage.

Note that the inputs of the Gm stage are internally biased to

a dc level and dc blocking capacitors are generally needed on

the inputs to avoid upsetting the operation of the device.

The currents from the Gm stage are then injected into a

balanced ladder attenuator at a deliberately diffused location

along the ladder, wherein the location of the centroid of the

injection region is dependent on the applied gain control

voltage. The steering of the current injection into the ladder

is accomplished by proprietary means to achieve linear-in-dB

gain control and low distortion.

Linear-in-dB gain control is accomplished by the application of

a voltage in the range of 0 V dc to 1.4 V dc to the gain control

pin, with maximum gain occurring at the highest voltage.

The output of the ladder attenuator is passed into a fixed-gain

transimpedance amplifier (TZA) to provide gain and to buffer

the ladder terminating impedance from load variations. The

TZA uses feedback to improve linearity and to provide controlled

50 Ω differential output impedance. The quiescent current of

the output amplifier is adaptive; it is controlled by an output

level detector, which biases the output stage for signal levels

above a threshold.

The outputs of the ADL5331 require external dc bias to the

positive supply voltage. This bias is typically supplied through

external inductors. The outputs are best taken differentially to

avoid any common-mode noise that is present, but, if necessary,

can be taken single-ended from either output.

The output impedance is 20  differential and can drive a range

of impedances from <20  to >75 . Back series terminations

can be used to pad the output impedance to a desired level.

If only a single output is used, it is still necessary to provide a

bias to the unused output pin and it is advisable to arrange a

reasonably equivalent ac load on the unused output. Differential

output can be taken via a 1:1 balun into a 50 Ω environment. In

virtually all cases, it is necessary to use dc blocking in the output

signal path.

At high gain settings, the noise floor is set by the input stage,

in which case the noise figure (NF) of the device is essentially

independent of the gain setting. Below a certain gain setting,

however, the input stage noise that reaches the output of the

attenuator falls below the input-equivalent noise of the output

stage. In such a case, the output noise is dominated by the output

stage itself; therefore, the overall NF of the device gets worse

on a dB-per-dB basis as the gain is lowered, because the gain

is reduced below the critical value. Figure 7 through Figure 9

provide details of this behavior.

ADL5331

Rev. 0 | Page 10 of 16

APPLICATIONS INFORMATION

ADL5331

VPS1

COM1

INHI

INLO

COM1

VPS1

IPBS

OPBS

COM2

VPS2

COM2

OPHI

OPLO

COM2

VPS2

GAIN

ENBL

VPS2

100pF

0.68µH L2

0.68µH

10nF

C13

10nF

C14

10nF

C10

10nF

0.1µF

C16

100pF

C15

0.1µF

C11

100pF

C12

0.1µF

100pF

0.1µF

100pF

VPOS

RFOUT

POS

RFIN

POS

GAIN

07593-017

Figure 15. Basic Connections

BASIC CONNECTIONS

Figure 15 shows the basic connections for operating the

ADL5331. There are two positive supplies, VPS1 and VPS2,

which must be connected to the same potential. Connect COM1

and COM2 (common pins) to a low impedance ground plane.

Apply a power supply voltage between 4.75 V and 5.25 V to

VPS1 and VPS2. Connect decoupling capacitors with 100 pF

and 0.1 µF power supplies close to each power supply pin. The

VPS2 pins (Pins 13 and Pin 18 through Pin 22) can share a pair

of decoupling capacitors because of their proximity to each other.

The outputs of the ADL5331, OPHI and OPLO, are open

collectors that need to be pulled up to the positive supply

with 120 nH RF chokes. The ac-coupling capacitors and

the RF chokes are the principle limitations for operation at

low frequencies. For example, to operate down to 1 MHz,

use 0.1 µF ac coupling capacitors and 1.5 µH RF chokes. Note

that in some circumstances, the use of substantially larger

inductor values results in oscillations.

Because the differential outputs are biased to the positive

supply, ac-coupling capacitors (preferably 100 pF) are needed

between the ADL5331 outputs and the next stage in the system.

Similarly, the INHI and INLO input pins are at bias voltages of

about 3.3 V above ground.

The nominal input and output impedance looking into each

individual RF input/output pin is 25 Ω. Consequently, the

differential impedance is 50 Ω.

To enable the ADL5331, the ENBL pin must be pulled high.

Taking ENBL low puts the ADL5331 in sleep mode, reducing

current consumption to 250 µA at an ambient temperature.

The voltage on ENBL must be greater than 1.7 V to enable the

device. When enabled, the device draws 100 mA at low gain to

215 mA at maximum gain.

The ADL5331 is primarily designed for differential signals;

however, there are several configurations that can be imple-

mented to interface the ADL5331 to single-ended applications.

Figure 16 and Figure 17 show options for differential-to-single-

ended interfaces. Both configurations use ac-coupling capacitors

at the input/output and RF chokes at the output.

RFIN

10nF

INHI

INLO

RFOUT

10nF

OPHI

OPLO

ADL5331

RF VGA

120nH

07593-018

ETC1-1-13ETC1-1-13

Figure 16. Differential Operation with Balun Transformers

Figure 16 illustrates differential balance at the input and output

using a transformer balun. Input and output baluns are recom-

mended for optimal performance. Much of the characterization

for the ADL5331 was completed using 1:1 baluns at the input

and output for a single-ended 50 Ω match. Operation using

M/A-COM ETC1-1-13 transmission line transformer baluns

is recommended for a broadband interface; however, narrow-

band baluns can be used for applications requiring lower

insertion loss over smaller bandwidths.

ADL5331

Rev. 0 | Page 11 of 16

10nF

INHI

INLO

RFOUTRFIN

10nF

OPHI

OPLO

ADL5331

RF VGA

120nH

ETC1-1-13

07593-019

Figure 17. Single-Ended Drive with Balanced Output

The device can be driven single-ended with similar perfor-

mance, as shown in Figure 17. The single-ended input interface

can be implemented by driving one of the input terminals and

terminating the unused input to ground. To achieve the optimal

performance, the output must remain balanced. In the case of

Figure 17, a transformer balun is used at the output.

GAIN CONTROL INPUT

When the VGA is enabled, the voltage applied to the GAIN pin

sets the gain. The input impedance of the GAIN pin is 1 MΩ.

The gain control voltage range is between 0.1 V and 1.4 V,

which corresponds to a typical gain range between −15 dB and

+15 dB.

The 1 dB input compression point remains constant at 3 dBm

through the majority of the gain control range, as shown in

Figure 7 through Figure 9. The output compression point

increases decibel for decibel with increasing gain setting. The

noise floor is constant up to VGAIN = 1 V where it begins to rise.

The bandwidth on the gain control pin is approximately 3 MHz.

Figure 10 shows the response time of a pulse on the VGAIN pin.

Although the ADL5331 provides accurate gain control, precise

regulation of output power can be achieved with an automatic

gain control (AGC) loop. Figure 18 shows the ADL5331 in an

AGC loop. The addition of a log amp or a TruPwr™ detector

(such as the AD8362) allows the AGC to have improved

temperature stability over a wide output power control range.

Note that the ADL5331, because of its positive gain slope, in

an AGC application requires a detector with a negative VOUT/

RFIN slope. As an example, the AD8319 in the example in

Figure 19 has a negative slope. The AD8362 rms detector,

however, has a positive slope. Extra circuitry is necessary to

compensate for this.

To operate the ADL5331 in an AGC loop, a sample of the

output RF must be fed back to the detector (typically using

a directional coupler and additional attenuation). A setpoint

voltage is applied to the VSET input of the detector while VOUT

is connected to the GAIN pin of the ADL5331. Based on the

detector’s defined linear-in-dB relationship between VOUT

and the RFIN signal, the detector adjusts the voltage on the

GAIN pin (the detector’s VOUT pin is an error amplifier

output) until the level at the RF input corresponds to the applied

setpoint voltage. The VGAIN setting settles to a value that results

in the correct balance between the input signal level at the

detector and the setpoint voltage.

The detector’s error amplifier uses CLPF, a ground-referenced

capacitor pin, to integrate the error signal (in the form of a

current). A capacitor must be connected to CLPF to set the

loop bandwidth and to ensure loop stability.

INLO

INHI

GAIN

OPLO

OPHI

DIRECTIONAL

COUPLER

ATTENUATOR

VPOS COMM

ADL5331

CLPF

VOUT

VSET RFIN

LOG AMP OR

TruPwr

DETECTOR

DAC

07593-020

RFIN

Figure 18. ADL5331 in AGC Loop

ADL5331

Rev. 0 | Page 12 of 16

INLO

INHI

GAIN

OPLO

OPHI

10dB

DIRECTIONAL

COUPLER

10dB

ATTENUATOR

VPOS COMM

ADL5331

+5V

COMM

VOUT VPOS

VSET INHI

INLOCLPF

AD8319

LOG AMP

DAC

RFIN

SIGNAL RFOUT SIGNAL

390Ω

1kΩ

SETPOINT

VOLTAGE

220pF

1nF

120nH

10nF

07593-021

10nF

Figure 19. AD8319 Operating in Controller Mode to Provide Automatic Gain Control Functionality in Combination with the ADL5331

Figure 19 shows the basic connections for operating the AD8319

log detector in an automatic gain control (AGC) loop with the

ADL5331.

The gain of the ADL5331 is controlled by the output pin of the

AD8319. The voltage, VOUT, has a range of 0 V to near VPOS. To

avoid overdrive recovery issues, the AD8319 output voltage can

be scaled down using a resistive divider to interface with the

0.1 V to 1.4 V gain control range of the ADL5331.

A coupler/attenuation of 21 dB is used to match the desired

maximum output power from the VGA to the top end of the

linear operating range of the AD8319 (approximately −5 dBm

at 900 MHz).

Figure 20 shows the transfer function of the output power vs.

the VSET voltage over temperature for a 100 MHz sine wave

with an input power of −1.5 dBm. Note that the power control

of the AD8319 has a negative sense. Decreasing VSET, which

corresponds to demanding a higher signal from the ADL5331,

increases gain.

This AGC loop is capable of controlling signals of ~30 dB,

which is the gain range limitation on the ADL5331. Across

the top 25 dB range of output power, the linear conformance

error is within ±0.5 dB over temperature.

3.00

2.25

1.50

–0.75

–1.50

–2.25

–3.00

0.75

–5

–10

–15

–20

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6

VSET (V)

OUTPUT POWER (dBm)

ERROR FROM STRAIGHT LINE AT 25°C (dB)

+85°C

+25°C

–40°C

07593-022

Figure 20. ADL5331 Output Power vs. AD8319 Setpoint Voltage,

PIN = 0 dBm at 100 MHz

ADL5331

Rev. 0 | Page 13 of 16

For the AGC loop to remain in equilibrium, the AD8319 must

track the envelope of the output signal of the ADL5331 and

provide the necessary voltage levels to the gain control input

of the ADL5331. Figure 21 shows an oscilloscope of the AGC

loop depicted in Figure 19. A 100 MHz sine wave with 50% AM

modulation is applied to the ADL5331. The output signal from the

VGA is a constant envelope sine wave with amplitude corres-

ponding to a setpoint voltage at the AD8319 of 1.3 V. The gain

control response of the AD8319 to the changing input envelope

is also shown in Figure 21.

07593-023

AD8319 OUTPUT

CH1 250mV ΩCH2 200mV

CH3 250mV Ω

M2.00ms A CH4 1.80V

T0.00000s

ADL5331 OUTPUT

AM MODULATED INPUT

Figure 21. Oscilloscope Showing an AM Modulated Input Signal and the

Response from the AD8319

Figure 22 shows the response of the AGC RF output to a pulse

on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop

responds with an RF burst. In this configuration, the input signal to

the ADL5331 is a 1 GHz sine wave at a power level of −15 dBm.

07593-024

CH3 200mV Ω

CH2 500mV M 4.0µs 12.5MS/s 80.0ns/pt

A CH1 150mV

t1: 4.48µs

t2: 2.4µs

Δt: –2.08µs

1/Δt: –480.8kHz

MEAN(C1) 440.3mV

CURS2 POS

2.4µs

CURS1 POS

4.48µs

AMPL(C1) 3.36V

AMPL(C2) 900mV

Figure 22. Oscilloscope Showing theResponse Time of the AGC Loop

Response time and the amount of signal integration are con-

trolled by CLPF. This functionality is analogous to the feedback

capacitor around an integrating amplifier. While it is possible

to use large capacitors for CLPF, in most applications, values

under 1 nF provide sufficient filtering.

More information on the use of AD8319 in an AGC application

can be found in the AD8319 data sheet.

CMTS TRANSMIT APPLICATION

Interfacing to AD9789

Because of its broadband operating range, the ADL5331 VGA

can also be used in direct-launch cable modem termination

systems (CMTS) applications in the 50 MHz to 860 MHz cable

band. The ADL5331 makes an excellent choice as a post-DAC

VGA in a CMTS application when used with the Analog

Devices AD9789 wideband DAC. The AD9789 also contains

digital signal processing specifically designed to process

DOCSIS type CMTS signals. A typical AD9789-to-ADL5331

interface is shown in Figure 23.

7593-025

16mA

50Ω

55Ω

20Ω

AD9789

DAC 25Ω70Ω

VGA 5V SERIES

TERMINATION

Figure 23. Block Diagram of AD9789 interface to ADL5331 in a DOCSIS Type Application

ADL5331

Rev. 0 | Page 14 of 16

INTERFACING TO AN IQ MODULATOR

The basic connections for interfacing the ADL5331 with the

ADL5385 are shown in Figure 24. The ADL5385 is an RF

quadrature modulator with an output frequency range of

50 MHz to 2.2 GHz. It offers excellent phase accuracy and

amplitude balance, enabling high performance direct RF

modulation for communication systems.

The output of the ADL5385 is designed to drive 50  loads and

easily interfaces with the ADL5331. The input to the ADL5331

can be driven single-ended, as shown in Figure 17. Similar

configurations are possible with the ADL537x family of

quadrature modulators. These modulators can provide outputs

from 500 MHz to 4 GHz.

SOLDERING INFORMATION

On the underside of the chip scale package, there is an exposed

compressed paddle. This paddle is internally connected to the

chip’s ground. Solder the paddle to the low impedance ground

plane on the printed circuit board to ensure specified electrical

performance and to provide thermal relief. It is also recom-

mended that the ground planes on all layers under the paddle

be stitched together with vias to reduce thermal impedance.

10nF

INHI

INLO

RF OUTPUT

10nF

OPHI

COMMVPOS

OPLO

ETC1-1-13

IBBP

IBBN

QBBP

QBBN

COMMVPOS

GAIN CONTROL

100pF

DIFFERENTIAL I/Q

BASEBAND INPUTS

DAC

VOUT

ADL5385

IQ MOD

68µH

ADL5331

RF VGA

07593-030

Figure 24. ADL5385 Quadrature Modulator and ADL5331 Interface

ADL5331

Rev. 0 | Page 15 of 16

EVALUATION BOARD SCHEMATIC

AGNDA

OPHIA

VPS2A

AGNDA

PS1A

INHIA

VPS1A

AGNDA

VPS2A

AGNDA

SW1A

AGNDA

IPBSA

OPBSA

VS2A

78 9101112

192021222324

VS1A

C13A

100pF

C10A

100pF

C7A

100pF

AGNDA

C8A

0.1µF

C9A

0.1µF

C16A

10nF

C11A

C12A

R12A

0Ω

RSA

0Ω

R16A

0Ω

R3A

1kΩ

R1A

0Ω

R17A

10kΩ

R2A

0Ω

AGNDA

C1A

100pF

AGNDA

0.1µF

AGNDA

C17A

1000pF

R6A

0Ω

R4A

0Ω

R9A

0Ω

VS1A

C15A

10nF

L1A

0.68µH

L2A

0.68µH

T2A

C14A

0.1µF

C3A

0.1µF

C4A

100pF

C11A

10nF

C12A

10nF

T1A

GAINA

ENBLA

VPS1A

GNA

ENB_A

PS1

VPS1A

TESTLOOP

BLUE

TESTLOOP

RED

TESTLOOP

BLACK

PS2

VPS2A

GND

AGNDA

ENBLA

VPS1A

VPS2A

GAINA

IPBSA

OPBSA

VREFA

AGNDA

R14A

0Ω

P1A 1

P1A 2

P1A 3

P1A 4

P1A 5

P1A 6

P1A 7

P1A 8

07593-026

VPS1

COM1

INHI

INLO

COM1

VPS1

IPBS

OPBS

COM2

VPS2

VS2A

COM2

OPHI

OPLO

COM2

VPS2

EPAD

ENBL

GAIN

VPS2

Z1A

ADL5331

Figure 25. ADL5331 Single-Ended Input/Output Evaluation Board

ADL5331

Rev. 0 | Page 16 of 16

OUTLINE DIMENSIONS

*COMP LIANT T O JEDE C STANDARDS MO-220-V GGD- 2

EXCEPT FOR EXPOSED PAD DIMENSION

*2.45

2.30 S Q

2.15

0.60 M A X

0.50

0.40

0.30

0.23

0.18

2.50 RE F

0.50

BSC

12° MA X 0.80 M A X

0.65 TYP 0.05 M A X

0.02 NOM

1.00

0.85

0.80

SEATING

PLANE

PIN 1

INDICATOR TOP

BSC SQ

4.00

BSC SQ PIN 1

INDICATOR

0.60 M A X

COPLANARITY

0.08

0.20 REF

0.23 M IN

EXPOSED

PA D

(BOTTOMVIEW)

FO R PRO P ER CONNE CT I O N O F

THE EXPOSED PAD, REFER TO

THE P IN CONFIGURATIO N AND

FUNCT ION DE S CRIPT IONS

SECT ION OF THIS DATA SHEE T .

080808-A

Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description

Package

Option

Ordering

Quantity

ADL5331ACPZ-R71 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-2 1,500

ADL5331ACPZ-WP1 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-2 250

ADL5331-EVALZ1 ADL5331 Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D07593-0-5/09(0)