2.25 GHz XpressView HDMI 1:2 Splitter with 4:1 Input Mux ADV7630 Data Sheet FEATURES General Interrupt controller with interrupt output On-chip 5 V regulator for 5 V HDMI cable power support Software libraries, driver, and application available Internal EDID RAM 128-lead 14 mm x 14 mm TQFP_EP package 2.25 GHz TMDS HDMI 1:2 splitter with 4:1 input mux High-Definition Multimedia Interface (HDMI) supported All mandatory and additional 3D video formats supported CEC 1.4-compatible 225 MHz maximum TMDS clock frequency XpressView fast switching on all HDMI input ports 36-/30-bit per pixel Deep Color and 24-bit per pixel color support High-bandwidth Digital Content Protection (HDCP) 1.4 support with internal HDCP keys HDCP repeater support Up to 127 KSVs supported Integrated CEC controller 5 V detect and hot plug assert for each HDMI port EDID data extraction on HDMI outputs Hot plug detection (HPD) input on HDMI outputs APPLICATIONS Video conferencing HDTV AVR, HTiB Soundbar Video switch HDMI splitter FUNCTIONAL BLOCK DIAGRAM HDMI 1 ADV7630 TMDS DDC TMDS DDC HDMI 3 TMDS DEEP COLOR HDMIRX 4:1 MUX HDMI TXA DDC TMDS TMDS HDMI TXB DDC DDC HDMI 4 1:2 SPLITTER TMDS DDC HDCP KEYS FAST SWITCH CEC I 2C INT I 2C INT CEC TX EDID/HDCP BUFFER 10635-001 HDMI 2 Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7630 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................9 Applications ....................................................................................... 1 Power Supply Recommendation .................................................. 14 Functional Block Diagram .............................................................. 1 Power-Up Sequence ................................................................... 14 Revision History ............................................................................... 2 Power-Down Sequence .............................................................. 14 General Description ......................................................................... 3 Functional Overview...................................................................... 15 Detailed Functional Block Diagram .......................................... 3 HDMI Receiver........................................................................... 15 Specifications..................................................................................... 4 HDMI Transmitter ..................................................................... 15 Electrical Characteristics ............................................................. 4 I2C Interface ................................................................................ 15 Timing Characteristics ................................................................ 6 Other Features ............................................................................ 15 Absolute Maximum Ratings ............................................................ 8 Outline Dimensions ....................................................................... 16 Package Thermal Performance ................................................... 8 Ordering Guide .......................................................................... 16 ESD Caution .................................................................................. 8 REVISION HISTORY 9/12--Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADV7630 GENERAL DESCRIPTION Each HDMI input port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface even with long and low quality cables. The ADV7630 is a high quality 1:2 HDMI(R) splitter with 4:1 input multiplexer. It incorporates a four-input HDMI receiver and dual transmitter functions onto a single chip. The ADV7630 supports all mandatory HDMI 3D TV formats, HDTV formats up to 1080p 36-bits per pixel Deep Color, and display resolutions up to 1080p60. The reception of HDCP encrypted video is also supported by the HDMI receiver with TMDS The HDMI video transmitted to the downstream device by the transmitter. HDMI output features dedicated DDC lines with an HDCP encryption engine. Each HDMI has a dedicated hot plug detect port and DDC lines along with an internal HDCP encryption engine. The ADV7630 features an EDID replicator and internal EDID RAM. On the transmitter side, DDC control allows reading back EDID data from sink. As the part incorporates an internal regulator, the EDID functionality on the receiver's side can be powered from the HDMI cable when ac power is removed from the system. The ADV7630 integrates an HDMI CEC controller that supports the capability discovery and control (CDC) feature. The ADV7630 incorporates XpressViewTM fast switching on all input HDMI ports. Using an Analog Devices, Inc., hardwarebased HDCP engine that minimizes software overhead, XpressView technology allows fast switching between all HDMI input ports in less than 1 second. Fabricated in an advanced CMOS process, the ADV7630 is provided in a 14 mm x 14 mm, 128-lead surface-mount TQFP_EP, RoHS-compliant package and is specified over the 0C to 70C temperature range. EDID REPEATER CONTROLLER 5V DETECT VOLTAGE REG. HPD CONTROLLER HDCP EEPROM EP_SCK EP_MISO EP_MOSI EP_CS INT1 DDCA_SCL DDCB_SCL DDCC_SCL DDCD_SCL DDCA_SDA DDCB_SDA DDCC_SDA DDCD_SDA CEC HPA_A HPA_B HPA_C HPA_D RXA_5V RXB_5V RXC_5V RXD_5V DETAILED FUNCTIONAL BLOCK DIAGRAM CEC CONTROLLER INTERRUPT CONTROLLER HDCP ENGINE HDCP ENGINE TX EDID BUFFER TX DDC CONTROL HDMI TX RXA_0 RXA_1 RXA_2 EQUALIZER SAMPLER RXB_0 RXB_1 RXB_2 EQUALIZER SAMPLER EQUALIZER SAMPLER RXD_0 RXD_1 RXD_2 EQUALIZER SAMPLER XpressView FAST SWITCHING 4:1 MUX HOT PLUG DETECT TXB_0 TXB_1 TXB_2 TXB_C TXA_HPD TXB_HPD INTERNAL CLOCK CONTROL INTERFACE I2C 10635-002 SCL SDA ADV7630 CS PLLs CLK_IN RXA_C RXB_C RXC_C RXD_C TXA_0 TXA_1 TXA_2 TXA_C 1:2 SPLITTER HDMI TX RXC_0 RXC_1 RXC_2 TXA_DDC_SCL TXA_DDC_SDA TXB_DDC_SCL TXB_DDC_SDA Figure 2. Rev. 0 | Page 3 of 16 ADV7630 Data Sheet SPECIFICATIONS DVDD, TXA_PVDD, TXB_PVDD, CVDD, TX_AVDD at 1.71 V to 1.89 V; DVDDIO, TVDD, SYS_3P3V at 3.14 V to 3.46 V; TMIN to TMAX = 0oC to 70oC, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance 1 DIGITAL INPUTS (5 V TOLERANT) 2 Input High Voltage Input Low Voltage High Impedance Leakage Current DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current 1 Output Capacitance POWER REQUIREMENTS1 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply TXA PLL Power Supply TXB Terminator Power Supply Comparator Power Supply System Power Supply TX Analog Power Supply Power-Up Time Test Condition 1 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Terminator Power Supply Comparator Power Supply System Power Supply TX Analog Power Supply Symbol Test Conditions/Comments Min VIH VIL IIN Digital inputs Digital inputs RESET, CS, EP_MISO Other digital inputs Excluding differential HDMI inputs 2 CIN VIH VIL ILEAK VOH VOL ILEAK COUT Max 0.8 40 10 20 2.6 DDCA_SCL, DDCB_SCL, DDCC_SCL, DDCD_SCL, DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA, TXA_DDC_SDA, TXB_DDC_SDA 3 TXA_HPD, TXB_HPD 10 A 0.4 30 10 20 1.71 3.14 1.71 1.71 3.14 1.71 3.14 1.71 Test Condition 1 Test Condition 1 Test Condition 1 Test Condition 1 Test Condition 1 Test Condition 1 Test Condition 1 Rev. 0 | Page 4 of 16 V V A A pF 30 2.4 DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA, TXA_DDC_SDA, TXB_DDC_SDA, TXA_DDC_SCL, TXB_DDC_SCL3 All other digital pins Excluding non-tristable outputs 4 Unit V V A 0.8 DVDD DVDDIO TXA_PVDD TXB_PVDD TVDD CVDD SYS_3P3V TX_AVDD tPWRUP IDVDD IDVDDIO ITX_PVDD 5 ITVDD ICVDD ISYS_3P3V ITX_AVDD Typ V V A A pF 1.8 3.3 1.8 1.8 3.3 1.8 3.3 1.8 25 1.89 3.46 1.89 1.89 3.46 1.89 3.46 1.89 V V V V V V V V ms 277 0.13 85.9 226 307 2.21 33.0 303 0.13 97.6 227 328 3.23 34.9 mA mA mA mA mA mA mA Data Sheet Parameter Test Condition 2 Power-Down Currents1 ADV7630 Symbol Test Conditions/Comments IDVDD_PD IDVDDIO_PD ITX_PVDD_PD 6 ITVDD_PD ICVDD_PD ISYS_3P3V_PD ITX_AVDD_PD Test Condition 2 Test Condition 2 Test Condition 2 Test Condition 2 Test Condition 2 Test Condition 2 Test Condition 2 Min Typ Max Unit 0.38 0 0.057 0.031 0.027 0.050 3.160 1.974 0.128 0.157 0.082 0.101 0.217 3.450 mA mA mA mA mA mA mA 1 Data recorded during lab characterization. The following pins are 5 V tolerant: TXA_DDC_SCL, TXA_DDC_SDA, TXB_DDC_SCL, TXB_DDC_SDA, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA. 3 SDA pins are bidirectional. 4 Non-tristatable pins are all differential HDMI TX outputs. 5 Sum of currents ITXA_PVDD and ITXB_PVDD. 6 Sum of currents ITXA_PVDD_PD and ITXB_PVDD_PD. 2 Table 2. Test Conditions for Power Requirements Parameter TEST CONDITION 1 Number of HDMI Inputs (XpressView Mode) Video Format (Each HDMI Input) HDCP Encryption HDCP Decryption Audio Video Pattern (Each HDMI Input) Number of HDMI Outputs Used Temperature Power Supply Voltages TEST CONDITION 2 (POWER-DOWN) Number of HDMI Inputs (XpressView Mode) Video Format (Each HDMI Input) HDCP Decryption Video Pattern (Each HDMI Input) Number of HDMI Outputs Used Audio Temperature Power Supply Voltages Value Used for Typical Case Value Used For Maximum Case Four inputs 1080p60, 12 bits Transmitter only Off 192 kHz PCM Pseudo random Two outputs 25oC Nominal Four inputs 1080p60, 12 bits Transmitter only Off 192 kHz PCM Pseudo random Two outputs 70oC Maximum Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable 25oC Nominal Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable 70oC Maximum Rev. 0 | Page 5 of 16 ADV7630 Data Sheet TIMING CHARACTERISTICS Data and I2C Timing Characteristics Table 3. Parameter CLOCK Clock Frequency, CLK_IN Frequency Stability TMDS Frequency Range I2C PORTS 1 SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time RESET FEATURE RESET Pulse Width Symbol Min Typ Max Unit 200 225 MHz ppm MHz 27.000 25 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 kHz ns s ns ns ns ns ns s 5 ms 600 1.3 600 600 100 300 300 1 SPI PORT EP_CS Falling Edge Before First EP_SCK Edge EP_CS Rising Edge After Last Rising EP_SCK Edge SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After EP_SCK Edge Data Output Setup Before EP_SCK Edge Data Input Setup Time Before EP_SCK Edge Data Input Hold Time After EP_SCK Edge 1 tCSL tCSH tSL tSH tDAV tDOSU tDSU tDHD 191.4 191.4 191.4 191.4 217.5 217.5 217.5 217.5 27.2 217.5 21.3 21.3 Data guaranteed by design. Timing Diagrams t5 t3 t3 SDA t6 t2 t4 t7 2 Figure 3. I C Timing Rev. 0 | Page 6 of 16 t8 10635-003 t1 SCL ns ns ns ns ns ns ns ns Data Sheet ADV7630 tCSL tCSH EP_CS EP_SCK tSH tSL tDAV tDOSU EP_MOSI EP_MISO 10635-005 tDSU tDHD Figure 4. SPI Timing Rev. 0 | Page 7 of 16 ADV7630 Data Sheet ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 4. Parameter CVDD to GND DVDD to GND TVDD to GND TX_AVDD to GND TXA_PVDD to GND TXB_PVDD to GND SYS_3P3V to GND DVDDIO to GND Digital Inputs Voltage to GND Analog Inputs Voltage to GND HDMI Digital Inputs Voltage to GND 5 V Tolerant Digital Inputs to GND1, 3, 6 5 V Digital Inputs2 5 V Tolerant Digital Outputs to GND3, 6 Digital Outputs Voltage to GND4, 5 Analog Outputs Voltage to GND HDMI Digital Outputs to GND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 2.2 V 2.2 V 3.9 V 2.2 V 2.2 V 2.2 V 3.9 V 3.9 V GND - 0.3 V to DVDDIO + 0.3 V GND - 0.3 V to TXA_PVDD + 0.3 V GND - 0.3 V to TVDD + 0.3 V GND - 0.3 V to 5.5 V GND - 0.3 V to 5.5 V GND - 0.3 V to DVDDIO + 0.3 V GND - 0.3 V to CVDD + 0.3 V GND - 0.3 V to TVDD + 0.3 V 125C -60C to +150C 260C 1 The following pins are 3.3 V inputs, 5 V tolerant: TXB_HPD, TXB_DDC_SDA, , TXA_HPD, TXA_DDC_SDA, DDCA_SCL, DDCB_SCL, DDCC_SCL, DDCD_SCL. 2 The following pins are 5 V inputs: RXA_5V, RXB_5V, RXC_5V, RXD_5V. 3 The following pins are 3.3 V outputs, 5 V tolerant: TXB_DDC_SCL, TXA_DDC_SCL, HPA_D, HPA_C, HPA_B, HPA_A. 4 Except the DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA, EP_MOSI, EP_SCK, and EP_CS pins, which are kept to GND - 0.3 V to REG_3P3V. 5 Except the REG_3P3V output, which is kept to GND - 0.3 V to SYS_3P3 + 0.3 V and REG_1P8V output, which is kept to GND - 0.3 V to DVDD + 0.3 V. 6 The following pins are 3.3 V bidirectional input/outputs, 5 V tolerant: TXA_DDC_SDA, TXB_DDC_SDA, DDCA_SDA, DDCB_SDA, DDCC_SDA, and DDCD_SDA. To reduce power consumption when using the ADV7630, the user is advised to turn off the unused sections of the part. Due to PCB metal variation and, therefore, variation in PCB heat conductivity, the value of JA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the JA value. The maximum junction temperature (TJ MAX) of 125C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): TJ TS JT WTOTAL where: TS is the package surface temperature (C). JT is 0.22C/W for the 128-lead TQFP_EP. WTOTAL = ((CVDD x ICVDD) + (0.2 x TVDD x ITVDD) + (DVDD x IDVDD) + (TX_AVDD x ITX_AVDD) + (TXA_PVDD x ITXA_PVDD) + (TXB_PVDD x ITXA_PVDD) + (DVDDIO x IDVDDIO)) + NTX x PTX where: 0.2 is 20% of the TVDD power that is dissipated on the part itself. NTX is the number of connected and active TX ports. PTX = 28 mW minus average power dissipated on-chip of each HDMI transmitters. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 16 Data Sheet ADV7630 1 DNC 2 CVDD RXA_2+ RXA_2- RXA_1+ RXA_1- TVDD RXA_0+ RXA_0- RXA_C+ RXA_C- CVDD DVDD RXB_2+ RXB_2- RXB_1+ RXB_1- TVDD RXB_0+ RXB_0- RXB_C+ RXB_C- CVDD RXC_2+ RXC_2- RXC_1+ RXC_1- TVDD RXC_0+ RXC_0- RXC_C+ RXC_C- CVDD 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PIN 1 IDENTIFIER 96 DNC 95 DNC DNC 3 94 DNC DNC 4 93 DNC DNC 5 92 DVDD DNC 6 91 CVDD DNC 7 90 RXD_2+ INT1 8 89 RXD_2- CLK_IN 9 88 RXD_1+ CEC 10 87 RXD_1- DVDDIO 11 86 TVDD SDA 12 85 RXD_0+ SCL 13 84 RXD_0- CS 14 83 RXD_C+ DVDD 15 82 RXD_C- TXB_PVDD 16 81 CVDD TXB_PVDD 17 80 DVDD NC 18 79 SYS_3P3V TXB_PVDD 19 78 HPA_A TXB_HPD 20 77 RXA_5V TX_AVDD 21 76 HPA_B ADV7630 TOP VIEW (Not to Scale) TXB_C- 22 75 RXB_5V TXB_C+ 23 74 HPA_C TX_AVDD 24 73 RXC_5V TXB_0- 25 72 HPA_D TXB_0+ 26 71 RXD_5V TX_AVDD 27 70 REG_1P8V TXB_1- 28 69 EP_CS TXB_1+ 29 68 EP_SCK TXB_2- 30 67 EP_MISO TXB_2+ 31 66 EP_MOSI TX_AVDD 32 65 REG_3P3V 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TX_AVDD TXA_1- TXA_1+ TXA_2- TXA_2+ TX_AVDD DNC TXA_HPD DDCD_SCL DDCD_SDA DDCC_SCL DDCC_SDA DDCB_SCL DDCB_SDA DDCA_SCL DDCA_SDA 44 TXA_C- 48 43 TX_AVDD TXA_0+ 42 R_EXT 47 41 TXA_PVDD TXA_0- 40 NC 46 39 TXA_PVDD TX_AVDD 38 TXA_PVDD 45 37 DVDD TXA_C+ 35 36 TXA_DDC_SCL TXB_DDC_SCL TXA_DDC_SDA 33 34 TXB_DDC_SDA EXPOSED PADDLE--PIN 0 GND (BOTTOM) NOTES 1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 2. EXPOSED PAD SHOULD BE CONNECTED TO GND. 3. DNC = DO NOT CONNECT TO THIS PIN. Figure 5. Pin Configuration Rev. 0 | Page 9 of 16 10635-008 RESET 128 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADV7630 Data Sheet Table 5. Pin Function Descriptions Pin No. 0 1 Mnemonic GND RESET 2 to 7, 55, 93 to 96 8 DNC 9 CLK_IN 10 CEC 11 12 DVDDIO SDA 13 14 SCL CS Digital input/output Power Digital input/output Digital input Digital input 15 16 DVDD TXB_PVDD Power Power 17 TXB_PVDD Power 18, 40 19 NC TXB_PVDD Not connected Power 20 TXB_HPD Digital input 21 22 23 24 25 26 27 28 29 30 31 32 33 TX_AVDD TXB_C- TXB_C+ TX_AVDD TXB_0- TXB_0+ TX_AVDD TXB_1- TXB_1+ TXB_2- TXB_2+ TX_AVDD TXB_DDC_SDA 34 TXB_DDC_SCL Power HDMI output HDMI output Power HDMI output HDMI output Power HDMI output HDMI output HDMI output HDMI output Power Digital input/output Digital output INT1 Type Ground Miscellaneous digital Do not connect Description The Exposed Pad Should be Connected to GND. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7630 circuitry. Do not connect to this pin. Miscellaneous digital Digital input Interrupt Output Pin. Input Pin for a 3.3 V 27.000 MHz Clock Oscillator. The following frequencies are also supported: 24 MHz, 24.576 MHz, and 28.63636 MHz. Consumer Electronic Control Channel. Digital I/O Supply Voltage (3.3 V). I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. I2C Port Serial Clock Input. SCL is the clock line for the control port. Chip Select Pin. Pulling this pin up causes the I2C state machine to ignore I2C transmission. This pin has internal pull-down. Digital Core Supply Voltage (1.8 V). 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXA_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXA_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. This pin is not connected internally (see Figure 5). 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXA_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. Hot Plug Detect Signal of HDMI Output Port B. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. 1.8 V Power Supply for TMDS Outputs. TMDS Clock Output Complement of HDMI Output Port B. TMDS Clock Output True of HDMI Output Port B. 1.8 V Power Supply for TMDS Outputs. TMDS Output Channel 0 Complement of HDMI Output Port B. TMDS Output Channel 0 True of HDMI Output Port B. 1.8 V Power Supply for TMDS Outputs. TMDS Output Channel 1 Complement of HDMI Output Port B. TMDS Output Channel 1 True of HDMI Output Port B. TMDS Output Channel 2 Complement of HDMI Output Port B. TMDS Output Channel 2 True of HDMI Output Port B. 1.8 V Power Supply for TMDS Outputs. HDCP Master Serial Data of HDMI Output Port B. TXB_DDC_SDA is a 3.3 V open-drain input/output that is 5 V tolerant. HDCP Master Serial Clock of HDMI Output Port B. TXB_DDC_SCL is a 3.3 V open-drain output that is 5 V tolerant. Rev. 0 | Page 10 of 16 Data Sheet ADV7630 Pin No. 35 Mnemonic TXA_DDC_SDA 36 TXA_DDC_SCL Type Digital input/output Digital output 37 38 DVDD TXA_PVDD Power Power 39 TXA_PVDD Power 41 TXA_PVDD Power 42 R_EXT Input 43 44 45 46 47 48 49 50 51 52 53 54 56 TX_AVDD TXA_C- TXA_C+ TX_AVDD TXA_0- TXA_0+ TX_AVDD TXA_1- TXA_1+ TXA_2- TXA_2+ TX_AVDD TXA_HPD Power HDMI output HDMI output Power HDMI output HDMI output Power HDMI output HDMI output HDMI output HDMI output Power Digital input 57 58 DDCD_SCL DDCD_SDA 59 60 DDCC_SCL DDCC_SDA Digital input Digital input/output Digital input Digital input/output 61 62 DDCB_SCL DDCB_SDA 63 64 DDCA_SCL DDCA_SDA 65 REG_3P3V Digital input Digital input/output Digital input Digital input/output Power output 66 67 68 69 EP_MOSI EP_MISO EP_SCK EP_CS Digital output Digital input Digital output Digital output Description HDCP Master Serial Data of HDMI Output Port A. TXA_DDC_SDA is a 3.3 V open-drain input/output that is 5 V tolerant. HDCP Master Serial Clock of HDMI Output Port A. TXA_DDC_SCL is a 3.3 V open-drain output that is 5 V tolerant. Digital Core Supply Voltage (1.8 V). 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXB_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXB_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. 1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It should be kept separately from TXB_PVDD to avoid possible crosstalk. This power supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with 10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the package. Sets internal reference currents. Place a 470 resistor (1% tolerance) between this pin and ground. 1.8 V Power Supply for TMDS Outputs. TMDS Clock Output Complement of HDMI Output Port A. TMDS Clock Output True of HDMI Output Port A. 1.8 V Power Supply for TMDS Outputs. TMDS Output Channel 0 Complement of HDMI Output Port A. TMDS Output Channel 0 True of HDMI Output Port A. 1.8 V Power Supply for TMDS Outputs. TMDS Output Channel 1 Complement of HDMI Output Port A. TMDS Output Channel 1 True of HDMI Output Port A. TMDS Output Channel 2 Complement of HDMI Output Port A. TMDS Output Channel 2 True of HDMI Output Port A. 1.8 V Power Supply for TMDS Outputs. Hot Plug Detect Signal of HDMI Output Port A. This pin indicates to the interface whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels. HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port D. DDCD_SDA is a 5 V tolerant 3.3 V input and open-drain output. HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port C. DDCC_SDA is a 5 V tolerant 3.3 V input and open-drain output. HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port B. DDCB_SDA is a 5 V tolerant 3.3 V input and open-drain output. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port A. DDCA_SDA is a 5 V tolerant 3.3 V input and open-drain output. Output of Internal 3.3 V LDO. Must be connected to ground via decoupling capacitors (10 nF in parallel with 100 nF capacitor). This pin can be used to power up external EDID SPI EEPROM when part is in power-down mode and 5 V is connected to the part from an HDMI cable. SPI Master Output/Slave Input for External EDID Interface. SPI Master Input/Slave Output for External EDID Interface. SPI Clock for External EDID Interface. SPI Chip Select for External EDID Interface. Rev. 0 | Page 11 of 16 ADV7630 Data Sheet Pin No. 70 Mnemonic REG_1P8V Type Power output 71 RXD_5V HDMI input 72 73 HPA_D RXC_5V HDMI output HDMI input 74 75 HPA_C RXB_5V HDMI output HDMI input 76 77 HPA_B RXA_5V HDMI output HDMI input 78 79 HPA_A SYS_3P3V 80 81 82 83 84 85 86 87 88 89 90 91 92 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DVDD CVDD RXD_C- RXD_C+ RXD_0- RXD_0+ TVDD RXD_1- RXD_1+ RXD_2- RXD_2+ CVDD DVDD CVDD RXC_C- RXC_C+ RXC_0- RXC_0+ TVDD RXC_1- RXC_1+ RXC_2- RXC_2+ CVDD RXB_C- RXB_C+ RXB_0- RXB_0+ TVDD RXB_1- RXB_1+ RXB_2- RXB_2+ DVDD CVDD RXA_C- RXA_C+ HDMI output Miscellaneous power Power Power HDMI input HDMI input HDMI input HDMI input Power HDMI input HDMI input HDMI input HDMI input Power Power Power HDMI input HDMI input HDMI input HDMI input Power HDMI input HDMI input HDMI input HDMI input Power HDMI input HDMI input HDMI input HDMI input Power HDMI input HDMI input HDMI input HDMI input Power Power HDMI input HDMI input Description Output of Internal 1.8 V LDO. This pin must be connected only to decoupling capacitors (100 nF in parallel with 10 nF). 5 V Detect Pin for Port D in the HDMI Interface. This pin is used to power the EDID replicator. Hot Plug Assert Signal Output for HDMI Port D. 5 V Detect Pin for Port C in the HDMI Interface. This pin is used to power the EDID replicator. Hot Plug Assert Signal Output for HDMI Port C. 5 V Detect Pin for Port B in the HDMI Interface. This pin is used to power the EDID replicator. Hot Plug Assert Signal Output for HDMI Port B. 5 V Detect Pin for Port A in the HDMI Interface. This pin is used to power the EDID replicator. Hot Plug Assert Signal Output for HDMI Port A. 3.3 V Power Supply. Digital Core Supply Voltage (1.8 V). HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port D in the HDMI Interface. Digital Input Clock True of Port D in the HDMI Interface. Digital Input Channel 0 Complement of Port D in the HDMI Interface. Digital Input Channel 0 True of Port D in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port D in the HDMI Interface. Digital Input Channel 1 True of Port D in the HDMI Interface. Digital Input Channel 2 Complement of Port D in the HDMI Interface. Digital Input Channel 2 True of Port D in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port C in the HDMI Interface. Digital Input Clock True of Port C in the HDMI Interface. Digital Input Channel 0 Complement of Port C in the HDMI Interface. Digital Input Channel 0 True of Port C in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port C in the HDMI Interface. Digital Input Channel 1 True of Port C in the HDMI Interface. Digital Input Channel 2 Complement of Port C in the HDMI Interface. Digital Input Channel 2 True of Port C in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. Digital Core Supply Voltage (1.8 V). HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Rev. 0 | Page 12 of 16 Data Sheet Pin No. 121 122 123 124 125 126 127 128 Mnemonic RXA_0- RXA_0+ TVDD RXA_1- RXA_1+ RXA_2- RXA_2+ CVDD ADV7630 Type HDMI input HDMI input Power HDMI input HDMI input HDMI input HDMI input Power Description Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). Rev. 0 | Page 13 of 16 ADV7630 Data Sheet POWER SUPPLY RECOMMENDATION POWER-UP SEQUENCE POWER-DOWN SEQUENCE The power-up sequence of the ADV7630 is as follows: The ADV7630 supplies can be de-asserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3. 4. 5. 6. Hold RESET low. Bring up the 3.3 V supplies (DVDDIO, TVDD, SYS_3P3V). A minimum delay of 20 ms is required from the point at which the 3.3 V supplies reaches the minimum recommended value (3.14 V) before powering up the 1.8 V supplies. Bring up the 1.8 V supplies (DVDD, TXA_PVDD, TXB_PVDD, CVDD, TX_AVDD). These should be powered up together, that is, there should be a difference of less than 0.3 V between them. RESET can be pulled high after supplies have been powered up. A complete reset is recommended after power-up. This can be performed by the system microcontroller. 3.3V RESET 0V 1.8V 1.8V SUPPLY 0V 3.3V 3.14V 3.3V SUPPLY Rev. 0 | Page 14 of 16 TPSS 20ms 0V Figure 6. Supply Power-Up Sequence RESET > 5ms 10635-007 1. 2. Data Sheet ADV7630 FUNCTIONAL OVERVIEW HDMI RECEIVER HDMI TRANSMITTER The ADV7630 incorporates a 1:2 HDMI splitter with 4:1 multiplexed input receiver that supports all mandatory and many optional 3D formats, HDTV formats up to 1080p, and all display resolutions up to UXGA (1600 x 1200 at 60 Hz). The ADV7630 features two HDMI transmitters: TXA and TXB. Both transmitters support 3D TV formats as well as all HDTV formats up to 1080p 36-bit Deep Color. The TXA and TXB transmitters have separate DDC lines to allow reading EDID data and performing HDCP operations authentication with two independent HDMI sinks. The inclusion of HDCP allows the ADV7630 to receive encrypted video content. The HDMI interface of the ADV7630 allows for the reception of two parallel and independent video streams including authentication of a video receiver, decryption of encoded data at the receiver, and the maintenance of that authentication during transmission, as specified by the HDCP 1.4 protocol. The HDMI-compatible receiver on the ADV7630 incorporates an equalizer that compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance. XpressView fast switching can be implemented with full HDCP authentication available on the background port. HDMI receiver features include: * * * * * * * * * * * * 1:2 HDMI splitter 4:1 HDMI input mux 3D format support 225 MHz HDMI receiver Integrated equalizer for cable lengths up to 30 meters HDCP 1.4 also on background ports Internal HDCP keys 36-/30-bit Deep Color support Repeater support Internal EDID RAM Hot plug assert output pin for each HDMI port CEC controller Both transmitters feature an on-chip microprocessor unit (MPU) with an I2C master to perform HDCP operations and EDID reading operations. I2C INTERFACE The ADV7630 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. The ADV7630 is controlled by an external I2C master device, such as a microcontroller. OTHER FEATURES Other features include the following: * * * * * Rev. 0 | Page 15 of 16 Fully qualified software libraries, driver, and application Programmable interrupt request output pin (INT1) Chip select Temperature range: 0oC to 70oC 14 mm x 14 mm, Pb-free 128-lead TQFP with exposed pad ADV7630 Data Sheet OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 128 1 1.00 REF 12.40 REF 97 96 97 96 128 1 PIN 1 SEATING PLANE EXPOSED PAD TOP VIEW 1.05 1.00 0.95 0.20 0.15 0.09 0.08 COPLANARITY BOTTOM VIEW (PINS DOWN) (PINS UP) 65 64 32 33 VIEW A 0.15 0.10 0.05 0.40 BSC LEAD PITCH 7 0 6.35 REF 65 64 0.23 0.18 0.13 32 33 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-AEE-HD 04-17-2012-A 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.20 MAX Figure 7. 128-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-128-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7630KSVZ 1 Temperature Range 0C to 70C Package Description 128-Lead TQFP_EP Package Option SV-128-1 Z = ROHS Compliant. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10635-0-9/12(0) Rev. 0 | Page 16 of 16