74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Rev. 7 — 30 January 2019 Product data sheet
1. General description
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down
resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches
are transparent, therefore a latch output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up
time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight
latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the state of the latches.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at VCC = 3.0 V
3. Ordering information
Table 1. Ordering information
PackageType number Temperature range
Name Description Version
74ALVCH16373DGG -40 °C to +85 °C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
4. Functional diagram
001aam007
1Q0
1Q1
1OE 2OE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1LE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2LE
Fig. 1. Logic symbol
001aam009
47 3D 1Q01D0 2
1
46 1Q11D1 3
44 1Q21D2 5
43 1Q31D3
11EN1OE
48 C11LE
24 2EN2OE
25 C42LE
6
41 1Q41D4 8
40 1Q51D5 9
38 1Q61D6 11
37 1Q71D7 12
36 2Q02D0 13
35 2Q12D1 14
33 2Q22D2 16
32 2Q32D3 17
30 2Q42D4 19
29 2Q52D5 20
27 2Q62D6 22
26 2Q72D7 23
4D 2
Fig. 2. IEC logic symbol
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 2 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
to internal circuit
mna705
VCC
data input
Fig. 3. Bus hold circuit
001aam010
LELE
to 7 other channels
D
LATCH
1
Q1D0
1LE
1OE
1Q0
LELE
to 7 other channels
D
LATCH
9
Q2D0
2LE
2OE
2Q0
Fig. 4. Logic diagram
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 3 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5. Pinning information
5.1. Pinning
74ALVCH16373
1OE 1LE
1Q0 1D0
1Q1 1D1
GND GND
1Q2 1D2
1Q3 1D3
VCC VCC
1Q4 1D4
1Q5 1D5
GND GND
1Q6 1D6
1Q7 1D7
2Q0 2D0
2Q1 2D1
GND GND
2Q2 2D2
2Q3 2D3
VCC VCC
2Q4 2D4
2Q5 2D5
GND GND
2Q6 2D6
2Q7 2D7
2OE 2LE
001aam008
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Fig. 5. Pin configuration SOT362-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol Pin Description
1OE, 2OE 1, 24 output enable input (active LOW)
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 positive supply voltage
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs
1LE, 2LE 48, 25 latch enable input (active HIGH)
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 4 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
Z = high-impedance OFF-state.
Inputs
nOE nLE nDn
Internal latches Outputs nQn Operating mode
L H L L L
L H H H H
enable and read register
(transparent mode)
L L l L L
LLhH H
latch and read register
(hold mode)
H L l L Z
H L h H Z
latch register and disable
outputs
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +4.6 V
IIK input clamping current VI < 0 V -50 - mA
control inputs [1] -0.5 +4.6 VVIinput voltage
data inputs [1] -0.5 VCC + 0.5 V
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
VOoutput voltage [1] -0.5 VCC + 0.5 V
IOoutput current VO = 0 V to VCC - ±50 mA
ICC supply current - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +85 °C [2] - 600 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 5 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
maximum speed performance
CL = 30 pF 2.3 - 2.7 V
CL = 50 pF 3.0 - 3.6 V
VCC supply voltage
low voltage applications 1.2 - 3.6 V
data inputs 0 - VCC VVIinput voltage
control inputs 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature in free air -40 - +85 °C
VCC = 2.3 V to 3.0 V 0 - 20 ns/VΔt/ΔV input transition rise and fall rate
VCC = 3.0 V to 3.6 V 0 - 10 ns/V
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ [1] Max Unit
Tamb = -40 °C to +85 °C
VCC = 1.2 V VCC - - V
VCC = 1.8 V 0.7VCC 0.9 - V
VCC = 2.3 V to 2.7 V 1.7 1.2 - V
VIH HIGH-level input
voltage
VCC = 2.7 V to 3.6 V 2.0 1.5 - V
VCC = 1.2 V - - 0 V
VCC = 1.8 V - 0.9 0.2VCC V
VCC = 2.3 V to 2.7 V - 1.2 0.7 V
VIL LOW-level input
voltage
VCC = 2.7 V to 3.6 V - 1.5 0.8 V
VI = VIH or VIL
IO = -100 μA; VCC = 1.8 V to 3.6 V VCC - 0.2 VCC - V
IO = -6 mA; VCC = 1.8 V VCC - 0.4 VCC - 0.1 - V
IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V
IO = -12 mA; VCC = 2.3 V VCC - 0.5 VCC - 0.17 - V
IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V
IO = -18 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V
VOH HIGH-level output
voltage
IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V
VI = VIH or VIL
IO = 100 μA; VCC = 1.8 V to 3.6 V - 0 0.20 V
IO = 6 mA; VCC = 1.8 V - 0.09 0.30 V
IO = 6 mA; VCC = 2.3 V - 0.07 0.20 V
IO = 12 mA; VCC = 2.3 V - 0.15 0.40 V
IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V
IO = 18 mA; VCC = 2.3 V - 0.23 0.60 V
VOL LOW-level output
voltage
IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 6 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Symbol Parameter Conditions Min Typ [1] Max Unit
VCC = 1.8 V to 3.6 V
control input; VI = 5.5 V or GND - 0.1 5 μA
IIinput leakage current
data input; VI = VCC or GND - 0.1 5 μA
VI = VIH or VIL; VO = VCC or GND
VCC = 1.8 V to 2.7 V - 0.1 5 μA
IOZ OFF-state output
current
VCC = 2.7 V to 3.6 V - 0.1 10 μA
VI = VCC or GND
VCC = 1.8 V to 2.7 V - 0.1 10 μA
ILIZ OFF-state input
leakage current
VCC = 3.6 V - 0.1 15 μA
VI = VCC or GND; IO = 0 A;
VCC = 1.8 V to 2.7 V - 0.2 40 μA
ICC supply current
VCC = 2.7 V to 3.6 V - 0.2 40 μA
VI = VCC - 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V
per control input - 5 500 μA
ΔICC additional supply
current
per data I/O input - 150 750 μA
VCC = 2.3 V; VI = 0.7 V [2] 45 - - μAIBHL bus hold LOW current
VCC = 3.0 V; VI = 0.8 V [2] 75 150 - μA
VCC = 2.3 V; VI = 1.7 V [2] -45 - - μAIBHH bus hold HIGH current
VCC = 3.0 V; VI = 2.0 V [2] -75 -175 - μA
VCC = 2.7 V [2] 300 - - μAIBHLO bus hold LOW
overdrive current VCC = 3.6 V [2] 450 - - μA
VCC = 2.7 V [2] -300 - - μAIBHHO bus hold HIGH
overdrive current VCC = 3.6 V [2] -450 - - μA
CIinput capacitance - 5.0 - pF
[1] All typical values are measured at Tamb = 25 °C.
[2] Valid for data inputs of bus hold parts only.
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 7 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10.
Symbol Parameter Conditions Min Typ [1] Max Unit
Tamb = -40 °C to +85 °C
nDn to nQn; see Fig. 6 [2]
VCC = 1.2 V - 8.8 - ns
VCC = 1.8 V 1.5 3.2 5.7 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.1 3.9 ns
VCC = 2.7 V 1.0 2.3 3.7 ns
VCC = 3.0 V to 3.6 V [4] 1.0 2.1 3.3 ns
nLE to nQn; see Fig. 7 [2]
VCC = 1.2 V - 7.4 - ns
VCC = 1.8 V 1.5 3.4 5.9 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.2 3.9 ns
VCC = 2.7 V 1.0 2.2 3.5 ns
tpd propagation delay
VCC = 3.0 V to 3.6 V [4] 1.0 2.2 3.2 ns
nOE to nQn; see Fig. 8 [5]
VCC = 1.2 V - 8.9 - ns
VCC = 1.8 V 1.5 4.0 7.3 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.6 5.2 ns
VCC = 2.7 V 1.0 2.9 4.9 ns
ten enable time
VCC = 3.0 V to 3.6 V [4] 1.0 2.3 4.2 ns
nOE to nQn; see Fig. 8 [6]
VCC = 1.2 V - 8.9 - ns
VCC = 1.8 V 1.5 3.2 5.6 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.2 4.1 ns
VCC = 2.7 V 1.0 3.1 4.7 ns
tdis disable time
VCC = 3.0 V to 3.6 V [4] 1.0 2.8 4.1 ns
nLE HIGH; see Fig. 7
VCC = 1.8 V 3.5 1.0 - ns
VCC = 2.3 V to 2.7 V [3] 3.0 1.0 - ns
VCC = 2.7 V 3.0 1.0 - ns
tWpulse width
VCC = 3.0 V to 3.6 V [4] 2.5 1.0 - ns
nDn to nLE; see Fig. 9
VCC = 1.8 V 1.0 -0.1 - ns
VCC = 2.3 V to 2.7 V [3] 1.0 -0.1 - ns
VCC = 2.7 V 1.0 -0.1 - ns
tsu set-up time
VCC = 3.0 V to 3.6 V [4] 1.0 0.0 - ns
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 8 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Symbol Parameter Conditions Min Typ [1] Max Unit
nDn to nLE; see Fig. 9
VCC = 1.8 V 1.2 0.1 - ns
VCC = 2.3 V to 2.7 V [3] 1.5 0.2 - ns
VCC = 2.7 V 1.5 0.4 - ns
thhold time
VCC = 3.0 V to 3.6 V [4] 1.2 0.2 - ns
per flip-flop; VI = GND to VCC [7]
outputs enabled - 16 - pF
CPD power dissipation
capacitance
outputs disabled - 10 - pF
[1] All typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical values are measured at VCC = 2.5 V.
[4] Typical values are measured at VCC = 3.3 V.
[5] ten is the same as tPZL and tPZH.
[6] tdis is the same as tPLZ and tPHZ.
[7] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC
2 × fi × N + Σ(CL × VCC
2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC
2 × fo) = sum of the outputs.
10.1. Waveforms and test circuit
001aam011
nDn input
nQn output
tPHL tPLH
GND
VI
VM
VM
VM
VM
VOH
VOL
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 6. Propagation delay, input (nDn) to data output (nQn)
001aam012
VI
tW
tPHL
VMVMVM
GND
VOH
VOL
nLE input
nQn output
tPLH
VMVM
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 7. Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 9 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
001aal795
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
nQn output
LOW-to-OFF
OFF-to-LOW
nQn output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VMVM
GND
GND
tPZL
tPZH
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig. 8. 3-state enable and disable times
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 9. Data setup and hold times for input (nDn) to input (nLE)
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
2.3 V to 2.7 V and < 2.3 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 10 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 10. Test circuit for measuring switching times
Table 9. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
2.3 V to 2.7 V and
< 2.3 V
VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND
2.7 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND
3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 11 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
11. Package outline
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT362-1 MO-153
sot362-1_po
03-02-19
13-08-05
Unit
mm
max
nom
min
0.15 0.28 0.2 12.6
0.5
0.8
A
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A1A2
1.05
A3bpc D(1)
8°
θE(2) e HEL
1
LpQ v w
1.2 0.25 0.10.25 0.08
y Z
7.9 0.46.0 0.350.05 0.17 0.1 12.4 0.4 0°
0.85
8.3 0.86.2 0.50
pin 1 index
v A
θ
A
D
Lp
Q
E
Z
c
L
1 24
48 25
e
w
y
X
A
HE
bp
A1
A2
detail X
(A3)
0 5 mm
scale
2.5
Fig. 11. Package outline SOT362-1 (TSSOP48)
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 12 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
TTL Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ALVCH16373 v.7 20190130 Product data sheet - 74ALVCH16373 v.6
Modifications: The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Type number 74ALVCH16373DL (SOT370-1) removed.
Package outline drawing SOT362-1 (TSSOP48) updated.
74ALVCH16373 v.6 20120710 Product data sheet - 74ALVCH16373 v.5
Modifications: Table 8 corrected (errata).
74ALVCH16373 v.5 20111117 Product data sheet - 74ALVCH16373 v.4
Modifications: Legal pages updated.
74ALVCH16373 v.4 20100531 Product data sheet - 74ALVCH16373 v.3
74ALVCH16373 v.3 19990920 Product specification - 74ALVCH16373 v.2
74ALVCH16373 v.2 19980629 Product specification - 74ALVCH16373 v.1
74ALVCH16373 v.1 19970321 Product specification - -
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 13 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
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internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
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with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
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data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
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special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 14 / 15
Nexperia 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................4
5.1. Pinning.........................................................................4
5.2. Pin description............................................................. 4
6. Functional description................................................. 5
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................6
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 8
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 12
12. Abbreviations............................................................ 13
13. Revision history........................................................13
14. Legal information......................................................14
© Nexperia B.V. 2019. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 30 January 2019
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2019. All rights reserved
Product data sheet Rev. 7 — 30 January 2019 15 / 15