This is information on a product in full production.
September 2014 DocID026945 Rev 1 1/19
STGIPN3H60AT
SLLIMM™-nano (small low-loss intelligent molded module)
IPM, 3 A - 600 V 3-phase IGBT inverter bridge
Datasheet
-
production data
Features
•IPM 3 A, 600 V, 3-phase IGBT inverter bridge
including control ICs for gate driving and
freewheeling diodes
•Optimized for low electromagnetic interference
•V
CE(sat)
negative temperature coefficient
•3.3 V, 5 V, 15 V CMOS/TTL input comparators
with hysteresis an
•d pull-down resistor
•Undervoltage lockout
•Internal bootstrap diode
•Interlocking function
•Optimized pinout for easy board layout
•85 kΩ NTC for temperature control (UL1434
CA 2 and 4)
Applications
•3-phase inverters for motor drives
•Dish washers, refrigerator comp ressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
This intelligent power module implements a
compact, high-performance AC motor drive in a
simple, rugged design. It is composed of six
IGBTs with freewheeling diodes and three half-
bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. SLLIMM™ is a trademark of
STMicroelectronics.
NDIP-26L
Table 1. Device summary
Order code Marking Package Packaging
STGIPN3H60AT GIPN3H60AT NDIP-26L Tube
www.st.com
Contents STGIPN3H60AT
2/19 DocID026945 Rev 1
Contents
1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DocID026945 Rev 1 3/19
STGIPN3H60AT Internal schematic diagram and pin configuration
19
1 Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
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Internal schematic diagram and pin configuration STGIPN3H60AT
4/19 DocID026945 Rev 1
Table 2. Pin description
Pin Symbol Description
1 GND Ground
2 T NTC thermistor terminal
3V
CC
W Low voltage power supply W phase
4 HIN W High side logic input for W phase
5 LIN W Low side logic input for W phase
6 T NTC thermistor terminal
7 NC Not connected
8 NC Not connected
9V
CC
V Low voltage power supply V phase
10 HIN V High side logic input for V phase
11 LIN V Low side logic input for V phase
12 NC Not connected
13 V
CC
U Low voltage power supply for U phase
14 HIN U High side logic input for U phase
15 T NTC thermistor terminal
16 LIN U Low side logic input for U phase
17 V
boot
U Bootstrap voltage for U phase
18 P Positive DC input
19 U U phase out put
20 N
U
Negative DC input for U phase
21 V
boot
V Bootstrap voltage for V phase
22 V V phase output
23 N
V
Negative DC input for V phase
24 V
boot
W Bootstrap voltage for W phase
25 W W phase output
26 N
W
Negative DC input for W phase
DocID026945 Rev 1 5/19
STGIPN3H60AT Internal schematic diagram and pin configuration
19
Figure 2. Pin layout (top view)
(*) Dummy pin internally connected to P (positive DC input).
Electrical ratings STGIPN3H60AT
6/19 DocID026945 Rev 1
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3. Inverter part
Symbol Parameter Value Unit
V
CES
Each IGBT collector emitter voltage (V
IN(1)
= 0)
1. Applied between
HIN
i
, LIN
i and
G
ND
for i = U, V, W.
600 V
± I
C (2)
2. Calculated according to the iterative formula:
Each IGBT continuous collector current at
T
C
= 25 °C 3A
± I
CP (3)
3. Pulse width limited by max junction tempera ture.
Each IGBT pulsed collector current 18 A
P
TOT
Each IGBT total dissipation at T
C
= 25 °C 8 W
Table 4. Control part
Symbol Parameter Min. Max. Unit
V
OUT
Output voltage applied between OUT
U
, OUT
V
,
OUT
W
- GND V
boot
-18 V
boot
+ 0.3 V
V
CC
Low voltage power supply - 0.3 18 V
V
boot
Bootstrap voltage - 0.3 618 V
V
IN
Logic input volt age applied be tween
HIN
i
, LIN
i and
G
ND
for i = U, V, W - 0.3 V
CC
+ 0.3 V
ΔV
OUT/dT
Allowed output slew rate 50 V/ns
Table 5. Total system
Symbol Parameter Value Unit
V
ISO
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.) 1000 V
T
J
Power chips operating junction temperature -40 to 150 °C
T
C
Module case operating temperature -40 to 125 °C
I
C
T
C
() T
jmax()
T
C
–
R
thj c–
V
CE sat()max()
T
jmax()
I
C
T
C
(),()×
------ ---- ----------- ---------- ----- ---------- ----------- ---- ----------- ---------- ----- ---------- ------=
DocID026945 Rev 1 7/19
STGIPN3H60AT Electrical ratings
19
2.2 Thermal data
Table 6. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction-ambient 50 °C/W
Ele ctr ical characteristics STGI PN3H60AT
8/19 DocID026945 Rev 1
3 Electrical characteristics
T
j
= 25 °C unless otherwise specified.
Note: t
ON
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are
the switching time of IGBT itself under the internally given gate driving condition.
Figure 3. Switching time test circuit
Table 7. Inverter part
Symb ol Parameter Test conditions Min. Typ. Max. Unit
V
CE(sat)
Collector-emitter
saturati on vol t age
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A - 2.15 2.6 V
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A, T
J
= 125 °C -1.65
I
CES
Collector-cut off current
(V
IN(1)
= 0 “logic state”) V
CE
= 550 V, V
CC
= V
Boot
= 15 V - 250 µA
V
F
Diode forward voltage V
IN(1)
= 0 “logic state”, I
C
= 1 A - 1.7 V
Inductive load switching time and energy
t
on
Turn-on time
V
DD
= 300 V,
V
CC
= V
boot
= 15 V,
V
IN(1)
= 0 - 5 V,
I
C
= 1 A
(see Figure 4)
-275
ns
t
c(on)
Crossover time (on) - 90
t
off
Turn-off time - 890
t
c(off)
Crossover time (off) - 125
t
rr
Reverse recovery time - 50
E
on
Turn-on switching losses - 18 µJ
E
off
Turn-off switch ing losses - 13
1. Applied between
HIN
i
, LIN
i and
G
ND
for i = U, V, W (LIN inputs are active-low).
VBOOT>VCC
L
IC
VCE
VCC
INPUT
0
1
BUS
Lin
Hin
Vcc
LVG
HVG
OUT
BOOT
GND
DocID026945 Rev 1 9/19
STGIPN3H60AT Electri cal chara ct er istics
19
Figure 4. Switching time definition
3.1 Control part
V
CE
I
C
I
C
V
IN
t
ON
t
C(ON)
VIN(ON) 10% IC 90% IC 10% VCE
(a) turn-on (b) turn-off
t
rr
100% IC 100% IC
V
IN
V
CE
t
OFF
t
C(OFF)
VIN(OFF) 10% VCE 10% IC
AM09223V1
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Ty p. Max. Unit
V
CCthON
Undervo lt a ge turn -on thre sho ld 9.1 9.6 10.1 V
V
CCthOFF
Undervo lt a ge turn -off threshol d 7.9 8.3 8.8 V
V
CChys
Undervo lt a ge hy stereses 0.9 V
I
qccu
Undervo lt age quies ce nt sup ply
current V
CC
< 7.9 V 250 330 µA
I
qcc
Quiescent current V
CC
= 15 V 350 450 µA
Ele ctr ical characteristics STGI PN3H60AT
10/19 DocID026945 Rev 1
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Ty p. Max. Unit
V
boot_thON
Undervo lt a ge turn -on thre sho ld 8.5 9.5 10.5 V
V
boot_thOFF
Undervo lt a ge turn -off threshol d 7.2 8.3 9.2 V
V
boothys
Undervo lt a ge hy stereses 0.9 V
I
qboot
Quiescent current 250 µA
R
DS(on)
Boot st rap driv er on-re si st a nc e V
CC
> 12.5 V 125 Ω
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
(1)
1. See Figure 5: Dead time and interlocking definition.
Symbol Paramete r Test conditions Min. Typ. M ax. Unit
V
il
Low level logic inpu t voltage 1.1 V
V
ih
High level logic input voltage 1.8 V
I
il
Low level logic input current V
IN (2)
= 0
2. Applied between
HIN
i
, LIN
i and
G
ND
for i = U, V, W
-1 µA
I
ih
High level logic input current V
IN (1)
= 15 V 20 70 µA
Dt Dead tim e 320 ns
Figure 5. Dead time and interlocking definition
DT DT
DT
LIN
HIN
LVG
HVG
Interlocking function
AM03794v1
DocID026945 Rev 1 11/19
STGIPN3H60AT Electri cal chara ct er istics
19
3.1.1 NTC thermistor
Equation 1: resistance variation vs. temperature
Where T are temperatures in Kelvins
Figure 6. NTC resistance vs. temperature
Table 11. NTC thermistor
Symbol Parameter Test conditions Min. Ty p. Max. Unit.
R
25
Resistance T
= 25 °C 85 kΩ
R
100
Resistance T
= 100 °C 5388 Ω
B B-constant T
= 25 °C to 100 °C 4092 K
T Operating temperature -25 125 °C
RT() R
25
e
B1
T
--- 1
298
------- ---–


⋅=
0
500
1.000
1.500
2.000
2.500
3.000
3.500
-40 -20 0 20 40 60 80 100 120 140
NTC [kΩ]
[°C]
Min
Max
Typ
GIPD17220131349FSR
Ele ctr ical characteristics STGI PN3H60AT
12/19 DocID026945 Rev 1
Figure 7. NTC resistance vs. temperature (zoom)
0
5
10
15
20
25
30
35
40
50 70 90 110 130 150
NTC [kΩ]
[°C]
Min
Max
Typ
GIPD17220131350FSR
DocID026945 Rev 1 13/19
STGIPN3H60AT Application information
19
4 Application information
Figure 8. Typical application circuit
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Application information STGIPN3H60AT
14/19 DocID026945 Rev 1
4.1 Recommendations
•Input signals HIN, LIN are active-high logic. A 500 kΩ (typ.) pull-down resistor is built-in
for each input. To prevent input signal oscillation, the wiring of each input should be as
short as possible and the use of RC filters (R1, C1) on each input signal is suggested.
The filters should be done with a time constant of about 100ns and must be placed as
close as possible to the IPM input pins.
•The bypass capacitor Cvcc (aluminum or tantalum) is recommended to reduce the
transient circuit demand on the power supply. In addition, a decoupling capacitor C2
(from 100 to 220 nF, ceramic with low ESR) is suggested, to reduce high frequency
switching noise distributed on the power supply lines. It must be placed as close as
possible to each Vcc pin and in parallel to the bypass capacitor.
•The use of RC filter (RSF, CSF) for current monitoring is recommended to improve
noise immunity. The filter must be placed as close as possible to the microcontroller or
to the Op-amp.
•The decoupling capacitor C3 (from 100 to 220 nF, ceramic with low ESR), in parallel to
each Cboot, is recommended in order to filter high frequency disturbances.
•The Zener diodes DZ1 between the Vcc pins and GND and in parallel to each Cboot is
suggested in order to prevent overvoltage.
•The decoupling capacitor C4 (from 100 to 220 nF, ceramic with low ESR) in parallel to
the electrolytic capacitor Cvdc is recommended, in order to prevent surge destruction.
Both capacitors C4 and Cvdc should be placed as close as possible to the IPM (C4 has
priority over Cvdc).
•By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an opto-coupler is possible.
•Low inductance shunt resistors should be used for phase leg current sensing
•In order to avoid malfunctions, the wiring between N pins, the shunt resistor and
PWR_GND should be as short as possible.
•It is recommended to connect SGN_GND to PWR_GND at only one point (near the
terminal of shunt resistor), in order to avoid any malfunction due to power ground
fluctuation.
Note: For further details refer to AN4043.
Table 12. Recommended operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
PN
Supply voltage Applie d between P-Nu, Nv ,
Nw 300 500 V
V
CC
Control supply voltage Applied between V
CC
-
GND 12 15 17 V
V
BS
High side bias voltage Applied between V
BOOTi
-
OUT
i
for i = U, V, W 11.5 17 V
t
dead
Blanking time to prevent
Arm-short For each input signal 1.5 µs
f
PWM
PWM input signal -40°C < T
c
< 100°C
-40°C < T
j
< 125°C 25 kHz
T
C
Case operation temperature 100 °C
DocID026945 Rev 1 15/19
STGIPN3H60AT Package mechanical data
19
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPAC K is an ST tradema rk.
Figure 9. NDIP-26 L drawin g
b1,b3
b,b2
c
c1
BASE METAL
WITH PLATING
SECTION F-F&G-G
D
E
eB1
eB2
e
b
D1
A3
e1
D2
A1
A4
PIN 1 PIN 16
PIN 1
PIN 26 PIN 17
PIN 26 PIN 17
L
A
A2
FF
GG
b2
D3
PIN 16
0.075
0.075
PIN#1 ID
8278949B
Package mechanical data STGIPN3H60AT
16/19 DocID026945 Rev 1
Table 13.NDIP-26L mechanical data
Dim. mm.
Min. Typ. Max.
A4.40
A1 0.80 1.00 1.20
A2 3.00 3.10 3.20
A3 1.70 1.80 1.90
A4 5.70 5.90 6.10
b 0.53 0.72
b1 0.52 0.60 0.68
b2 0.83 1.02
b3 0.82 0.90 0.98
c 0.46 0.59
c1 0.45 0.50 0.55
D 29.05 29.15 29.25
D1 0.50 0.77 1.00
D2 0.35 0.53 0.70
D3 29.55
E 12.35 12.45 12.55
e 1.70 1.80 1.90
e1 2.40 2.50 2.60
eB1 16.10 16.40 16.70
eB2 21.18 21.48 21.78
L 1.24 1.39 1.54
DocID026945 Rev 1 17/19
STGIPN3H60AT Package mechanical data
19
Figure 10. NDIP-26L tube dimensions (dimensions are in mm.)
Note: Base quantity 17 pcs, bulk quantity 476 pcs.
ANTIS TATIC S 03 PVC
AM10474v1
8313150_A
Revision history STGIPN3H60AT
18/19 DocID026945 Rev 1
6 Revision history
Table 14. Document revision history
Date Revision Changes
30-Sep-2014 1Initi al rele as e.
DocID026945 Rev 1 19/19
STGIPN3H60AT
19
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