74LCX08MTCX - APTINA IMAGING - Datasheet.Directory

74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Publication Order Number:

74LCX08/D

August-2017, Rev. 2

74LCX08

Low Voltage Quad 2-Input AND Gate with 5V

Tolerant Inputs

Features

■5V tolerant inputs

■2.3V–3.6V VCC specifications provided

■5.5ns tPD max. (VCC = 3.3V), 10µA ICC max.

■Power down high impedance inputs and outputs

■±24mA output drive (VCC = 3.0V)

■

■Latch-up performance exceeds JEDEC 78 conditions

■ESD performance:

– Human body model > 2000V

– Machine model > 150V

■Leadless DQFN package

General Description

The LCX08 contains four 2-input AND gates. The inputs

tolerate voltages up to 7V allowing the interface of 5V

systems to 3V systems.

The 74LVX08 is fabricated with advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Note:

1. DQFN package available in Tape and Reel only.

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74LCX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LCX08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX08BQX(1) MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

74LCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements proprietary noise/EMI reduction circuitry

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Connection Diagrams

Pin Assignments for SOIC, SOP, and TSSOP

Pad Assignments for DQFN

(Top View)

Pin Description

Logic Symbol

IEEE/IEC

Pin Names Description

An, BnInputs

OnOutputs

(Bottom View)

DAP No Connect

Note: DAP (Die Attach Pad)

74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Note:

2. IO Absolute Maximum Rating must be observed.

Recommended Operating Conditions(3)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. ON

Semiconductor does not recommend exceeding them or designing to absolute maximum ratings.

Note:

3. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

VCC Supply Voltage –0.5V to +7.0V

VIDC Input Voltage –0.5V to +7.0V

VODC Output Voltage, Output in HIGH or LOW State(2) –0.5V to VCC + 0.5V

IIK DC Input Diode Current, VI < GND –50mA

IOK DC Output Diode Current

VO < GND –50mA

VO > VCC +50mA

IODC Output Source/Sink Current ±50mA

ICC DC Supply Current per Supply Pin ±100mA

IGND DC Ground Current per Ground Pin ±100mA

TSTG Storage Temperature –65°C to +150°C

Symbol Parameter Min. Max. Units

VCC Supply Voltage

Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0 5.5 V

VOOutput Voltage, HIGH or LOW State 0 VCC V

IOH / IOL Output Current

VCC = 3.0V–3.6V ±24 mA

VCC = 2.7V–3.0V ±12

VCC = 2.3V–2.7V ±8

TAFree-Air Operating Temperature –40 85 °C

∆t / ∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns / V

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

DC Electrical Characteristics

AC Electrical Characteristics

Note:

4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two

separate outputs of the same device. The specification applies to any outputs switching in the same direction,

either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).

Symbol Parameter VCC (V) Conditions

TA = –40°C to +85°C

UnitsMin. Max.

VIH HIGH Level Input Voltage 2.3–2.7 1.7 V

2.7–3.6 2.0

VIL LOW Level Input Voltage 2.3–2.7 0.7 V

2.7–3.6 0.8

VOH HIGH Level Output Voltage 2.3–3.6 IOH = –100µA VCC – 0.2 V

2.3 IOH = –8mA 1.8

2.7 IOH = –12mA 2.2

3.0 IOH = –18mA 2.4

IOH = –24mA 2.2

VOL LOW Level Output Voltage 2.3–3.6 IOL = 100µA 0.2 V

2.3 IOL = 8mA 0.6

2.7 IOL = 12mA 0.4

3.0 IOL = 16mA 0.4

IOL = 24mA 0.55

IIInput Leakage Current 2.3–3.6 0 ≤ VI ≤ 5.5V ±5.0 µA

IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA

ICC Quiescent Supply Current 2.3–3.6 VI = VCC or GND 10 µA

3.6V ≤ VI ≤ 5.5V ±10

∆ICC Increase in ICC per Input 2.3–3.6 VIH = VCC – 0.6V 500 µA

Symbol Parameter

TA = –40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V,

CL = 50pF

VCC = 2.7V,

CL = 50pF

VCC = 2.5V ± 0.2V,

CL = 30pF

Min. Max. Min. Max. Min. Max.

tPHL, tPLH Propagation Delay 1.5 5.5 1.5 6.2 1.5 6.6 ns

tOSHL, tOSLH Output to Output Skew(4) 1.0 ns

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Dynamic Switching Characteristics

Capacitance

Symbol Parameter VCC (V) Conditions

TA = 25°C

UnitTypical

VOLP Quiet Output Dynamic Peak VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6

VOLV Quiet Output Dynamic Valley VOL 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V

2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7pF

COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25 pF

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

AC Loading and Waveforms (Generic for LCX Family)

Figure 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

Symbol

VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC / 2

Vmo 1.5V 1.5V VCC / 2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH – 0.3V VOH – 0.3V VOH – 0.15V

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Schematic Diagram (Generic for LCX Family)

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74LCX08 — Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs

Tape and Reel Specification

Tape Format for DQFN

Tape Dimensions inches (millimeters)

Reel Dimensions inches (millimeters)

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

BQX Leader (Start End) 125 (Typ.) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (Typ.) Empty Sealed

Tape Size A B C D N W1 W2

12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

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