ZABG6002
ZABG6002
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LOW POWER 6 STAGE FET LNA AND MIXER BIAS CONTROLLER
Summary
The ZABG6002 is a programmable low power depletion mode FET bias and mixer controller intended primarily for
satellite Low Noise Blocks (LNBs). Designed to provide system flexibility the ZABG6002 can be programmed to bias
six low noise amplifier (LNA) stages or four LNA and two active mixer stages, allowing the ZABG6002 to be used in
several syste m designs.
Combining advanced IC process and packaging techniques, the ZABG6002 operates with minimal current over a
wide supply voltage. The small package and reduced component count minimizes the PCB area whilst enhancing
overall LNB reliability.
Features
• Six stage FET bias controller, two configurable as
mixer stages
• Operating range of 3.0V to 8.0V
• Amplifier FET drain voltages set at 2.0V, mixer
drain voltage set at 0.25V
• Amplifier FET drain current selectable from 0 to
15mA, mixer current from 0 to 7.5mA
• Switchable FET’s for power management
• FET drain voltages and currents held stable over
temperature and VCC variations
• FETs protected against ov erstress during power-
up and power-down.
• Internal negative supply generator allo wing single
supply operation (available for external use)
• Low quiescent supply current, 1.6mA typical
• Low external component count
Pin Assignments
QFN2044
QSOP20
Applications
• Twin LNB’s
• Quad LNB’s
• US LNB’s
• Microwave links
• PMR and Cellular telephon e systems
Twin LNB System Diagrams
ZABG
6002 ZXHF
5002
Horizontal Vertical
ZABG
6002 ZXHF
5002
Horizontal Vertical
ZABG
6002
2x2 MUX
ZLNB
102
Left
Right
ZABG
6002
2x2 MUX
ZLNB
102
Left
Right
G2
Gnd
D3
G3
Cnb1
G1
D4
Vcc
D1
D5D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1RcalM
G4
G2
Gnd
D3
G3
Cnb1
G1
D4
Vcc
D1
D5D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1RcalM
G4
G2
Gnd
D3
G3
Cnb1
G1
D4
Vcc
D1
D5D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1RcalM
G4
CsubCsubCsub
G1
D2
G2
D4
D5
Rcal2
Rcal1
G4
RcalM
Gnd
G3
D3
D6
G5
CsubCnb2
G6
Cnb1
D1 1Vcc
G1
D2
G2
D4
D5
Rcal2
Rcal1
G4
RcalM
Gnd
G3
D3
D6
G5
CsubCnb2
G6
Cnb1
D1 1Vcc
ZABG6002
ZABG6002
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Device Description
The ZABG series of devices are designed to meet the bias requirements of GaAs and HEMT FETs commonly used
in satellite receiver LNBs with a minimum of external components whilst operating from a minimal voltage supply
and using minimal current.
The ZABG6002 has six FET bias stages that can be user programmed to provide either a two plus four
arrangement of amplifier FET stages or a two plus two arrangement of amplifier FET stages along with two active
mixer FET stages. Programming of the FET bias stage arrangement and the operating currents of each FET group
is achieved by resistors connected to the Rcal1, Rcal2 and RcalM pins, allowing input FETs to be biased for
optimum noise, amplifier FETs for optimum gain and mixer FETs (if used) for optimum conversion gain. Amplifier
FETs can be operated at currents in the range 0 to 15mA and mixer FETs in the range 0.5 to 7.5mA.
Drain voltages of amplifier stages are set at 2.0V and mixer stages at 0.3V. The drain supplies are current limited to
approximately 5% above the operating currents set by their associat ed Rcal resistors.
As an additional feature the Rcal pins can also be used as logic inputs to disable pairs of FETs as part of a power
management scheme or simply an alternative to LNA switching. Driven to a logic high (>3.0V), the inputs disable
their associated FET bias stages by switching gate feeds to -2.5V and drain feeds open circuit.
Depletion mode FETs require a negative voltage bias supply when operated in grounded source circuits. The
ZABG6002 includes an integrated low noise switched capacitor DC-DC converter generating a regulated output of -
2.5V to allow single supply operation. To aid efficiency and 3.3V systems the ZABG6002 has been design to used
with supply rails of 3.3V to 8V
It is possible to use less than the devices full complement of FET bias controls, unused drain and gate connections
can be left open circuit without affecting operation of the remaining bias circuits.
To protect the external FETs the circuits have been designed to ensure that, under any conditions including power
up/down transients, the gate drive from the bias circuits cannot exceed -3V. Additionally each stage has its own
individual current limiter. Furthermore if the negative rail experiences a fault condition, such as overload or short
circuit, the drain supply to the FETs will shut down avoiding excessive current flow.
The ZABG6002 is available in the 20 pin 4mm x 4mm QFN or QSOP20 pa ckage.
Device operating temperature is -40°C to 85°C to suit a wide range of environmental conditions.
ZABG6002
ZABG6002
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Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.6 to +10 V
Supply Current 100 mA
Power Dissipation 600 mW
Operating Temperature Range -40 to +85 °C
Storage Temperature Range -40 to 150 °C
Electrical Characteristics Measured at TAMB = 25°C, VCC = 3.3V (Note 1), R CAL1 = RCAL2 = 36K (setting ID1/2/4/5 to 10mA),
RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated
Parameter Conditions Symbol Min. Typ. Max. Unit
Operating Voltage Range VCC 3.0 8.0 V
Supply Current ID1-6 = 0 ICC 1.6 4.0 mA
ID1-6 = 10mA, no RCALM I
CC(L) 62 64 mA
Substrate Voltage ICSUB = 0 VCSUB -3.0 -2.65 -2.0 V
ICSUB = -200uA VCSUB(L) -2.55 -2.0 V
Oscillator Frequency FOSC 150 260 600 kHz
Gate Characteristics
Gate (G1 to G6, resistor RCALM not present)
Current Range IG -100 +500 uA
Voltage Low ID = 12mA, IG = -10uA VG(L) -3.0 -2.5 -2.0 V
Voltage High ID = 8mA, IG = 0 VG(H) 0 0.7 1.0 V
Voltage Disabled (*1) ID = 0, IG = -10uA,
V RCAL1-2 = 3.0V VG(DIS) -3.0 -2.5 -2.0 V
Gate (G3 and G6, resistor RCALM present)
Current Range IG -100 +500 uA
Voltage Low ID = 6mA, IG = -10uA VG(L) -3.0 -2.5 -2.0 V
Voltage High ID = 4mA, IG = 0 VG(H) 0 0.7 1.0 V
Voltage Disabled (*1) ID = 0, IG = -10uA,
V RCAL2 = V RCALM 3.0V VG(DIS) -3.0 -2.5 -2.0 V
Drain Characteristics
Drain (D1 to D6, resistor RCALM not present)
Current Range ID 0 15 mA
Current Operating Standard Application
Circuit ID(OP) 8 10 12 mA
Current Disabled (*1) V
D = 0, VRCAL = 3.0V ID(DIS) 10 uA
Voltage Operating ID = 10mA VD(OP) 1.8 2.0 2.2 V
ZABG6002
ZABG6002
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Electrical Characteristics (Cont.) Measured at TAMB = 25°C, VCC = 3.3V (Note 1), RCAL1 = RCAL2 = 36K (setting ID1/2/4/5 to
10mA), RCALM = 68K (setting ID3/6 to 5mA) unless otherwise stated
Parameter Conditions Symbol Min. Typ. Max. Unit
Drain Characteristics
Drain (D3 and D6, resisto r RCALM present)
Current Range IDM 0.5 7.5 mA
Current Operating Standard Application
Circuit IDM(OP) 4 5 6 mA
Current Disabled (*1) VD = 0, VRCAL = 3.0V,
RCALM not present IDM(DIS) 10 uA
Voltage Operating ID = 5mA VDM(OP) 0.25 0.3 0.35 V
RCAL(1 and 2)
Disable Threshold (*1) V
RCAL(DIS) 1.8 2.7 3.0 V
Input Current VRCAL = 3.0V IRCAL(DIS) 1.7 10 uA
RCALM
Disable Threshold (*1) R
CALM(DIS) 1.5M 3.3M 5.0M Ω
RCALM Range RCALM 39k 390k
Ω
Voltage and Temperature dependence (RCALM not present)
delta ID vs VCC V
CC = 3.3 to 8.0V dID/dVCC 1.2 %/V
delta ID vs TOP T
OP = -40°C to +85°C dID/dTOP 0.05 %/°C
delta VD vs VCC V
CC = 3.3 to 8.0V dVD/dVCC 0.05 %/V
delta VD vs TOP T
OP = -40°C to +85°C dVD/dTOP 50 ppm/°C
Output Noise
Drain Voltage CGATE-GND = 10nF,
CDRAIN-GND = 10nF VD(NOISE) 0.02 Vpk-pk
Gate Voltage CGATE-GND = 10nF,
CDRAIN-GND = 10nF VG(NOISE) 0.005 Vpk-pk
Notes: 1. To disable FET stages 3 and 6, pin RCAL2 must be set to 3V or above and pin RCALM should be open circuit. See applications section for
further information.
2. The characteristics are measured using up to three external reference resistors, RCAL1, RCAL2 and RCALM, wired from pins RCAL1/2/M to ground.
Resistor RCAL1 sets the drain current of FETs 1 and 4. If RCALM is not present, resistor RCAL2 sets the drain currents of FETs 2, 3, 5 and 6. If RCALM
is present, resistor RCAL2 sets the drain currents of FETs 2 and 5 and RCALM sets the drain currents of FETs 3 and 6.
3. The negative bias voltages are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB of value 47nF are required for
this purpose.
4. The QFN2044 exposed pad must either be connected to Csub or left open circuit.
5. Noise voltage measurements are made with FETs and gate and drain capacitors of value 10nF in place. Noise voltages are not measured in production.
6. ESD sensitive, handling precautions are recommended.
ZABG6002
ZABG6002
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Typical Characteristics Measured at TAMB = 25°C, VCC = 3.3V, RCAL1 = RCAL2 = 36K (setting ID to 10mA), RCALM = 68K (setting
ID3/6 to 5mA) unless otherwise stated
Z ABG6002 Drain Vol tage (D1 - D6) vs Temperature
1.7
1.8
1.9
2
2.1
2.2
2.3
-40 -20 0 20 40 60 80
Temper at ur e ( ° C)
Drai n Voltage (V)
Z ABG6002 Drain Current ( D 1 - D6) vs Temperat ure
0
2
4
6
8
10
12
14
16
18
20
-40-200 20406080
Temper at ur e ( ° C)
Dra in Curr en t (mA)
Z ABG6002 Drain Voltage (D3 & D6 onl y) vs Temperature
0
0.1
0.2
0.3
0.4
0.5
-40 -20 0 20 40 60 80
Tempera tur e ( ° C)
Drain Vol tage (V)
ZA BG6002 Drain Current (D3 & D6 only) vs Temperature
0
2
4
6
8
10
-40-200 20406080
Temperat ur e (°C)
Drain Curr e nt ( mA)
ZABG6002 Substrat e Voltage vs Substrate Current
-3
-2.8
-2.6
-2.4
-2.2
-2
0 50 100 150 200 250
Substrat e Curr ent ( uA)
Substrat e Volt age ( V)
ZABG6002
ZABG6002
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Typical Characteristics (Cont.) Measured at TAMB = 25°C, VCC = 3.3V, RCAL1 = RCAL2 = 36K (setting ID to 10mA), RCALM = 68K
(setting ID3/6 to 5mA) unless otherwise stated
Z ABG6002 Drain Vol tage vs Drain Current (D1-D6)
1.8
1.9
2
2.1
2.2
051015
Drain Current (mA)
Drain Voltage ( V)
Z ABG6002 Drain Current vs R
CAL
0
5
10
15
10 100 1000
R
CAL
(k)
Drain Cur rent (mA)
Z ABG6002 Drain Vol tage vs Drai n Cu rrent (D3 & D6 only)
0
0.1
0.2
0.3
0.4
0.5
0510
Drai n Curr ent (mA )
Drai n Volt age ( V)
Z ABG6002 Drain Current vs R
CALM
0
5
10
10 100 1000
R
CAL
(k)
Dra in Current (mA)
ZABG6002
ZABG6002
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Application Information
The ZABG6002 is a flexible device and can b e set up in a number of ways.
1. 6 LNA stages to provide standard bias to the GaAs o r HEMT FET’ s
2. 4 LNA stages to provide standard bias to the GaAs or HEMT FET’s plu s 2 active mixer stages
3. Power down FET groups for LNA switching or power saving.
The truth table below shows the function of these features.
FET Stage
Rcal Pin Resistor Termination 1st LNA
Stages 2nd LNA
Stages 3rd LNA/Mixer
Stages
Rcal1 Rcal2 RcalM Bias 1 Bias 4 Bias 2 Bias 5 Bias 3 Bias 6
Gnd Gnd Open On On On On On On
Gnd Gnd Gnd On On On On Mixer Mixer
Gnd 3V Open On On Off Off Off Off
Gnd 3V Gnd On On Off Off Mixer Mixer
3V Gnd Open Off Off On On On On
3V Gnd Gnd Off Off On On Mixer Mixer
3V 3V Open Off Off Off Off Off Off
3V 3V Gnd Off Off Off Off Mixer Mixer
ZABG6002 in 6 LNA mode
Below is a partial applications circuit for the ZABG6002 showing all external components needed for biasing one of
the six FET stages available as a normal LNA bias. Each bias stage is provided with a gate and drain pin. The drain
pin provides a regulated 2.0V supply that includes a drain current monitor. The drain current taken by the external
FET is compared with a user selected level, generating a signal that adjusts the gate voltage of the FET to obtain
the required drain current. If for any reason, an attempt is made to draw more than the user set drain current from
the drain pin, the drain voltage will be reduced to ensure excess current is not taken. The gate pin drivers are also
current limited.
The bias stages are split up into two groups, with the drain curre nt of each group set by an external RCAL resistor.
RCAL1 sets the drain currents of stages 1 and 4, whilst RCAL2 sets the drain currents of stag es 2,3,5 and 6.
JF2
Vcc
L*
L*
C*
C* C1
10nF
C2
10nF CNB
47nF
CSUB
47nF
RCAL2
* Stripline Eleme nts
RCAL1
36k
G2
Gnd
D3
G3
Cnb1
G1
D4
Vcc
D1
D5
D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1
RcalM
G4
ZABG6002
JF2
Vcc
L*
L*
C*
C* C1
10nF
C2
10nF CNB
47nF
CNB
47nF
CSUB
47nF
RCAL2
* Stripline Eleme nts
RCAL1
G2
Gnd
D3
Cnb1
G1
D4
Vcc
D1
D5
D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1
RcalM
G4
ZABG6002
36k
ZABG6002
ZABG6002
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This allows the optimization of drain currents for differing tasks such as input stages where noise can be critical and
later amplifier stages where gain may be more important. A graph showing the relationship between the value of
RCAL and ID is provided in the Typical Characteristics section of this datasheet. To ensure that the mixer function is
disabled the RCALM pin should be left open circuit.
ZABG6002 in 4 LNA and 2 active mixer mode
Below is a partial applications circuit for the ZABG6002 showing all external components needed for biasing one of
the four FET stages available for LNA bias and one of the two mixer bias stages. Each LNA bias stage is provided
with a gate and drain pin. The drain pin provides a regulated 2.0V supply that includes a drain current monitor. Each
mixer bias stage is provided with a gate and drain pin. The drain pin provides a regulated 0.3V supply that includes
a drain current monitor but optimized to the requirements of an active mixer. The drain current taken by the external
FET (LNA and Mixer) is compared with a user selected level, generating a signal that adjusts the gate voltage of the
FET to obtain the required drain current. If for any reason, an attempt is made to draw more than the user set drain
current from the drain pin, the drain voltage will be reduced to ensure excess current is not taken. The gate pin
drivers are also current limited.
JF2
Vcc
L*
L*
C*
C* C1
10nF
C2
10nF
CNB
47nF
CSUB
47nF
RCAL2
36k
* Stripline Elem ents
RCAL1
36k
G2
Gnd
D3
G3
Cnb1
G1
D4
Vcc
D1
D5
D2
G5
Cnb2
Csub
D6
G6
Rcal2
Rcal1
RcalM
G4
ZABG6002
RCALM
68k
JFM
L*
L*
C*
C*C3
10nF
C4
10nF
VLO
The bias stages are split up into three groups, with the drain current of each group set by an external RCAL resistor.
RCAL1 sets the LNA drain currents of stages 1 and 4 and RCAL2 sets the drain currents of LNA stages 2 and 5. RCALM
sets the mixer drain currents of stages 3 and 6. This allows the optimization of drain currents for differing tasks such
as input stages where noise can be critical and later amplifier stages where gain may be more important. A graph
showing the relationship between the value of RCAL and ID is provided in the Typical Characteristics section of this
datasheet.
ZABG6002
ZABG6002
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General Operation
In both modes the RCAL 1 and RCAL 2 pins can also be used as logic inputs. If set to a logic high state (>3.0V), the
associated FET bias stages programmed for LNA use (2V drains) are disabled by driving gate pins to -2,5V and
switching drain pins open-circuit. This feature can be used as part of a power management system that turns off
any unwanted stages in a multi input receiver.
The ZABG6002 includes a switched capacitor DC-DC converter that is used to generate the negative supply
required to bias depletion mode FETs used in common source circuit configuration as shown above. This converter
uses two external capacitors, CNB the charge transfer capacitor and CSUB the output reservoir capacitor. The circuit
provides a regulated -2.5V supply both for gate driver use and for external use if required (for extra discrete bias
stages, mixer bias, local oscillator bias etc.). The -2.5V supply is available from the CSUB pin.
If any bias stages are not required, their gate and drain pins may be left open circuit. If all bias stages associated
with an RCAL resistor are not required, then this resistor may be omitted.
It must be noted that the exposed pad of the QFN package must be either left floating or conn ected to Csub.
Ordering Information
Device Package Reel size (inches) Tape width (mm) Quantity per reel
ZABG6002JB20TC QFN2044 13 12 3,000
ZABG6002Q20TC QSOP20 13 16 2,500
Marking Information
Part Name
Pin 1
ZABG6002
YYWW
Date Code
ZABG
6002
YYWW
Pin 1
Part Name
Date Code
Year/Week
QFN2044 QSOP20
ZABG6002
ZABG6002
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Package Outline Dimensions
QSOP20
DIM Millimeters Inches
MIN MAX MIN MAX
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 1.50 0.049 0.059
D 8.56 8.74 0.337 0.344
ZD 0.058 REF 1.47 REF
b 0.20 0.30 0.008 0.012
c 0.18 0.25 0.007 0.010
e 0.64 BSC 0.025 BSC
E 5.79 6.20 0.228 0.244
E1 3.81 3.99 0.150 0.157
L 0.41 1.27 0.016 0.050
θ 0° 8° 0° 8°
h 0.25 0.50 0.010 0.020
ZABG6002
ZABG6002
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Package Outline Dimensions (Cont.)
QFN2044
DIM Min. Max. Typ.
D 3.95 4.05 4.00
E 3.95 4.05 4.00
D2 2.40 2.60 2.50
E2 2.40 2.60 2.50
A 0.57 0.63 0.60
A1 0 0.05 0.02
A3 — — 0.15
b 0.20 0.30 0.25
L 0.35 0.45 0.40
e — — 0.50
z — — 0.875
aaa 0.25
bbb 0.10
ccc 0.10
ZABG6002
ZABG6002
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