© Semiconductor Components Industries, LLC, 2005
October, 2020 − Rev. 2
1Publication Order Number:
NC7WZ125/D
TinyLogic UHS Dual Buffer
with 3-STATE Outputs
NC7WZ125
Description
The NC7WZ125 is a Dual Non−Inverting Buffer with independent
active LOW enables for the 3−STATE outputs. The Ultra High Speed
device is fabricated with advanced CMOS technology to achieve
superior switching performance with high output drive while
maintaining low static power dissipation over a broad VCC operating
range. The device is specified to operate over the 1.65 V to 5.5 V VCC
operating range. The inputs and outputs are high impedance when
VCC is 0 V. Inputs tolerate voltages up to 5.5 V independent of VCC
operating range. Outputs tolerate voltages above VCC when in the
3−STATE condition.
Features
•Space Saving US8 Surface Mount Package
•MicroPak™ Pb−Free Leadless Package
•Ultra High Speed: tPD 2.6 ns Typ. into 50 pF at 5 V VCC
•High Output Drive: ±24 mA at 3 V VCC
•Broad VCC Operating Range: 1.65 V to 5.5 V
•Matches the Performance of LCX when Operated at 3.3 V VCC
•Power Down High Impedance Inputs / Outputs
•Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation
•Outputs are Overvoltage Tolerant in 3−STATE Mode
•Proprietary Noise / EMI Reduction Circuitry Implemented
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A2Y2
1Y1
A1
OE1EN
OE2
IEEE/IEC
Figure 1. Logic Symbol
EN 1
WZ25
ALYW
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
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P3, WZ25 = Specific Device Code
KK = 2−Digit Lot Run Traceability Code
XY = 2−Digit Date Code Format
Z = Assembly Plant Code
A = Assembly Site
L = Wafer Lot Number
YW = Assembly Start Week
UQFN8
1.6X1.6, 0.5P
CASE 523AY
US8
CASE 846AN
P3KK
XYZ
NC7WZ125
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2
Connection Diagrams
Figure 2. Connection Diagram
(Top View)
Figure 3. Pad Assignments for MicroPak
(Top Thru View)
1
OE2
2
Y1
3
A2
OE1
7
A1
6
Y2
5
VCC 8 4 GND
OE1VCC
1
2
3
8
7
6
45
A1OE2
Y2Y1
GND A2
PIN DESCRIPTIONS
Pin Names Description
OEn Enable Inputs for 3−STATE Outputs
An Input
Yn 3−STATE Outputs
FUNCTION TABLE
Inputs Output
OE AnYn
L L L
L H H
H L Z
H H Z
H = HIGH Logic Level
L = LOW Logic Level
Z = 3−STATE
NC7WZ125
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3
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VCC Supply Voltage −0.5 6.5 V
VIN DC Input Voltage (Note 1) −0.5 6.5 V
VOUT DC Output Voltage −0.5 6.5 V
IIK DC Input Diode Current VIN < 0 V − −50 mA
IOK DC Output Diode Current VOUT < 0 V − −50 mA
IOUT DC Output Source / Sink Current −±50 mA
ICC / IGND DC VCC / Ground Current −±100 mA
TSTG Storage Temperature Range −65 +150 °C
TJJunction Lead Temperature under Bias −+150 °C
TLJunction Lead Temperature (Soldering, 10 Seconds) −+260 °C
PDPower Dissipation in Still Air US8
MicroPak−8
−
−
500
539
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC Supply Voltage Operating 1.65 5.5 V
Supply Voltage Data Retention 1.5 5.5
VIN Input Voltage 0 5.5 V
VOUT Output Voltage Active State 0 VCC V
3−STATE 0 5.5 V
TAOperating Temperature −40 +85 °C
tr, tfInput Rise and Fall Time VCC @ 1.8 V ±0.15 V, 2.5 V ±0.2 V 0 20 ns/V
VCC @ 3.3 V ±0.3 V 0 10
VCC @ 5.0 V ±0.5 V 0 5
qJA Thermal Resistance US8
MicroPak−8
−
−
250
232
°C/W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Unused inputs must be held HIGH or LOW. They may not float.
NC7WZ125
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4
DC ELECTICAL CHARACTERISTICS
Symbol Parameter Conditions VCC (V)
TA = +25°C TA = −40 to +85°C
Unit
Min Typ Max Min Max
VIH HIGH Level Input
Voltage
1.65 to 1.95 0.65 VCC − − 0.65 VCC −V
2.3 to 5.5 0.7 VCC − − 0.7 VCC −
VIL LOW Level Input
Voltage
1.65 to 1.95 − − 0.35 VCC −0.35 VCC V
2.3 to 5.5 − − 0.3 VCC −0.3 VCC
VOH HIGH Level Output
Voltage
VIN = VIH or
VIL
IOH = −100 mA 1.65 1.55 1.65 −1.55 −V
2.3 2.2 2.3 −2.2 −
3.0 2.9 3.0 −2.9 −
4.5 4.4 4.5 −4.4 −
VIN = VIH or
VIL
IOH = −4 mA 1.65 1.29 1.52 −1.29 −
IOH = −8 mA 2.3 1.9 2.15 −1.9 −
IOH = −16 mA 3.0 2.4 2.80 −2.4 −
IOH = −24 mA 3.0 2.3 2.68 −2.3 −
IOH = −32 mA 4.5 3.8 4.20 −3.8 −
VOL LOW Level Output
Voltage
VIN = VIH or
VIL
IOL = 100 mA 1.65 −0.0 0.10 −0.10 V
2.3 −0.0 0.10 −0.10
3.0 −0.0 0.10 −0.10
4.5 −0.0 0.10 −0.10
IOL = 4 mA 1.65 −0.08 0.24 −0.24
IOL = 8 mA 2.3 −0.10 0.3 −0.3
IOL = 16 mA 3.0 −0.15 0.4 −0.4
IOL = 24 mA 3.0 −0.22 0.55 −0.55
IOL = 32 mA 4.5 −0.22 0.55 −0.55
IIN Input Leakage
Current
VIN = 5.5 V, GND 1.65 to 5.5 − − ±0.1 −±1mA
IOZ 3−STATE Output
Leakage
VIN = VIH or VIL
0 ≤ VOUT ≤ 5.5 V
1.65 to 5.5 − − ±0.5 −±5mA
IOFF Power Off Leakage
Current
VIN or VOUT = 5.5 V 0.0 − − 1−10 mA
ICC Quiescent Supply
Current
VIN = 5.5 V, GND 1.65 to 5.5 − − 1−10 mA
NOISE CHARACTERISTICS
Symbol Parameter Conditions VCC (V)
TA = +25°C
Unit
Typ Max
VOLP (Note 3) Quiet Output Maximum Dynamic VOL CL = 50 pF 5.0 −1.0 V
VOLV (Note 3) Quiet Output Minimum Dynamic VOL CL = 50 pF 5.0 −1.0 V
VOHV (Note 3) Quiet Output Minimum Dynamic VOH CL = 50 pF 5.0 −4.0 V
VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage CL = 50 pF 5.0 −3.5 V
VILD (Note 3) Maximum LOW Level Dynamic Input Voltage CL = 50 pF 5.0 −1.5 V
3. Parameter guaranteed by design.
NC7WZ125
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5
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions VCC (V)
TA = +25°C TA = −40 to +85°C
Unit
Min Typ Max Min Max
tPLH, tPHL Propagation Delay
AN to YN
(Figure 4, 6)
CL = 15 pF
RD = 1 MW
S1 = Open
1.8 ±0.15 − − 12.0 −13.0 ns
2.5 ±0.2 − − 7.5 −8.0
3.3 ±0.3 − − 5.2 −5.5
5.0 ±0.5 − − 4.5 −4.8
CL = 50 pF,
RD = 500 W
S1 = Open
3.3 ±0.3 − − 5.7 −6.0
5.0 ±0.5 − − 5.0 −5.3
tOSLH, tOSHL Output to Output Skew
(Note 4) (Figure 4, 6)
CL = 50 pF,
RD = 500 W
S1 = Open
3.3 ±0.3 − − 1.0 −1.0 ns
5.0 ±0.5 − − 0.8 −0.8
tPZL, tPZH Output Enable Time
(Figure 4, 6)
CL = 50 pF
RD,RU = 500 W
S1 = GND for tPZH
S1 = VI for tPZL
VI = 2 x VCC
1.8 ±0.15 − − 14.0 −15.0 ns
2.5 ±0.2 − − 8.5 −9.0
3.3 ±0.3 − − 6.2 −6.5
5.5 ±0.5 − − 5.5 −5.8
tPLZ, tPHZ Output Disable Time
(Figure 4, 6)
CL = 50 pF
RD,RU = 500 W
S1 = GND for tPZH
S1 = VI for tPZL
VI = 2 x VCC
1.8 ±0.15 − − 12.0 −13.0 ns
2.5 ±0.2 − − 8.0 −8.5
3.3 ±0.3 − − 5.7 −6.0
5.0 ±0.5 − − 4.7 −5.0
CIN Input Capacitance 0−2.5 − − − pF
COUT Output Capacitance 5.0 −4− − − pF
CPD Power Dissipation
Capacitance (Figure 5)
(Note 5) 3.3 −10 −− − pF
5.0 −12 −− −
4. Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin|.
5. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at
no output loading and operating at 50% duty cycle. (see Figure 5) CPD is related to ICCD dynamic operating current by the expression:
ICCD = (CPD) (VCC) (fIN) + (ICCstatic).
NC7WZ125
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6
AC Loading and Waveforms
Figure 4. AC Test Circuit
Figure 5. ICCD Test Circuit Figure 6. AC Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tW = 500 ns
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%.
A
INPUT
VCC
VCC
CLRD
INPUT OUTPUT
OE INPUT RU GND
OPEN
VIN
OUTPUT
OE
ORDERING INFORMATION
Order Number Top Mark Package Shipping
†
NC7WZ125K8X WZ25 8−Lead US8, JEDEC MO−187, Variation CA
3.1 mm Wide
3000 / Tape & Reel
NC7WZ125L8X P3 8−Lead MicroPak, 1.6 mm Wide
(Pb−Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
6. Pb−Free package per JEDEC J−STD−020B.
MicroPak is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
UQFN8 1.6X1.6, 0.5P
CASE 523AY
ISSUE O
DATE 31 AUG 2016
C
SEATING
PLANE
0.05 C
SIDE VIEW
0.05 C
AB
2X
1.60
1.60
0.05 C
TOP VIEW
PIN#1 IDENT
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO−255
VARIATION UAAD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
0.025±0.025
4
123
567
80.30±0.05
(0.15)
(0.20)
0.30±0.05
0.05 C
0.50±0.05
BOTTOM VIEW
1.60±0.05
1.60±0.05
0.50
0.20±0.05 (8X)
1.00±0.05
0.30±0.05 (7X)
0.10 C A B
0.05 C
(0.20)3X
(0.09)
DETAIL A
DETAIL A
SCALE : 2X
(0.10)
RECOMMENDED
LAND PATTERN
1.60
0.45
(2X)
0.40
(6X)
1.61
0.25
(8X)
0.50
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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UQFN8 1.6X1.6, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
US8
CASE 846AN
ISSUE O
DATE 31 DEC 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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