K6T4008V1B, K6T4008U1B Family CMOS SRAM Document Title 512Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft December 17, 1996 Preliminary 1.0 Finalize - Change datasheet format - Erase low power part from product - Erase 70ns part from KM68U4000B family - Power dissipation Improved 0.7 to 1.0W - VIL(MAX) improved 0.4 to 0.6V. - ICC2 decreased 50 to 45mA. Januarary 14, 1998 Final 2.0 Revised - ICC1 decreased 20 to 25mA February 12, 1998 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM 512Kx8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology: TFT * Organization: 512Kx8 * Power Supply Voltage K6T4008V1B Family: 3.0~3.6V K6T4008U1B Family: 2.7~3.3V * Low Data Retention Voltage: 2V(Min) * Three state output and TTL Compatible * Package Type: 32-SOP, 32-TSOP2-400F/R The K6T4008V1B and K6T4008U1B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature range and have various package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature K6T4008V1B-B Vcc Range Speed 3.0~3.6V 701)/851)/100ns K6T4008U1B-B 2.7~3.3V 851)/100ns K6T4008V1B-F 3.0~3.6V Commercial(0~70C) Industrial(-40~85C) K6T4008U1B-F 851)/100ns Standby (ISB1, Max) PKG Type Operating (ICC2, Max) 15A 45mA 32-SOP 32-TSOP2-F/R 20A 2.7~3.3V 1. The paramerter is measured with 30pF test load. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Clk gen. A18 1 32 VCC VCC 32 1 A18 A16 2 31 A15 A15 31 2 A16 A14 3 30 A17 A17 30 3 A14 A12 4 29 WE WE 29 4 A12 A7 5 28 A13 A13 28 5 A7 A6 6 27 A8 A8 27 6 A6 A7 A5 7 26 A9 A9 26 7 A5 A6 A4 8 25 A11 A11 25 8 A4 A3 9 24 OE OE 24 9 A3 A2 10 23 A10 A10 23 10 A2 A1 11 22 CS CS 22 11 A1 A0 12 21 I/O8 I/O8 21 12 A0 I/O1 13 20 I/O7 I/O7 20 13 I/O1 Precharge circuit. A18 A16 A14 32-SOP 32-TSOP2 Forward 32-TSOP2 Reverse 14 19 I/O6 I/O6 19 14 15 18 I/O5 I/O5 18 15 I/O3 VSS 16 17 I/O4 I/O4 17 16 VSS Name A1 A0 Data cont I/O 8 I/O2 I/O Circuit Column select Data cont A9 A8 A13A17A15 A10 A11 A3 A2 Function CS Chip Select Input OE Output Enable Input Vcc Power CS WE Write Enable Input Vss Ground WE A0~A18 Address Inputs Memory array 1024 rows 512x8 columns A5 I/O 1 I/O3 Function Row select A4 I/O2 Name A12 I/O1~I/O8 Data Inputs/Outputs Control logic OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM PRODUCT LIST Commercial Temp Products(0~70C) Part Name Industrial Temp Products(-40~85C) Function Part Name K6T4008V1B-GB70 K6T4008V1B-GB80 K6T4008V1B-GB10 32-SOP, 70ns, 3.3V,LL 32-SOP, 85ns, 3.3V,LL 32-SOP, 100ns, 3.3V,LL K6T4008V1B-VB70 K6T4008V1B-VB85 K6T4008V1B-VB10 K6T4008V1B-MB70 K6T4008V1B-MB85 K6T4008V1B-MB10 32-TSOP2-F, 70ns, 3.3V,LL 32-TSOP2-F, 85ns, 3.3V,LL 32-TSOP2-F, 100ns, 3.3V,LL 32-TSOP2-R, 70ns, 3.3V,LL 32-TSOP2-R, 85ns, 3.3V,LL 32-TSOP2-R, 100ns, 3.3V,LL K6T4008U1B-GB85 K6T4008U1B-GB10 32-SOP, 85ns, 3.0V,LL 32-SOP, 100ns, 3.0V,LL K6T4008U1B-VB85 K6T4008U1B-VB10 K6T4008U1B-MB85 K6T4008U1B-MB10 32-TSOP2-F, 85ns, 3.0V,LL 32-TSOP2-F, 100ns, 3.0V,LL 32-TSOP2-R, 85ns, 3.0V,LL 32-TSOP2-R, 100ns, 3.0V,LL Function K6T4008V1B-GF85 K6T4008V1B-GF10 32-SOP, 85ns, 3.3V,LL 32-SOP, 100ns, 3.3V,LL K6T4008V1B-VF85 K6T4008V1B-VF10 K6T4008V1B-MF85 K6T4008V1B-MF10 32-TSOP2-F, 85ns, 3.3V,LL 32-TSOP2-F, 100ns, 3.3V,LL 32-TSOP2-R, 85ns, 3.3V,LL 32-TSOP2-R, 100ns, 3.3V,LL K6T4008U1B-GF85 K6T4008U1B-GF10 32-SOP, 85ns, 3.0V,LL 32-SOP, 100ns, 3.0V,LL K6T4008U1B-VF85 K6T4008U1B-VF10 K6T4008U1B-MF85 K6T4008U1B-MF10 32-TSOP2-F, 85ns, 3.0V,LL 32-TSOP2-F, 100ns, 3.0V,LL 32-TSOP2-R, 85ns, 3.0V,LL 32-TSOP2-R, 100ns, 3.0V,LL Note : LL means Low Low standby current FUNCTIONAL DESCRIPTION CS OE WE I/O Mode Power H X1) X1) High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L X1) L Din Write Active 1. X means dont care (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT VCC -0.5 to VCC+0.5 V - -0.3 to 4.6 V - PD 1 W - TSTG -65 to 150 C - TA TSOLDER 0 to 70 C K6T4008V1B-L, K6T4008U1B-L -40 to 85 C K6T4008V1B-P, K6T4008U1B-P 260C, 10sec (Lead Only) - - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6T4008V1B Family K6T4008U1B Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 V Input high voltage VIH K6T4008V1B, K6T4008U1B Family 2.2 - Vcc+0.32) V Input low voltage VIL K6T4008V1B, K6T4008U1B Family - 0.6 V -0.3 3) Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : VCC +3.0V in case of pulse width 30ns 3. Undershoot : -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol ILI Min Typ Max Unit VIN=Vss to Vcc -1 - 1 A Test Conditions Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 A Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 10 mA ICC1 Cycle time=1s, 100% duty, IIO=0mA, CS0.2V VIN0.2V or V INVcc-0.2V Read - - 10 Write - - 25 - - 45 mA Average operating current mA ICC2 Cycle time=Min, 100% duty, I IO=0mA, CS=VIL, VIN=VIH or VIL Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or V IH - - 0.5 mA Standby ISB1 CSVcc-0.2V, Other inputs=0~Vcc - - 1) A 15 1. Industrial product = 20A 4 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. K6T4008V1B-7, K6T4008V1B-8 Family and K6T4008U1B-8 Family AC CHARACTERISTICS (K6T4008V1B Family: Vcc=3.0~3.6V, K6T4008U1B Family: Vcc=2.7~3.3V Commercial product: TA=0 to 70C, Industrial product: TA=-40 to 85C) Speed Bins Parameter List Read Symbol 85ns Units 100ns Min Max Min Max Min Max Read cycle time tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns Output enable to low-Z output Write 70ns Output hold from address change tOH 10 - 10 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 55 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CSVcc-0.2V Data retention current IDR Vcc=3.0V, CSVcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 3.6 V - 0.5 0 - - 5 - - 15 1) A ms 1. Industrial product = 20A 5 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS tHZ tOE OE Data out High-Z tOLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 2.2V VDR CS GND CSVCC - 0.2V 7 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM Units : millimeter(inch) PACKAGE DIMENSIONS 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8 #17 14.120.30 0.5560.012 #1 #16 20.87 MAX 0.822 20.470.20 0.8060.008 11.430.20 0.4500.008 2.740.20 0.1080.008 3.00 0.118 MAX 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.800.20 0.0310.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 +0.004 0.016 -0.002 0.41 1.27 0.050 0.05 MIN 0.002 8 Revision 2.0 February 1998 K6T4008V1B, K6T4008U1B Family CMOS SRAM PACKAGE DIMENSIONS Units : millimeter(inch) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0.25 ( 0.010 ) #32 0~8 #17 11.760.20 0.4630.008 #1 10.16 0.400 0.45~0.75 0.018 ~ 0.030 #16 21.35 0.841 MAX 1.000.10 0.0390.004 1.20 0.047 MAX 20.950.10 0.8250.004 ( 0.15 +0.10 -0.05 0.006 +0.004 -0.002 0.50 ) 0.020 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.400.10 0.0160.004 0.05 MIN 0.002 1.27 0.050 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8 0.25 ( ) 0.010 #1 #16 11.760.20 0.4630.008 #32 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 #17 21.35 0.841 MAX 1.000.10 0.0390.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 ( 0.50 ) 0.020 1.20 0.047 MAX 20.950.10 0.8250.004 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.400.10 0.0160.004 1.27 0.050 0.05 MIN 0.002 9 Revision 2.0 February 1998