© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 7 1Publication Order Number:
MC100LVEL16/D
MC100LVEL16
3.3V ECL Differential
Receiver
Description
The MC100LVEL16 is a differential receiver. The device is
functionally equivalent to the EL16 device, operating from a 3.3 V
supply. The LVEL16 exhibits a wider VIHCMR range than its EL16
counterpart. With output transition times and propagation delays
comparable to the EL16 the LVEL16 is ideally suited for interfacing
with high frequency sources at 3.3 V supplies.
Under open input conditions, the Q input will be pulled down to VEE
and the Q input will be biased to VCC/2. This condition will force the
Q output low.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
•300 ps Propagation Delay
•High Bandwidth Output Transitions
•The 100 Series Contains Temperature Compensation
•PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
•Internal Input Pulldown Resistors on D, Pullup and Pulldown
Resistors on D
•Q Output will Default LOW with Inputs Open or at VEE
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
KV16
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
KVL16
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G= Pb−Free Package
4BMG
G
1
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Figure 1. Logic Diagram and Pinout Assignment
D, D ECL Data Inputs
Q, Q ECL Data Outputs
VBB Reference Voltage Output
VCC Positive Supply
VEE Negative Supply
NC No Connect
Table 1. PIN DESCRIPTION
PIN FUNCTION
1
2
3
45
6
7
8
Q
VEE
VCC
D
Q
D
VBB
NC
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 kW
Internal Input Pullup Resistor 75 kW
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 KV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time out of Drypack,
Pb−Free Packages (Note 1) SOIC−8
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 79
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Refer to Application Note AND8003/D for additional information.
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Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V
VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage VEE = 0 V
VCC = 0 V VI VCC
VI VEE
6 to 0
−6 to 0 V
V
Iout Output Current Continuous
Surge 50
100 mA
mA
IBB VBB Sink/Source ± 0.5 mA
TAOperating Temperature Range −40 to +85 °C
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM SO−8
SO−8 190
130
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 ± 5% °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM TSSOP−8
TSSOP−8 185
140
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W
qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm DFN8
DFN8 129
84 °C/W
°C/W
Tsol Wave Solder Pb
Pb−Free <2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C265
265 °C
qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
MC100LVEL16
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Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 3)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 17 23 17 23 18 24 mA
VOH Output HIGH Voltage (Note 4) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
VOL Output LOW Voltage (Note 4) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV
VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV
VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
Vpp < 500 mV
Vpp y 500 mV 1.2
1.5
2.9
2.9
1.1
1.4
2.9
2.9
1.1
1.4
2.9
2.9
V
V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current D
D0.5
−600 0.5
−600 0.5
−600 mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2 V.
5. VIHCMR m in varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR r ange i s r eferenced to t he most p ositive s ide o f t he differential i nput s ignal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 6)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
IEE Power Supply Current 17 23 17 23 18 24 mA
VOH Output HIGH Voltage (Note 7) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
VOL Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV
VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
Vpp < 500 mV
Vpp y 500 mV −2.1
−1.8 −0.4
−0.4
−2.2
−1.9
−0.4
−0.4
−2.2
−1.9
−0.4
−0.4
V
V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current D
D0.5
−600 0.5
−600 0.5
−600 mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
7. Outputs are terminated through a 50 W resistor to VCC − 2 V.
8. VIHCMR m in varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR r ange i s r eferenced to t he most p ositive s ide o f t he differential i nput s ignal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V.
MC100LVEL16
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Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= −3.3 V (Note 9)
Symbol Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Toggle Frequency 1.75 1.75 1.75 GHz
tPLH
tPHL Propagation Delay to Output Differential
Single−Ended 150
100 275
275 400
450 225
175 300
300 375
425 240
190 315
315 390
440
ps
tSKEW Duty Cycle Skew (Differential)(Note 10) 5 30 5 20 5 20 ps
tJITTER Random Clock Jitter (RMS) 0.7 0.7 0.7 ps
VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV
tr
tfOutput Rise/Fall Times Q
(20% − 80%) 120 220 320 120 220 320 120 220 320 ps
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. VEE can vary ±0.3 V.
10.Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
11. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC − 2.0 V
MC100LVEL16
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ORDERING INFORMATION
Device Package Shipping†
MC100LVEL16DG SO−8
(Pb−Free) 98 Units / Rail
MC100LVEL16DR2G SO−8
(Pb−Free) 2500 Tape & Reel
MC100LVEL16DTG TSSOP−8
(Pb−Free) 100 Units / Rail
MC100LVEL16DTR2G TSSOP−8
(Pb−Free) 2500 Tape & Reel
MC100LVEL16MNR4G DFN8
(Pb−Free) 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
MC100LVEL16
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PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC100LVEL16
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PACKAGE DIMENSIONS
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1 14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
TSSOP−8
DT SUFFIX
CASE 948R−02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
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PACKAGE DIMENSIONS
DFN8 2x2, 0.5P
CASE 506AA
ISSUE E
ÇÇ
ÇÇ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
NOTE 4 A1 SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
ABB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K
L0.25 0.35
14
85
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30 PITCH
8X
1
PACKAGE
OUTLINE
RECOMMENDED
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
ÉÉ
ÉÉ
ÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTION
DETAIL B
DET AIL A
L1 −−− 0.10
0.30 REF
0.90
1.30
P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC100LVEL16/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loc
al
Sales Representative
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and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
