SN54AS823A . . . JT PACKAGE
SN74AS823A . . . DW OR NT PACKAGE
(TOP VIEW)
SN54AS823A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
NC – No internal connection
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3Q
4Q
5Q
NC
6Q
7Q
8Q
3D
4D
5D
NC
6D
7D
8D
426
14 15 16 17 18
9D
CLR
GND
NC
CLK
CLKEN
9Q
2D
1D
OE
NC
1Q
2Q
VCC
SN74AS824A . . . DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Functionally Equivalent to AMD’s AM29823
and AM29824
•Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
•Outputs Have Undershoot-Protection
Circuitry
•Power-Up High-Impedance State
•Buffered Control Inputs to Reduce
dc Loading Effects
•Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. These devices
are particularly suitable for implementing wider
buffer registers, I/O ports, bidirectional bus
drivers, parity bus interfacing, and working
registers.
With the clock-enable (CLKEN) input low , the nine
D-type edge-triggered flip-flops enter data on the
low-to-high transitions of the clock (CLK) input.
Taking CLKEN high disables the clock buffer,
latching the outputs. The SN54AS823A and
SN74AS823A have noninverting data (D) inputs
and the SN74AS824A has inverting (D) inputs.
Taking the clear (CLR) input low causes the nine
Q outputs to go low independently of the clock.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic level) or the high-
impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operation of the
flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
The SN54AS823A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AS823A and SN74AS824A
are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN54AS823A, SN74AS823A
(each flip-flop)
INPUTS OUTPUT
OE CLR CLKEN CLK D Q
L L X X X L
LHL↑HH
LHL↑LL
LHHXX Q
0
HXXXX Z
SN74AS824A
(each flip-flop)
INPUTS OUTPUT
OE CLR CLKEN CLK D Q
L L X X X L
LHL↑HL
LHL↑LH
LHHXX Q
0
HXXXX Z
logic symbols†
EN
1
7
6D 8
7D 9
8D 10
9D
2D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D 4
3D 5
4D 6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
13
CLK 1C2
R
11
CLR
G1
14
CLKEN
EN
1
7
8
9
10
2D
2
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
4
5
6
2Q
22
3Q
21
4Q
20
5Q
19
OE
13
CLK 1C2
R
11
CLR
G1
14
CLKEN
1D
2D
3D
4D
5D
6D
7D
8D
9D
SN54AS823A, SN74AS823A SN74AS824A
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
To Eight Other Channels
23
2
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE
CLR
SN54AS823A, SN74AS823A
To Eight Other Channels
23
2
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE
CLR
SN74AS824A
Pin numbers shown are for the DW, JT, and NT packages.
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: SN54AS823A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS823A, SN74AS824A 0°C to 70°C. . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
SN54AS823A SN74AS823A
SN74AS824A UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –24 –24 mA
IOL Low-level output current 32 48 mA
t
*
Pulse duration
CLR low 7.5 6.5
ns
t
w
*
P
u
lse
d
u
ration
CLK high or low 9.5 8
ns
↑
CLR high 8 8
tsu*Setup time before CLK
↑
Data 7 6 ns
CLKEN high or low 8.5 7.5
th*Hold time after CLK↑CLKEN low 0 0 ns
TAOperating free-air temperature –55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS SN54AS823A SN74AS823A
SN74AS824A UNIT
MIN TYP†MAX MIN TYP†MAX
VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2
VOH
VCC =45V
IOH = –15 mA 2.4 3.2 2.4 3.2 V
V
CC =
4
.
5
V
IOH = –24 mA 2 2
VOL
VCC =45V
IOL = 32 mA 0.3 0.5
V
V
OL
V
CC =
4
.
5
V
IOL = 48 mA 0.35 0.5
V
IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA
IOZL VCC = 5.5 V, VI = 0.4 V –50 –50 µA
IIVCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V –0.5 –0.5 mA
IO‡VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
SN54AS823A
Outputs high 49 80 49 80
SN54AS823A,
SN74AS823A
VCC = 5.5 V Outputs low 61 100 61 100
ICC
SN74AS823A
Outputs disabled 64 103 64 103
mA
I
CC Outputs high 49 80 49 80
mA
SN74AS824A VCC = 5.5 V Outputs low 61 100 61 100
Outputs disabled 64 103 64 103
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX§UNIT
(INPUT)
(OUTPUT)
SN54AS823A SN74AS823A
SN74AS824A
MIN MAX MIN MAX
tPLH
CLK
An Q
3.5 9 3.5 7.5
ns
tPHL
CLK
A
ny
Q
3.5 14 3.5 13
ns
tPHL CLR Any Q 3.5 16.5 3.5 15.5 ns
tPZH
OE
An Q
412 4 11
ns
tPZL
OE
A
ny
Q
4 13 4 12
ns
tPHZ
OE
Any Q
1 10 1 8
ns
tPLZ
OE
A
ny
Q
1 10 1.5 8
ns
§For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54AS823A, SN74AS823A, SN74AS824A
9-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS231A – JUNE 1984 – REVISED AUGUST 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
tPHZ
tPLZ
tPHL tPLH
0.3 V
tPZL
tPZH
tPLH tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V 3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test Test
Point
CL
(see Note A) RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-89525013A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89525013A
SNJ54AS
823AFK
5962-8952501KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8952501KA
SNJ54AS823AW
5962-8952501LA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8952501LA
SNJ54AS823AJT
SN74AS823ADW NRND SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS823A
SN74AS823ADWE4 NRND SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS823A
SN74AS823ADWG4 NRND SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AS823A
SN74AS823ANT NRND PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS823ANT
SN74AS823ANTE4 NRND PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74AS823ANT
SN74AS824ADW OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70
SN74AS824ADWR OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70
SN74AS824ANT OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70
SNJ54AS823AFK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
89525013A
SNJ54AS
823AFK
SNJ54AS823AJT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8952501LA
SNJ54AS823AJT
SNJ54AS823AW ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8952501KA
SNJ54AS823AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AS823A, SN74AS823A :
•Catalog: SN74AS823A
•Military: SN54AS823A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
4040110/C 08/96
B
0.200 (5,08) MAX
0.320 (8,13)
0.290 (7,37)
0.130 (3,30) MIN
0.008 (0,20)
0.014 (0,36)
Seating Plane
13
12
0.030 (0,76)
0.070 (1,78)
0.015 (0,38) MIN
A
24
1
0.100 (2,54) MAX
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0°–15°
1.440
(37,08)
1.460
0.285
(7,39)
0.291
(36,58)
(7,24)
28
PINS **
1.280
1.240
0.300
0.245
(7,62)
DIM
B MAX
A MAX
A MIN
B MIN (6,22)
24
(32,51)
(31,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
MECHANICAL DATA
MCFP007 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W (R-GDFP-F24) CERAMIC DUAL FLATPACK
4040180-5/B 03/95
1.115 (28,32)
0.090 (2,29)
0.375 (9,53)
0.019 (0,48)
0.030 (0,76)
0.045 (1,14)
0.006 (0,15)
0.045 (1,14)
0.015 (0,38)
0.015 (0,38)
0.026 (0,66)
0.004 (0,10)
0.340 (8,64)
0.840 (21,34)
124
0.360 (9,14)
0.240 (6,10)
1312
Base and Seating Plane
30° TYP
0.360 (9,14)
0.240 (6,10)
0.395 (10,03)
0.360 (9,14)
0.640 (16,26)
0.490 (12,45)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
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