@ PLESSEY PIC1650A ADVANCE INFORMATION Advance information is issued to advise Customers of new additions to the Plessey Semiconductors range which, nevertheless, still have pre-production status. Details given may, therefore, change without notice although we would expect this performance data to be representative of full production status product in most cases. Please contact your local Plessey Semiconductors Sales Oftice for PIC1650A 8 BIT MICROCOMPUTER details of current status. FEATURES User Programmable Intelligent Controller for Stand-Alone Applications 32 8-Bit RAM Registers 512 x 12-Bit Program ROM Arithmetic Logic Unit Real Time Clock Counter Self-contained Oscillator Access to RAM Registers Inherent in Instruction Wide Power Supply Operating Range (4.5V to 7.0V) Available in Two Temperature Ranges: 0 to 70C and -40 to 85C 4 Sets of 8 User Defined TTL-Compatible Input/ Output Lines M2 Level Stack The PIC1650A microcomputer is an MOS/LSI device containing RAM, I/O, and a central processing unit as well as customer-defined ROM on a single chip. This combination produces a low cost solution for applications which require sensing individual inputs and controlling individual outputs. Keyboard scanning, display driving, and other system control functions can be done at the same time due to the power of the 8-bit CPU. The internal ROM contains a customer-defined program using the PICs powerful instruction set to specify the overall functional characteristics of the device. The 8-bit input/output registers provide latched lines for interfacing to a limitless variety of applications. The PIC can be used to scan keyboards, drive displays, control electronic games and Vss (fi ol 40q) Vx + ~ Rao{}2 331 von =~ RAIfys sel] atc ~~ Raz (4 wD mcLA Test (]s 36) osc -- ras 3s[] ciK OUT + naa (7 34f} ADT =~ pas (Je 33f] RDB =~ 60 crgsoa | POF a> RAT [10 31] AD@ + peo (}1 sof] R03 ++ per 291) R02 == =~ AB (3 zef} ADy AB3 (14 27) RDB = Apa (Jis 26finc? =~ pas []6 25[] RC + - pps []17 2a RCS ~ na7 (Je 23 rca + - aco G9 220} Rc3 Aci (20 2p) rez + pPao Fig.1 Pin connections - top view provide enhanced capabilities to vending machines, traffic lights, radios, television, consumer appliances, industrial timing and contro! applications. The 12-bit instruction word format provides a powerful yet easy to use instruction repertoire emphasizing single bit manipulation as well as logical and arithmetic operations using bytes. FILE SELECT REGISTER W REGISTER REGISTER RAO-7 u GENERAL FILES (F11-F37) y RBO-? LOGIC K UNIT 2 LEVEL INSTRUCTION STACK DECODE RCO-7 STATUS REG (F3) RTCC REG (F1) & CONTROL PROG CNTR (F2) RDO-7 g [vo REG oF10)| v0 REGC(F7) V/OREG B(F6) | VO REG A(F5) PROGRAM ROM $12 x12 ATCC MCLR Fig. 2 PIC1650A block diagram 269PIC1650A The PIC 1650A is fabricated with N-Channel lon Implant technol- ogy resulting in a high performance product with proven reliabitity and production history. Only a single wide range power supply is required for operation, and an on-chip oscillator provides the operating clock with only an external RC network (or buffered crystal oscillator signal, for greater accuracy) to establish the frequency. Inputs and outputs are TTL-compatible. Extensive hardware and software support is available to aid the user in developing an application program and to verify perfor- mance before committing to mask tooling. Programs can be assembled into machine language using PICAL, eliminating the burden of coding with ones and zeros. PICAL is available ina Fortran I version that can be run on many popular computer systems. Once the application program is developed several options are available to insure proper performance. The PICs operation can be verified in any hardware application by using the PIC 1664B. The PIC 1664B is a ROM-iess PIC microcomputer with additional pins to connect external PROM or RAM and to accept HALT commands. The PFD 1000 Field Demo System is available containing a PIC 1664B with sockets for erasable CMOS PROMs. Finally, the PICES (PIC In-Circuit Emulation System) provides the user with emulation and debugging capability in either a stand-alone mode or operation as a peripheral to a larger computer system. Easy program debugging and changing is. facilitated because the user's program is stored in RAM. With these development tools, the user can quickly and confidently order the masking of the PICs ROM and bring his application into the market. A PIC Series Microcomputer Data Manual is available which gives additional detailed data on PIC based system design. PIN FUNCTIONS ARCHITECTURAL DESCRIPTION The firmware architecture of the PIC series microcomputer is based on a register file concept with simple yet powerful com- mands designed to emphasize bit, byte, and register transfer operations. The instruction set also supports computing func- tions as well as these control and interface functions. Internally, the P!C is composed of three functional elements connected together by a single bidirectional bus: the Register File composed of 32 addressable 8-bit registers, an Arithmetic Logic Unit, and a user-defined Program ROM composed of 512 words each 12 bits in width. The Register File is divided into two func- tional groups: operational registers and general registers. The operational registers include, among others, the Real Time Clock Counter Register, the Program Counter (PC), the Status Register, and the I/O Registers. The general purpose registers are used for data and control information under command of the instructions. The Arithmetic Logic Unit contains one temporary working regis- ter or accumulator (W Register) and gating to perform Boolean functions between data held in the working register and any file register. The Program ROM contains the operational program forthe rest of the logic within the controller. Sequencing of microinstructions is controlled via the Program Counter (PC) which automatically increments to execute in-line programs. Program control opera- tions can be performed by Bit Test and Skip instructions, Jump instructions, Call instructions, or by loading computed addresses into the PC. In addition, an on-chip two-level stack is employed to provide easy to use subroutine nesting. Activating the MCLRinput on power up initializes the ROM program to address 777s. Function OSC (input) RTCC (input) RAO-7, RBO-7, RCO-7, RDO-7 (input/output) MCLA (input) CLK OUT (output) TEST Voo Vix Vss Oscillator input. This signal can be driven by an external oscillator if a precise frequency of operation is required or an externai RC network can be used to set the frequency of operation of the internal clock generator. This is a Schmitt trigger input. Real Time Clock Counter. Used by the microprogram to keep track of elapsed time between events. The RTCC register increments on falling edges applied to this pin. This register can be loaded and read by the program. This is a Schmitt trigger input. User programmable input/output lines. These lines can be inputs and/or outputs and are under direct controi of the program. Master Clear. Used to initialize the internal ROM program to address 777, and latch all I/O register high. Should be held low at least 1ms past the time when the power supply is valid. This is a Schmitt trigger input. A signal derived from the internal oscillator. Used by external devices to synchronize themselves to PIC timing. Used for testing purposes only. Must be grounded for normal operation. Primary power supply. Output Buffer power. Used to enhance output current sinking capability. Ground 270PIC1650A REGISTER FILE ARRANGEMENT (Geral) Function Fo Not a physically implemented register. FO calls for the contents of the File Select Register (low order 5 bits) to be used to select a file register. FO is thus useful as an indirect address pointer. For example, W+FOW will add the contents of the file register pointed to by the FSR (F4) to W and place the result in W. F1 Real Time Clock Counter Register. This register can be loaded and read by the microprogram. The RTCC register keeps counting up after zero is reached. The counter increments on the falling edge of the input TCC. F2 Program Counter (PC).The PC is automatically incremented during each instruction cycle, and can be written into under program contro} (MOVWF F2).The PC is nine bits wide, but only its low order 8 bits can be read under program control. F3 Status Word Register. F3 can be altered under program control only via bit set, bit clear, or MOVWF F3 instruction. (7) (6) (5) 1] (3) (2) (1) (0) Car [+1 Tt Tt [Ti ftz to] | C (Carry): For AOO and SUB instructions, this bit is set if there is a carry out from the most significant bit of the resultant. For ROTATE instructions, this bit is loaded with either the high or low order bit of the source. DC (Digit Carry):For ADD and SUB instructions, this bit is set if there is a carry out from the 4th low order bit of the resultant. Z (Zero): Set if the result of an arithmetic operation is zero. Bits: 3-7 These bits are defined as logic ones. F4 File Select Register (FSR). Low order 5 bits only are used. The FSR is used in generating effective file register addresses under program control. When accessed as a directly addressed file, the upper 3 bits are read as ones. F5 VO Register A (A0-A7) F 1/O Register B (B0-87) F7 W/O Register C (CO-C7) F10 1/O Register D (D0-07) F11-F37| General Purpose Registers 271PIC1650A Basic Instruction Set Summary Each PIC instruction is a 12-bit word divided into an OP code which specifies the instruction type and one or more operands which further specify the operation of the instruction. The following PIC instruction summary lists byte-oriented, bit-ori- ented, and literal and control operations. For byte-oriented instructions, f represents a file register designator and d" represents a destination designator. The file register designator specifies which one of the 32 PIC file registers is to be utilized by the instruction. The destination designator specifies where the resuit of the operation performed by the instruction is to be placed. If d is zero, the result is placed in the BYTE-ORIENTED (11-6) FILE REGISTER OPERATIONS OP CODE PIC W register. If d is one, the result is returned to the file register specified in the instruction. For bit-oriented instructions, b represents a bit field designator which selects the number of the bit affected by the operation, while f" represents the number of the file in which the bit is located. For literal and control operations, k represents an eight or nine bit constant or literal vaiue. For an oscillator frequency of 1MHz the instruction execution time is 4 wsec, unless a conditional test is true or the program counter is changed as a result of an instruction. In these two cases, the instruction execution time is 8 usec. (5 (4-0) ) [a] (rues) | For d = 0, f-W (PICAL accepts d = 0 or d = W in the mnemonic) d=1,f-f (If dis omitted, assembler assigns d = 1.) Instructlon-Binary (Octal) Name Mnemonic, Operands Operation Status Affected| 000 000 000 000 (0000)} No Operation NOP - - None 000 000 1ff fff (0040)| Move W tof (Note 1) MOVWF f Wf None 000 001 000 000 (0100) Clear W CLRW _ 0-W Zz 000 O01 1ff fff (0140) Clear f CLRF f Of _ z 000 010 dff fff (0200) Subtract W from f SUBWF td f - Wed [f+W+1-d] C,DC,Z 000 011 dff fff (0300) Decrement f DECF fd f-1-d Zz 000 100 dff fff (0400) Inclusive OR W and f IORWEF fd WvVt-d Zz 000 101 dff fff (0500) AND W and ft ANDWF f,d Wef-d Zz 000 110 dff fff (0600) Exciusive OR W and f XORWF f.d Wft-d Zz 000 111 dff fff (0700) Add W and f ADDWF fd W-+f-d c,DC,2 001 000 dff fff {1000} Move f MOVF f,d f-d zZ 001 001 dff fff (1100) Compiement f COMF f,d f-d Zz 001 010 dff fff (1200) Increment f INCF f,d ft1-d z 001 O11 dff fff (1300) Decrement f, Skip if Zero DECFSZ f,d f - 1~d, skip if Zero None 001 100 dff fff (1400) Rotate Right f RRF f,d f(n)d(n-1),f(0)-C, C-d{7) c 001 101 dff fff (1600) Rotate Left f RLF f,d f(n)-d(n+1), f(7)-C, C-d(0) Cc 001 110 dff fff (1600) Swap halves f SWAPF f,d (0-3)sSf(4-7)d None 001 111 dff fff (1700) increment f, Skip if Zero INCFSZ f,d f+1d, skip if zero None BIT-ORIENTED (11-8) (7-5) (4-0) FILE REGISTER OPERATIONS OP CODE | b(BIT#)| 1 (FILE #) instruction-Binary (Octal) Name Mnemonic, Operands Operation Status Affected 010 Obb bff fff (2000) Bit Clear f BCF f,b 0-f(b) None 010 1bb bff fff (2400) Bit Set f BSF f,b 1f(b) None 011 Obb bff fff (3000) Bit Test f, Skip if Clear BTFSG f, b Bit Test f(b): skip if clear None 011 1bb bff fff (3400) Bit Test f, Skip if Set BTFSS f,b Bit Test f(b): skip is set None (11-8) (7-0) LITERAL AND CONTROL OPERATIONS OP CODE k (LITERAL) instruction-Binary (Octal) Name | Mnemonic, Operands Operation Status Affected 100 Okk kkk kkk (4000) Return and place Literal in W RETLW k k-W, Stack-PC None 100 tkk kkk kkk (4400) Call subroutine (Note 1) CALL k PC+1 Stack, k ~ PC None 101 kkk kkk kkk (5000) Go To address (k is 9 bits) GOTO k k~PC None 110 Okk kkk kkk (6000) Move Literal to W MOVLW k k--W None 110 1kk kkk kkk (6400) Inclusive OR Literal and W lORLW k kVW-W z 111 Okk kkk kkk (7000) AND Literal and W ANDLW k keW-W z 111 1kk kkk kkk (7400) Exclusive OR Literal and Ww XORLW k kKOW-W Zz NOTES: 1. The 9th bit of the program counter in the PIC is zero for a CALL and a MOVWF F2. Therefore, subroutines must be located in program memory locations 0-377. However, subroutines can be called from anywhere in the program memory since the Stack is 9 bits wide. 2. When an I/O register is modified as a function of itself, the value used will be that value present on the output pins. For example, an output pin which has been latched high but is driven jow by an external device, will be relatched in the low state. 272SUPPLEMENTAL INSTRUCTION SET SUMMARY The following supplemental instructions summarized below represent specific applications of the basic PIC instructions. For example, the CLEAR CARRY supplemental instruction is equiv- PIC1650A alent to the basic instruction BCF 3,0 (Bit Clear, File 3, Bit 0"). These instruction mnemonics are recognized by the PIC Cross Assembler (PICAL). Mnemonic, Equivalent Status Instruction-Binary (Octal) Name Op d Operation(s) Affected 010 000 000 011 (2003) Clear Carry CLRC BCF 3, 0 010 100 000 011 (2403) Set Carry SETC BSF 3,0 010 000 100 011 (2043) Clear Digit Carry CLRDC BCF 3, 1 010 100 100 011 (2443) Set Digit Carry SETDC BSF 3, 1 010 001 000 011 = (2103) Clear Zero CLRZ BCF 3, 2 010 101 000 011 (2503) Set Zero SETZ BSF 3, 2 011 100 000 011 (3403) Skip on Carry SKPC BTFSS 3, 0 011 000 000 O11 (3003) Skip on No Carry SKPNC BTFSC 3, 0 011 100 100 011 (3443) Skip on Digit Carry SKPDC BTFSS 3, 1 011 000 100 011 (3043) Skip on No Digit Carry SKPNDC BTFSC 3, 1 011 101 000 011 (3503) Skip on Zero SKPZ BTFSS 3, 2 - 011 001 000 011 (3103) Skip on No Zero SKPNZ BTFSC 3, 2 - 001 000 iff fff (1040) Test File TSTF f MOVF f, 1 001 O00 Off fff (1000) Move File to W MOVFW f MOVF f, 0 001 001 1ff fff (1140) Negate File NEGF f,d COMF f, 1 001 010 dff fff (1200) INCF f, d 011 000 000 011 (3003) Add Carry to Fite ADDCF f, d BTFSC 3,0 001 010 dff fff (1200) INCF f, d 011 000 000 011 (3003) Subtract Carry from File SUBCF fd BTFSC 3,0 ooo O11 aff ffrf (0300) DECF ft, d 011 000 100 011 (3043) Add Digit Carry to File ADDOCF f,d BTFSG 3,1 001 010 aff fff (1200) INCF f,.d 011 000 100 011 (3043) Subtract Digit Carry from File SUBDCF f.d BTFSC 3,1 000 011 dff fff (0300) DECF f,d z 101 kkk kkk kkk (5000) Branch Bk GOTO k _ 011 000 000 011 (3003) Branch on Carry BCk BTFSC 3,0 101 kkk kkk kkk (5000) GOTO k _ 011 100 000 011 (3403) Branch on No Carry BNC k BTFSS 3,0 101 kkk kkk kkk (5000) GOTO k - 011 100 100 011 (3043) Branch on Digit Carry BDC k BTFSC 3,1 101 kkk kkk kkk (5000) GOTOk - 011 001 000 011 (3443) Branch on No Digit Carry BNDC k BTFSS 3,1 101 kkk kkk kkk (5000) GOTO k _ 011 101 000 011 (3103) Branch on Zero BZk BTFSC 3,2 101 kkk kkk kkk (5000) GOTO k _ 011 101 000 011 (3503) Branch on No Zero BNZ k BTFSS 3.2 101 kkk kkk kkk (5000) GOTO k _ 273PIC1650A V/O Interfacing The equivalent circuit for an [/O port bit is shown below as it would interface with either the input of a TTL device (PIC is Outputting) or the output of an open collector TTL device (PIC is inputting). Each I/O port bit can be individually time multiplexed between input and output functions under software contro!. When outputting through a PIC I/O Port, the data is latched at the port and the pin can be connected directly to a TTL gate input. When inputting data through an I/O Port, the port latch must first be set to a high level under program control. This turns off Qa, allowing the TTL open collector device to drive the pad, pulled up by Q1, which can source a minimum of 100uA. Care, however, should be exercised when using open collector devices due to the potentially high TTL teakage current which can exist in the high logic state. Dn (INTERNAL D DATA BUS) a WRITE (INTERNAL Cog SIGNAL) j MCLR READ (INTERNAL SIGNAL) Pic INPUT/OUTPUT BIT | PO | Voc Yoo | | Qy | | . | [77 DEVICE INPUT C | | | | | | Qo | | | | | | | | | | | TTL DEVICE OUTPUT | LCOPEN-COLLECT OR) Fig.3 Typical interface - bidirectional 1/O line Programming Cautions The use of the bidirectional I/O ports are subject to certain rules of operation. These rules must be carefully followed in the instruction sequences written for I/O operation. Bidirectional 1/O Ports The bidirectional ports may be used for both input and output operations. For input operations these ports are non- latching. Any input must be present until read by an input instruction. The outputs are latched and remain unchanged until the output latch is rewritten. For use as an input port the output latch must be set in the high state. Thus the external device inputs to the PIC circuit by forcing the latched output line to the low state or keeping the latched output high. This Principle is the same whether operating on individual bits or the entire port. Some instructions operate internally as input followed by output operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation, and re-output the result. Caution must be used when using these instructions. As an example a BSF 274 operation on bit 5 of F7 (port RC) will cause all eight bits of F7 to be read into the CPU. Then the BSF operation takes place on bit 5 and F7 is re-output to the output latches. If another bit of F7 is used as an input (say bit 0) then bit 0 must be latched high. If during the BSF instruction on bit 5 an external device is forcing bit 0 to the low state then the input/output nature of the BSF instruction will leave bit 0 latched low after execution. In this state bit 0 cannot be used as an input until it is again latched high by the programmer. Refer to the examples below. Successive Operations on Bidirectional I/O Ports Care must be exercised if successive instructions operate on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU (MOVF, BIT SET, BIT CLEAR, and BIT TEST) is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. This wili happen if tea (See 1/O Timing Diagram) is greater than %4tcy (min). When in doubt, it is better to separate these instructions with a NOP or other instruction.PIC1650A OUTPUT INPUT What is thought to be happening: BSF 7.5 Read into CPU: 00001111 Set bit 5: OO101111 Write to F7: 00101111 (f no inputs were low during the instruction execution, there would be no problem. OUTPUT INPUT What could happen if an input were low BSF 75 Read into CPU 00001110 Set bit 5: Gota11tG Write to F7 00101110 in this case bit @ is now tatched low and is no longer useful as an input until set high again. Fig.4 Example 1 ELECTRICAL CHARACTERISTICS Maximum Ratings Temperature Under Bias Storage Temperature ...............4. Voltage on any pin with Respect to Vss . Power Dissipation .........0. 0... e cece eee ee eee rene ree ner e tenner bebe etn e ed 125C 5C to +150C 0.3V to +12.0V +. 1000mWw Fig.5 Example 2 *Exceeding these ratings could cause perma~ hent damage to the device. This is a stress tating only and functional operation of this device at these conditions is not implied operating ranges are specified in Standard Conditions. Exposure to absolute maximum r Di i i gs - Power Dissipated by a0 pine Note se LE coomwy ating conditions for extended periods may Standard Conditions (uniess otherwise stated): DC CHARACTERISTICS Operating Temperature Ts = 0C to +70C Characteristic Sym Min Typ Max Units Conditions Primary Supply Voitage Voo 45 _ 7.0 v Output Buffer Supply Voltage Vix 45 ~ 10.0 v (Note 2) Primary Supply Current Too _- 30 55 mA All 1/O pins high Output Buffer Supply Current Ixx ~~ 1 5 mA All I/O pins high (Note 3) input Low Voltage VIL 6.2 ~ 0.8 Vv Input High Voltage (except MCLR, RTCC & OSC when driven externally) Vint 24 ~ Voo Vv input High Voltage (MCLR, RTCC & OSC) Vina Voo~-1 ~_ Voo v Output High Voltage Vou 2.4 _ Voo Vv Ton = 100uA provided by internal puJlups (Note 4) Output Low Voltage (I/O only) Vou 0.45 Vv To = 1.6MA, Vex = 4.5V ~ 0.90 v To. = 5.0MA, Vax = 4.5V 0.90 Vv To. = 5.0MA, Vix = 8.0V _ 1.20 Vv To. = 10.0MA, Vex = 8.0V 2.0 Vv To. = 20.0MA, Vix = 8.0V (Note 5) Output Low Voltage (CLK OUT) Vore _ _ 0.45 Vv lo. = 1.6mA (Note 5) Input Leakage Current (MCLA, RTCC) Inc =10 _ +10 A Vss < Vin < Voo Input Low Current (all I/O ports) In -0.2 -0.6 1.6 mA Va = 0.4V internal pullup Input High Current (all I/O ports) TH 0.1 0.4 _ mA Vin = 2.4V NOTES: 1. Power dissipation for I/O pins is calculated by E (Vee Vit) ([Iu}} + E (Vee Vou) (\Tou|) + E (Vor) (Tov). The term1/O refers to all interface pins; input, ouput or1/O. 2. Vax Supply drives only the I/O ports. 3. The maximum Ixx current will be drawn when all 1/O ports are outputting a High. 4. Positive current indicates current into pin. Negative current indicates current out of pin. 5. Total Io. for all output pins (I/O ports plus CLK OUT) must not exceed 225mA. 275PIC1650A Standard Conditions (unless otherwise stated): AC CHARACTERISTICS Operating Temperature T, = 0C to +70C Characteristic Sym Min Typ Max Units Conditions instruction Cycle Time tey 4 - 20 us 0.2MHz 1.0MHz external time base (Note 1) RTCC input Period tar tey _ - - High Pulse Width trv Vatey _ _ _ Low Pulse Width tate Vatey _ _- _ (Note 2) T/O Ports Data Input Setup Time ts - [%tey-125) ong Data Input Hold Time th 0 _ _ ns Data Output Propagation Delay tea _ 500 800 ns Capacitive load = 50pF OSC Input External Input Impedance High Roscn _ 120 - 2 Vosc = 5V Applies to external External Input Impedance Low Rose. _ 10 = Q Vose = sa} OSC drive only. NOTES: 1. Instruction cycle period (tcy) equals four times the input oscillator time base period. pling circuit used on the RTCC input, CLK OUT may be 2. Due to the synchronous timing nature between CLK OUT and the sam directly tied to the ATCC input. 276PIC1650A CLK OUT \ TX TX _.) GATE t INCREMENT ANSWER WRITE PC be-EXECUTE TO ADDRESS ROM INSTRUCTION |INTERNAL vo FOR NEXT BUS INSTRUCTION Pt + OUTPUT VALID | { | | le | \ | \ INPUT \<ag- STABLE b>! NOTE: | | | Rise and fall times are load dependent. Fig.6 1/0 timing Fig.8 RTCC timing Vo (VOLTS) TYPICAL HYSTERESIS Vo (VOLTS) 15 27 MCLA, OSC VDD =5V TA = 25C Vi (VOLTS) VI (VOLTS) Fig.9 Schmitt trigger characteristics 277PIC1650A PIC 1650A OSCILLATOR OPTIONS (TYPICAL CIRCUITS) Yoo R (ext) TO PIC1650A PIN #36 I C (ext) Vpp = 5.0v Cc =47pF 22kQ TA = 25C Rext 14k. 40 60 80 100 120 140 160 180 200 220 240 260 INSTRUCTION CYCLE TIME (kHz) Oscillator Frequency With Typical Unit to Unit Variance Unit to Unit Variation at Voo = 5.0V, Ta = 25C is +25% Variation from Vpo = 4.5V 7.0V referenced to 5V is 3%, +9% Variation from T, = 0C 70C referenced to 25C is +3%, -5% Fig.10 RC option operation XTAL In| }OF R ____}_+ r an an >O> TO Osc PIN #36 ~~ ec ~~ 30% < DUTY CYCLE < 70% Fig.11 Buffered crystal input operation CLOCK FROM EXT. SYSTEM >> TO OSC PIN #36 Fig.12 External clock input operation 278PIC1650A voo Rl | AC00k TO PIC 1650A MCLR PIN#37 T Master Clear requires > 1.0ms delay before activation after power is applied to the Vop pin. To achieve this, an external RC configuration as shown can be used (assuming Voo is applied as a step function). Fig.13 Master clear lot (mA) Vot (VOLTS) lou vs. Vor TYP @ 25C The Output Sink Current is dependent on the Vxx supply and the output load. This chart shows the typical curves used to express the output drive capability. Fig.14 Output sink current graph T | VDD = VXX = 4.25V voD = 7.0v F UTA = 25C _ g z TA = 85C N 2 > WY = 40C : ~ \ 200 400 600s (1000 40 0 40 80 =| 120 10H (A) TEMPERATURE (C) Fig.15 Vou VS fox (1/O ports) Fig.16 Power supply current vs temperature 279PIC1650A PIC1650A. EMULATION CAUTIONS When emulating a PIC1650A using a PICES development system certain precautions should be taken. A. Be sure that the PICES Module being used is programmed for the PIC1650A mode. (Refer to PICES Manual). The PIC1664B contained within the module should have the MODE pin #22 set to a high state. 1. This causes the MCLR to force all I/O registers high. 2. The OSC 1 pin #59 becomes a single clock input pin. 3. The interrupt system becomes disabled and the RTCC always counts on the trailing edges. 4. Bits 3 through 7 on file register F3 are all ones. B. Make sure to only use two levels of stack Within the program. 280 C. Make sure all I/O cautions contained in this spec sheet are used. D. Be sure to use the 40 pin socket for the module plug. E.__Make sure that during an actual application that the MCLR input swings from a low to high level a minimum of 1msec after the supply voltage is applied. F. If an external oscillator drive is used, be sure that it can drive the 1202 input impedance of the OSC pin on the PIC1650A. G. The cable length and internal variations may cause some parameter values to differ between the PICES module and a production PIC1650A.