32-Channel, 16-/14-Bit,
Serial Input, Voltage Output DAC
AD5372/AD5373
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
32-channel DAC in a 64-lead LQFP and 64-lead LFCSP
AD5372/AD53731 guaranteed monotonic to 16/14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Digital reset (RESET)
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INTERFACE
05815-001
SDI
DV
CC
V
DD
V
SS
AGND DGND
SCLK
SDO
SYNC
BUSY
RESET
CLR
STATE
MACHINE
CONTROL
REGISTER
AD5372/
AD5373
X1 REGISTER
n = 16 FOR AD5372
n = 14 FOR AD5373
M REGISTER
C REGISTER
DAC 0
REGISTER
OFS0
REGISTER
GROUP 2 TO GROUP 3
ARE IDENTICAL TO GROUP 1
VREF1 SUPPLIES
GROUP 1 TO GROUP 3
X2A REGISTER
X2B REGISTER
BUFFER
BUFFER GROUP 0
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
VOUT7
SIGGND0
SIGGND1
SIGGND3
SIGGND2
VOUT16
TO
VOUT31
LDAC
n
n
n n n
14
n
n
n
nn
n
n
A/B
MUX
MUX
2
OFFSET
DAC 0
DAC 0
X1 REGISTER
M REGISTER
C REGISTER
DAC 7
REGISTER
X2A REGISTER
X2B REGISTER
n n n n n
nn
n
n
A/B
MUX
MUX
2
DAC 7
X1 REGISTER
A/B SELECT
REGISTER
M REGISTER
C REGISTER
TO
MUX 2s
DAC 0
REGISTER
OFS1
REGISTER
X2A REGISTER
X2B REGISTER
BUFFER
BUFFER GROUP 1
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
OUTPUT BUFFER
AND POWER-
DOWN CONTROL
n
8 8
n n n
14
n
nn
n
n
A/B
MUX
MUX
2
OFFSET
DAC 1
DAC 0
X1 REGISTER
M REGISTER
C REGISTER
DAC 7
REGISTER
X2A REGISTER
X2B REGISTER
n n n n n
nn
n
n
A/B
MUX
MUX
2
DAC 7
VREF1
A/B SELECT
REGISTER
TO
MUX 2s
88
Figure 1.
1 Protected by U.S. Patent No. 5,969,657.
AD5372/AD5373
Rev. C | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions......................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
DAC Architecture....................................................................... 15
Channel Groups.......................................................................... 15
A/B Registers and Gain/Offset Adjustment............................ 16
Load DAC.................................................................................... 16
Offset DACs ................................................................................ 16
Output Amplifier........................................................................ 17
Transfer Function....................................................................... 17
Reference Selection .................................................................... 17
Calibration................................................................................... 18
Additional Calibration............................................................... 19
Reset Function............................................................................ 19
Clear Function............................................................................ 19
BUSY and LDAC Functions...................................................... 19
Power-Down Mode.................................................................... 20
Thermal Shutdown Function ................................................... 20
Toggle Mode................................................................................ 20
Serial Interface ................................................................................ 21
SPI Write Mode .......................................................................... 21
SPI Readback Mode ................................................................... 21
Register Update Rates................................................................ 21
Channel Addressing and Special Modes................................. 22
Special Function Mode.............................................................. 23
Applications Information.............................................................. 24
Power Supply Decoupling......................................................... 24
Power Supply Sequencing ......................................................... 24
Interfacing Examples ................................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
7/11—Rev. B to Rev. C
Added 64-Lead LFCSP Package........................................Universal
Change to Features Section............................................................. 1
Change to General Description Section........................................ 3
Changes to Table 5............................................................................ 9
Added Figure 7; Renumbered Sequentially ................................ 10
Changes to Table 6.......................................................................... 10
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 25
2/08—Rev. A to Rev. B
Added Table 1.................................................................................... 3
Changes to t10 Parameter ................................................................. 6
Added t23 Parameter ......................................................................... 6
Changes to Figure 4.......................................................................... 7
Changes to Absolute Maximum Ratings Section..........................9
Changes to Pin Configuration and Function Descriptions
Section.............................................................................................. 10
Changes to Reset Function Section.............................................. 18
12/07—Rev. 0 to Rev. A
Changes to Table 3.............................................................................6
Changes to AD5373 Transfer Function Section......................... 16
Changes to Calibration Section.................................................... 17
Changes to Table 8.......................................................................... 18
Changes to Register Update Rates Section.................................. 20
Changes to Ordering Guide.......................................................... 25
8/07—Revision 0: Initial Version
AD5372/AD5373
Rev. C | Page 3 of 28
GENERAL DESCRIPTION
The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead
LQFP and LFCSP packages. The devices provide buffered
voltage outputs with a nominal span of 4× the reference voltage.
The gain and offset of each DAC can be independently trimmed
to remove errors. For even greater flexibility, the device is divided
into four groups of eight DACs. Two offset DACs allow the
output range of the groups to be altered. Group 0 can be adjusted
by Offset DAC 0, and Group 1 to Group 3 can be adjusted by
Offset DAC 1.
The AD5372/AD5373 offer guaranteed operation over a wide
supply range: VSS from −16.5 V to −4.5 V and VDD from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
The AD5372/AD5373 have a high speed serial interface that is
compatible with SPI, QSPI™, MICROWIRE™, and DSP inter-
face standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All
the outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)
AD5360 16 4 × VREF (20 V) 16 ±4
AD5361 14 4 × VREF (20 V) 16 ±1
AD5362 16 4 × VREF (20 V) 8 ±4
AD5363 14 4 × VREF (20 V) 8 ±1
AD5370 16 4 × VREF (12 V) 40 ±4
AD5371 14 4 × VREF (12 V) 40 ±1
AD5372 16 4 × VREF (12 V) 32 ±4
AD5373 14 4 × VREF (12 V) 32 ±1
AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3
AD5372/AD5373
Rev. C | Page 4 of 28
SPECIFICATIONS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V;
CL = open circuit; RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter
AD53721
B Version
AD53731
B Version Unit Test Conditions/Comments2
ACCURACY
Resolution 16 14 Bits
Integral Nonlinearity (INL) ±4 ±1 LSB max
Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic by design over
temperature
Zero-Scale Error ±10 ±10 mV max Before calibration
Full-Scale Error ±10 ±10 mV max Before calibration
Gain Error 0.1 0.1 % FSR Before calibration
Zero-Scale Error2 1 1 LSB typ After calibration
Full-Scale Error2 1 1 LSB typ After calibration
Span Error of Offset DAC ±35 ±35 mV max See the Offset DACS section for details
VOUTx Temperature Coefficient 5 5 ppm FSR/°C typ Includes linearity, offset, and gain drift
DC Crosstalk2 100 100 μV max Typically 20 μV; measured channel at midscale,
full-scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1)2
VREFx Input Current ±10 ±10 μA max Per input; typically ±30 nA
VREFx Range 2/5 2/5 V min/V max ±2% for specified operation
SIGGND INPUTS (SIGGND0 TO SIGGND3)2
DC Input Impedance 50 50 kΩ min Typically 55 kΩ
Input Range ±0.5 ±0.5 V min/V max
SIGGNDx Gain 0.995/1.005 0.995/1.005 min/max
OUTPUT CHARACTERISTICS2
Output Voltage Range VSS + 1.4 VSS + 1.4 V min ILOAD = 1 mA
V
DD − 1.4 VDD − 1.4 V max ILOAD = 1 mA
Nominal Output Voltage Range −4 to +8 −4 to +8 V min/V max
Short-Circuit Current 15 15 mA max VOUTx to DVCC, VDD, or VSS
Load Current ±1 ±1 mA max
Capacitive Load 2200 2200 pF max
DC Output Impedance 0.5 0.5 Ω max
DIGITAL INPUTS JEDEC compliant
Input High Voltage 1.7 1.7 V min DVCC = 2.5 V to 3.6 V
2.0 2.0 V min DVCC = 3.6 V to 5.5 V
Input Low Voltage 0.8 0.8 V max DVCC = 2.5 V to 5.5 V
Input Current ±1 ±1 μA max Excluding CLR pin
CLR High Impedance Leakage Current ±20 ±20 μA max
Input Capacitance2 10 10 pF max
DIGITAL OUTPUTS (SDO, BUSY)
Output Low Voltage 0.5 0.5 V max Sinking 200 μA
Output High Voltage (SDO) DVCC − 0.5 DVCC − 0.5 V min Sourcing 200 μA
SDO High Impedance Leakage Current ±5 ±5 μA max
High Impedance Output Capacitance2 10 10 pF typ
AD5372/AD5373
Rev. C | Page 5 of 28
Parameter
AD53721
B Version
AD53731
B Version Unit Test Conditions/Comments2
POWER REQUIREMENTS
DVCC 2.5/5.5 2.5/5.5 V min/V max
VDD 9/16.5 9/16.5 V min/V max
VSS −16.5/−4.5 −16.5/−4.5 V min/V max
Power Supply Sensitivity2
∆Full Scale/∆VDD −75 −75 dB typ
∆Full Scale/∆VSS −75 −75 dB typ
∆Full Scale/∆DVCC −90 −90 dB typ
DICC 2 2 mA max DVCC = 5.5 V, VIH = DVCC, VIL = GND
IDD 16 16 mA max Outputs unloaded, DAC outputs = 0 V
18 18 mA max Outputs unloaded, DAC outputs = full scale
ISS −16 −16 mA max Outputs unloaded, DAC outputs = 0 V
−18 −18 mA max Outputs unloaded, DAC outputs = full scale
Power-Down Mode Bit 0 in the control register is 1
DICC 5 5 μA typ
IDD 35 35 μA typ
ISS −35 −35 μA typ
Power Dissipation (Unloaded) 250 250 mW typ VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V
Junction Temperature3 130 130 °C max TJ = TA + PTOTAL × θJA
1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization; not production tested.
3 θJA represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter B Version Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time 20 μs typ Full-scale change
30 μs max DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs typ
Digital-to-Analog Glitch Energy 5 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 10 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V
1 Guaranteed by design and characterization; not production tested.
AD5372/AD5373
Rev. C | Page 6 of 28
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter 1, 2, 3 Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 11 ns min
SYNC falling edge to SCLK falling edge setup time
t5 20 ns min
Minimum SYNC high time
t6 10 ns min
24th SCLK falling edge to SYNC rising edge
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t94 42 ns max
SYNC rising edge to BUSY falling edge
t10 1/1.5 μs typ/μs max BUSY pulse width low (single-channel update); see Table 9
t11 600 ns max Single-channel update cycle time
t12 20 ns min
SYNC rising edge to LDAC falling edge
t13 10 ns min LDAC pulse width low
t14 3 μs max BUSY rising edge to DAC output response time
t15 0 ns min BUSY rising edge to LDAC falling edge
t16 3 μs max LDAC falling edge to DAC output response time
t17 20/30 μs typ/μs max DAC output settling time
t18 140 ns max CLR/RESET pulse activation time
t19 30 ns min
RESET pulse width low
t20 400 μs max
RESET time indicated by BUSY low
t21 270 ns min
Minimum SYNC high time in readback mode
t225 25 ns max SCLK rising edge to SDO valid
t23 80 ns max
RESET rising edge to BUSY falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 t9 is measured with the load circuit shown in Figure 2
.
5 t22 is measured with the load circuit shown in Figure 3.
TO
OUTPUT
PIN C
L
50pF
R
L
2.2k
V
OL
DV
CC
05815-002
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OH
T
O OUTPUT
PIN C
L
50pF
0
5815-003
Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram
AD5372/AD5373
Rev. C | Page 7 of 28
SCLK
SYNC
SDI
BUSY
V
OUTx
1
V
OUTx
2
VOUTx
RESET
VOUTx
CLR
12
24
t
8
t
12
t
10
t
13
t
17
t
14
t
15
t
13
t
17
t
9
t
7
t
5
t
4
t
2
t
6
DB23 DB0
t
16
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
BUSY
LDAC
1
LDAC
2
1
t
3
t
20
t
23
t
18
t
18
t
19
24
t
11
t
1
05815-004
Figure 4. SPI Write Timing
AD5372/AD5373
Rev. C | Page 8 of 28
05815-005
SDI
SDO
48
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
SELECTED REGISTER DATA CLOCKED OUT
t
22
t
21
LSB FROM PREVIOUS WRITE
SCLK
SYNC
DB0
DB0
DB0
DB0 DB23DB23
DB23 DB15
Figure 5. SPI Read Timing
DAC CODE
FULL-SCALE
ERROR
+
ZERO-SCALE
ERROR
ZERO-SCALE
ERROR
–4V
0 16383
8V
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OUTPUT
VOLTAGE
05815-006
Figure 6. DAC Transfer Function
AD5372/AD5373
Rev. C | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
VREF0, VREF1 to AGND −0.3 V to +5.5 V
VOUT0 through VOUT31 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGNDx to AGND −1 V to +1 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 130°C
θJA Thermal Impedance
64-Lead LFCSP 25.5°C/W
64-Lead LQFP 45.5°C/W
Reflow Soldering
Peak Temperature 230°C
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5372/AD5373
Rev. C | Page 10 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
NC
NC
NC
NC
NC
NC
NC
V
DD
BUSY
RESET
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
V
SS
VOUT20
V
DD
SIGGND2
VOUT19
VOUT4
VOUT5
VOUT26
VOUT25
VOUT24
AGND
DGND
DV
CC
SDO
SDI
SCLK
DV
CC
DGND
VOUT7
VOUT6
NC
NC
VOUT8
VOUT9
VOUT10
VOUT11
SIGGND1
VOUT12
VOUT13
VOUT15
VOUT14
VOUT16
VOUT17
VOUT18
VREF1
V
SS
CLR
LDAC
SYNC
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
11
47
46
45
42
43
44
48
41
40
39
37
36
35
34
33
38
NC = NO CONNECT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
05815-007
AD5372/AD5373
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VREF1
NC
NC
VOUT8
VOUT9
VOUT10
VOUT11
SIGGND1
VOUT12
VOUT13
VOUT14
VOUT15
VOUT16
VOUT17
VOUT18
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CLR
VOUT26
VOUT25
VOUT24
AGND
DGND
DVCC
SDO
SDI
SCLK
DVCC
DGND
VOUT7
VOUT6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
RESET
BUSY
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
NC
NC
NC
NC
NC
NC
NC
VDD
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
VSS
VDD
SIGGND2
VOUT19
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
TOP VIEW
AD5372/AD5373
(Not to Scale)
LDAC
SYNC
NOTES
1. NC = NO CONNECT.
2. THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP) HAS AN EXPOSED PAD
ON THE UNDERSIDE. CONNECT THE EXPOSED PAD TO VSS.
PIN 1
INDICATOR
05815-107
Figure 7. 64-Lead LFCSP Pin Configuration Figure 8. 64-Lead LQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
0 EPAD
Exposed Pad. The lead frame chip scale package (LFCSP) has an exposed pad on the
underside. Connected the exposed pad to VSS.
1 RESET Digital Reset Input.
2 BUSY Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and
LDAC Functions section for more information.
42 to 45, 47 to 50, 21 to 24,
26 to 33, 37 to 40, 60 to 62,
3, 5 to 8
VOUT0 to
VOUT31
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is
capable of driving an output load of 10 kΩ to ground. Typical output impedance of these
amplifiers is 0.5 Ω.
4 SIGGND3 Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
9 to 15, 19, 20 NC No Connect.
16, 35 VDD Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be
decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
17, 36 VSS Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should
be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
18 VREF1 Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.
25 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
34 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
41 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
46 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
51, 58 DGND Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.
52, 57 DVCC Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
53 SYNC Active Low Input. This is the frame synchronization signal for the serial interface.
54 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 50 MHz.
55 SDI Serial Data Input. Data must be valid on the falling edge of SCLK.
AD5372/AD5373
Rev. C | Page 11 of 28
Pin No. Mnemonic Description
56 SDO
Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO
on the rising edge of SCLK and is valid on the falling edge of SCLK.
59 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
63 LDAC Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more
information.
64 CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for
more information.
AD5372/AD5373
Rev. C | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
2
–2
0 65535
05815-008
DAC CODE
INL (LSB)
1
0
–1
16384 32768 49152
Figure 9. Typical AD5372 INL Plot
1.0
–1.0
08
05815-009
TEMPERATURE (°C)
INL ERROR (LSB)
0
0.5
0
–0.5
20 40 60
V
DD
= +15V
V
SS
= –15V
DV
CC
= +5V
VREFx = +3V
Figure 10. Typical INL Error vs. Temperature
–0.02
–0.01
0
AMPLITUDE (V)
024681
TIME (µs)
0
T
A
= 25°C
V
SS
= –15V
V
DD
= +15V
VREFx = +4.096V
0
5815-010
Figure 11. Analog Crosstalk Due to LDAC
0.0050
–0.0050
05
05815-011
TIME (µs)
AMPLITUDE (V)
0
0.0025
–0.0025
1234
TA = 25°C
VSS = –15V
VDD = +15V
VREFx = +4.096V
Figure 12. Digital Crosstalk
1.0
–1.0
0 65535
05815-012
DAC CODE
DNL (LSB)
0
0.5
–0.5
16384 32768 49152
Figure 13. Typical AD5372 DNL Plot
600
0
05
05815-013
FREQUENCY (Hz)
OUTPUT NOISE (nV/Hz)
200
300
400
500
100
1234
Figure 14. Output Noise Spectral Density
AD5372/AD5373
Rev. C | Page 13 of 28
0.50
0.45
0.40
0.35
0.30
0.25
–40 80
05815-014
TEMPERATURE (°C)
DI
CC
(mA)
–20 0 20 6040
DV
CC
= +5.5V
DV
CC
= +3.6V
DV
CC
= +2.5V
V
SS
= –12V
V
DD
= +12V
VREFx = +3V
Figure 15. DICC vs. Temperature
13.5
13.0
12.5
12.0
11. 5
–40 80
05815-015
TEMPERATURE (°C)
I
DD
/I
SS
(mA)
–20 0 20 6040
V
SS
= –12V
V
DD
= +12V
VREFx = +3V
I
SS
I
DD
Figure 16. IDD/ISS vs. Temperature
05815-016
14
12
10
8
6
4
2
012.6 12.8 13.0 13.2 13.4
V
SS
= –15V
V
DD
= +15V
T
A
= 25°C
NUMBER OF UNITS
I
DD
(mA)
Figure 17. Typical IDD Distribution
05815-017
14
12
10
8
6
4
2
00.30 0.35 0.40 0.45 0.50
DV
CC
= 5V
T
A
= 25°C
NUMBER OF UNITS
DI
CC
(mA)
Figure 18. Typical DICC Distribution
AD5372/AD5373
Rev. C | Page 14 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity, or endpoint linearity, is a measure of
the maximum deviation from a straight line passing through
the endpoints of the DAC transfer function. It is measured
after adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
all 0s are loaded into the DAC register. Zero-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its mini-
mum value. Zero-scale error is mainly due to offsets in the
output amplifier.
Full-Scale Error
Full-scale error is the error in the DAC output voltage when
all 1s are loaded into the DAC register. Full-scale error is a
measure of the difference between VOUT (actual) and VOUT
(ideal), expressed in millivolts, when the channel is at its maxi-
mum value. Full-scale error does not include zero-scale error.
Gain Error
Gain error is the difference between full-scale error and
zero-scale error. It is expressed as a percentage of the full-
scale range (FSR).
Gain Error = Full-Scale ErrorZero-Scale Error
VOUT Temperature Coefficient
The VOUT temperature coefficient includes output error
contributions from linearity, offset, and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
VDD and VSS power supplies. If the dc load current changes in
one channel (due to an update), this change can result in a
further dc change in one or more channel outputs. This effect is
more significant at high load currents and is reduced as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple VDD and VSS terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It is
specified as the area of the glitch in nV-s. It is measured by
toggling the DAC register data between 0x7FFF and 0x8000
(AD5372) or 0x1FFF and 0x2000 (AD5373).
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at
the output of one converter due to both the digital change
and subsequent analog output change at another converter. It
is specified in nV-s.
Digital Crosstalk
Digital crosstalk is defined as the glitch impulse transferred to
the output of one converter due to a change in the DAC register
code of another converter. It is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the digital inputs of the device can be capacitively coupled
both across and through the device to appear as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading
all DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz.
AD5372/AD5373
Rev. C | Page 15 of 28
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5372/AD5373 contain 32 DAC channels and 32 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit (AD5372) or 14-bit (AD5373)
resistor-string DAC followed by an output buffer amplifier.
The resistor-string section is simply a string of resistors (of
equal value) from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC output voltage by 4.
The nominal output span is 12 V with a 3 V reference and 20 V
with a 5 V reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5372/AD5373 Registers
Register Name
Word Length
in Bits Description
X1A (Group) (Channel) 16 (14) Input Data Register A, one for each DAC channel.
X1B (Group) (Channel) 16 (14) Input Data Register B, one for each DAC channel.
M (Group) (Channel) 16 (14) Gain trim registers, one for each DAC channel.
C (Group) (Channel) 16 (14) Offset trim registers, one for each DAC channel.
X2A (Group) (Channel) 16 (14) Output Data Register A, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
X2B (Group) (Channel) 16 (14) Output Data Register B, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
DAC (Group) (Channel) Data registers from which the DACs take their final input data. The DAC registers are updated
from the X2A or X2B registers. They are not readable or directly writable.
OFS0 14 Offset DAC 0 data register: sets offset for Group 0.
OFS1 14 Offset DAC 1 data register: sets offset for Group 1 to Group 3.
Control 3
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = global selection of X1B input data registers.
Bit 1 = enable thermal shutdown.
0 = disable thermal shutdown.
1 = enable thermal shutdown.
Bit 0 = software power-down.
0 = software power-up.
1 = software power-down.
A/B Select 0 8 Each bit in this register determines whether a DAC in Group 0 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 1 8 Each bit in this register determines whether a DAC in Group 1 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 2 8 Each bit in this register determines whether a DAC in Group 2 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 3 8 Each bit in this register determines whether a DAC in Group 3 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Table 8. AD5372/AD5373 Input Register Default Values
Register Name AD5372 Default Value AD5373 Default Value
X1A, X1B 0x5554 0x1555
M 0xFFFF 0x3FFF
C 0x8000 0x2000
OFS0, OFS1 0x1555 0x1555
Control 0x00 0x00
A/B Select 0 to A/B Select 3 0x00 0x00
AD5372/AD5373
Rev. C | Page 16 of 28
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or the X1B input
register, depending on the setting of the A/B bit in the control
register. If the A/B bit is 0, data is written to the X1A register.
If the A/B bit is 1, data is written to the X1B register. Note that
this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per-
channel basis so that some writes are to X1A registers and
some writes are to X1B registers.
05815-018
MUX DAC
DAC
REGISTER
MUX
X1A
REGISTER
X1B
REGISTER
M
REGISTER
C
REGISTER
X2A
REGISTER
X2B
REGISTER
Figure 19. Data Registers Associated with Each DAC Channel
Each DAC channel also has a gain (M) register and an offset
(C) register, which allow trimming out of the gain and offset
errors of the entire signal chain. Data from the X1A register is
operated on by a digital multiplier and adder controlled by the
contents of the M and C registers. The calibrated DAC data is
then stored in the X2A register. Similarly, data from the X1B
register is operated on by the multiplier and adder and stored in
the X2B register.
Although a multiplier and adder symbol are shown in Figure 19
for each channel, there is only one multiplier and one adder in the
device, which are shared among all channels. This has implica-
tions for the update speed when several channels are updated at
once, as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or
C register with the A/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B,
or to M or C with A/B set to 1. The X2A and X2B registers
are not readable or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or from the X2B register is
controlled by an 8-bit A/B select register associated with each
group of eight DACs. If a bit in this register is 0, the DAC takes
its data from the X2A register; if 1, the DAC takes its data from
the X2B register (Bit 0 through Bit 7 control DAC 0 to DAC 7).
Note that because there are 32 bits in four registers, it is possible to
set up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also provided
that sets all bits in the A/B select registers to 0 or to 1.
LOAD DAC
All DACs in the AD5372/AD5373 can be updated simultane-
ously by taking LDAC low when each DAC register is updated
from either its X2A or X2B register, depending on the setting
of the A/B select registers. The DAC register is not readable or
directly writable by the user. LDAC can be permanently tied
low, and the DAC output is updated whenever new data appears
in the appropriate DAC register.
OFFSET DACs
In addition to the gain and offset trim for each DAC, there are
two 14-bit offset DACs, one for Group 0 and one for Group 1 to
Group 3. These allow the output range of all DACs connected to
them to be offset within a defined range. Thus, subject to the
limitations of headroom, it is possible to set the output range of
Group 0 or Group 1 to Group 3 to be unipolar positive, unipolar
negative, or bipolar, either symmetrical or asymmetrical about
0 V. The DACs in the AD5372/AD5373 are factory trimmed with
the offset DACs set at their default values. This gives the best offset
and gain performance for the default output range and span.
When the output range is adjusted by changing the value of the
offset DAC, an extra offset is introduced due to the gain error of
the offset DAC. The amount of offset is dependent on the
magnitude of the reference and how much the offset DAC
moves from its default value. See the Specifications section for
this offset. The worst-case offset occurs when the offset DAC is
at positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can
be removed by programming the C register of the channel with
an appropriate value. The extra offset caused by the offset DAC
needs to be taken into account only when the offset DAC is
changed from its default value. Figure 20 shows the allowable
code range that can be loaded to the offset DAC, depending on
the reference value used. Thus, for a 5 V reference, the offset
DAC should not be programmed with a value greater than 8192
(0x2000).
5
0016383
05815-019
OFFS ET DAC CODE
VREF (V)
4
3
2
1
4096 8192 12288
RESERVED
Figure 20. Offset DAC Code Range
AD5372/AD5373
Rev. C | Page 17 of 28
OUTPUT AMPLIFIER
Because the output amplifiers can swing to 1.4 V below the
positive supply and 1.4 V above the negative supply, this limits
how much the output can be offset for a given reference voltage.
For example, it is not possible to have a unipolar output range
of 20 V, because the maximum supply voltage is ±16.5 V.
05815-020
CLR
CLR
CLR
DAC
CHANNEL
OFFSET
DAC
OUTPU
T
R6
10k
R2
20k
S3
S2
S1
R4
60kR3
20k
SIGGNDx
SIGGNDx
R5
60k
R1
20k
Figure 21. Output Amplifier and Offset DAC
Figure 21 shows details of a DAC output amplifier and its
connections to the offset DAC. On power-up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so
the output is pulled to SIGGNDx (R1 and R2 are greater than
R6). S2 is also closed to prevent the output amplifier from being
open-loop. If CLR is low at power-up, the output remains in this
condition until CLR is taken high. The DAC registers can be
programmed, and the outputs assume the programmed values
when CLR is taken high. Even if CLR is high at power-up, the
output remains in the previous condition until VDD > 6 V and
VSS < −4 V and the initialization sequence has finished. The
outputs then go to their power-on default value.
TRANSFER FUNCTION
The output voltage of a DAC in the AD5372/AD5373 is depend-
ent on the value in the input register, the value of the M and C
registers, and the value in the offset DAC.
AD5372 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 21,844).
DAC_CODE = INPUT_CODE × (M + 1)/216 + C − 215
where:
M = code in gain register − default code = 216 – 1.
C = code in offset register − default code = 215.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREFx × (DAC_CODE – (OFFSET_CODE ×
4))/216 + VSIGGND
where:
DAC_CODE should be within the range of 0 to 65,535.
For 12 V span, VREFx = 3.0 V.
For 20 V span, VREFx = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because this DAC is
a 14-bit device. On power-up, the default code loaded to the
offset DAC is 5461 (0x1555). With a 3 V reference, this gives
a span of −4 V to +8 V.
AD5373 Transfer Function
The input code is the value in the X1A or X1B register that is
applied to the DAC (X1A, X1B default code = 5461).
DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213
where:
M = code in gain register − default code = 214 – 1.
C = code in offset register − default code = 213.
The DAC output voltage is calculated as follows:
VOUT = 4 × VREFx × (DAC_CODE
OFFSET_CODE)/214 + VSIGGND
where:
DAC_CODE should be within the range of 0 to 16,383.
For 12 V span, VREFx = 3.0 V.
For 20 V span, VREFx = 5.0 V.
OFFSET_CODE is the code loaded to the offset DAC.
On power-up, the default code loaded to the offset DAC
is 5461 (0x1555). With a 3 V reference, this gives a span
of −4 V to +8 V.
REFERENCE SELECTION
The AD5372/AD5373 have two reference input pins. The
voltage applied to the reference pins determines the output
voltage span on VOUT0 to VOUT31. VREF0 determines the
voltage span for VOUT0 to VOUT7 (Group 0), and VREF1
determines the voltage span for VOUT8 to VOUT31 (Group 1
to Group 3). The reference voltage applied to each VREF pin
can be different, if required, allowing the groups to have
different voltage spans. The output voltage range and span
can be adjusted further by programming the offset and gain
registers for each channel as well as programming the offset
DACs. If the offset and gain features are not used (that is, the
M and C registers are left at their default values), the required
reference levels can be calculated as follows:
VREF = (VOUTMAXVOUTMIN)/4
If the offset and gain features of the AD5372/AD5373 are used,
the required output range is slightly different. The selected
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the selected
output range should be larger than the actual required range.
AD5372/AD5373
Rev. C | Page 18 of 28
The required reference levels can be calculated as follows:
1. Identify the nominal output range on VOUT.
2. Identify the maximum offset span and the maximum gain
required on the full output signal range.
3. Calculate the new maximum output range on VOUT,
including the expected maximum offset and gain errors.
4. Choose the new required VOUTMAX and VOUTMIN,
keeping the VOUT limits centered on the nominal values.
Note that VDD and VSS must provide sufficient headroom.
5. Calculate the value of VREF as follows:
VREF = (VOUTMAXVOUTMIN)/4
Reference Selection Example
If
Nominal output range = 12 V (−4 V to +8 V)
Zero-scale error = ±70 mV
Gain error = ±3%, and
SIGGNDx = AGND = 0 V
Then
Gain error = ±3%
=> Maximum positive gain error = 3%
=> Output range including gain error = 12 + 0.03(12) = 12.36 V
Zero-scale error = ±70 mV
=> Maximum offset error span = 2(70 mV) = 0.14 V
=> Output range including gain error and zero-scale error =
12.36 V + 0.14 V = 12.5 V
VREF calculation
Actual output range = 12.5 V, that is, −4.25 V to +8.25 V;
VREF = (8.25 V + 4.25 V)/4 = 3.125 V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the reference.
In this way, the user can use almost any convenient reference
level but can reduce the performance by overcompaction of
the transfer function.
Use a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5372/
AD5373 to reduce gain and offset errors to below 1 LSB. This
reduction is achieved by calculating new values for the M and C
registers and reprogramming them.
The M and C registers should not be programmed until both
the zero-scale and full-scale errors are calculated.
Reducing Zero-Scale Error
Zero-scale error can be reduced as follows:
1. Set the output to the lowest possible value.
2. Measure the actual output voltage and compare it to the
required value. This gives the zero-scale error.
3. Calculate the number of LSBs equivalent to the error and
add this number to the default value of the C register. Note
that only negative zero-scale error can be reduced.
Reducing Full-Scale Error
Full-scale error can be reduced as follows:
1. Measure the zero-scale error.
2. Set the output to the highest possible value.
3. Measure the actual output voltage and compare it to the
required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.
4. Calculate the number of LSBs equivalent to the span error
and subtract this number from the default value of the M
register. Note that only positive full-scale error can be
reduced.
AD5372 Calibration Example
This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but is measured at −4.03 V. This
gives a zero-scale error of −30 mV.
1 LSB = 12 V/65,536 = 183.105 μV
30 mV = 164 LSBs
The full-scale error can now be calculated. The output is set to
8 V and a value of 8.02 V is measured. This gives a full-scale
error of +20 mV and a span error of +20 mV – (–30 mV) =
+50 mV.
50 mV = 273 LSBs
The errors can now be removed as follows:
1. Add 164 LSBs to the default C register value:
(32,768 + 164) = 32,932
2. Subtract 273 LSBs from the default M register value:
(65,535 − 273) = 65,262
3. Program the M register to 65,262; program the C register
to 32,932.
AD5372/AD5373
Rev. C | Page 19 of 28
ADDITIONAL CALIBRATION
The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently reduced. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the reference
value. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range, for the AD5372 or the AD5373, is −4 V to +8 V.
Using a +3.1 V reference increases the range to −4.133 V to
+8.2667 V. Clearly, in this case, the offset and gain errors are
insignificant, and the M and C registers can be used to raise
the negative voltage to −4 V and then reduce the maximum
voltage to +8 V to give the most accurate values possible.
RESET FUNCTION
The reset function is initiated by the RESET pin. On the rising
edge of RESET, the AD5372/AD5373 state machine initiates a
reset sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom-
mended that the user bring RESET high as soon as possible to
properly initialize the registers.
When the reset sequence is complete (and provided that CLR is
high), the DAC output is at a potential specified by the default
register settings, which is equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and LDAC is taken low. The AD5372/AD5373 can be
returned to the default state by pulsing RESET low for at least
30 ns. Note that, because the reset function is triggered by the
rising edge, bringing RESET low has no effect on the operation
of the AD5372/AD5373.
CLEAR FUNCTION
CLR is an active low input that should be high for normal opera-
tion. The CLR pin has an internal 500 kΩ pull-down resistor.
When CLR is low, the input to each of the DAC output buffer
stages (VOUT0 to VOUT31) is switched to the externally set
potential on the relevant SIGGNDx pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs return to their previous values. The contents of the
input registers and DAC Register 0 to DAC Register 31 are not
affected by taking CLR low. To prevent glitches from appearing
on the outputs, CLR should be brought low whenever the output
span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can continue writing new data to the X1,
M, or C register (see the section for more
details), but no DAC output updates can take place.
Register Update Rates
The BUSY pin is bidirectional and has a 50 kΩ internal pull-up
resistor. When multiple AD5372 or AD5373 devices are used in
one system, the BUSY pins can be tied together. This is useful
when it is required that no DAC in any device be updated until
all other DACs are ready. When each device has finished updating
the X2 (A or B) registers, it releases the BUSY pin. If another
device has not finished updating its X2 registers, it holds BUSY
low, thus delaying the effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs are updated immediately after BUSY goes
high. A user can also hold the LDAC input permanently low. In
this case, the DAC outputs are updated immediately after BUSY
goes high. Whenever the A/B select registers are written to, BUSY
also goes low, for approximately 500 ns.
The AD5372/AD5373 have flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device. This means
that 1, 4, 8, or 32 DAC register values may need to be calculated
and updated. Because there is only one multiplier shared among
32 channels, this task must be done sequentially so that the
length of the BUSY pulse varies according to the number of
channels being updated.
Table 9. BUSY Pulse Widths
Action BUSY Pulse Width1
Loading input, C, or M to 1 channel2 1.5 μs maximum
Loading input, C, or M to 4 channels 3.3 μs maximum
Loading input, C, or M to 8 channels 5.7 μs maximum
Loading input, C, or M to 32 channels 20.1 μs maximum
1 BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
The AD5372/AD5373 contain an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with the
contents of the X2A or X2B register, depending on the setting of
the A/B select registers. However, the AD5372/AD5373 update
the DAC register only if the X2A or X2B data has changed,
thereby removing unnecessary digital crosstalk.
AD5372/AD5373
Rev. C | Page 20 of 28
POWER-DOWN MODE
The AD5372/AD5373 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGNDx potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5372/AD5373 can be programmed to shut down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 enables this function (see Table 16).
If the die temperature exceeds 130°C, the AD5372/AD5373 enter
a thermal shutdown mode, which is equivalent to setting the
power-down bit in the control register to 1. To indicate that the
AD5372/AD5373 have entered thermal shutdown mode, Bit 4
of the control register is set to 1. The AD5372/AD5373 remain
in thermal shutdown mode, even if the die temperature falls,
until Bit 1 in the control register is cleared to 0.
TOGGLE MODE
The AD5372/AD5373 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise need to
write to each channel individually. When the user writes to the
X1A, X1B, M, or C register, the calculation engine takes a certain
amount of time to calculate the appropriate X2A or X2B value.
If an application, such as a data generator, requires that the
DAC output switch between two levels only, any method that
reduces the amount of calculation time necessary is advanta-
geous. For the data generator example, the user needs only to
set the high and low levels for each channel once by writing to
the X1A and X1B registers. The values of X2A and X2B are
calculated and stored in their respective registers. The calculation
delay, therefore, happens only during the setup phase, that is,
when programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the relevant
A/B select register to set the MUX2 register bit. Furthermore,
because there are eight MUX2 control bits per register, it is
possible to update eight channels with a single write. Table 10
shows the bits that correspond to each DAC output.
Table 10. DACs Selected by A/B Select Registers
Bits
1
A/B Select
Register F7 F6 F5 F4 F3 F2 F1 F0
0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
1 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8
2 VOUT23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16
3 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24
1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected.
AD5372/AD5373
Rev. C | Page 21 of 28
SERIAL INTERFACE
The AD5372/AD5373 contain a high speed SPI operating at
clock frequencies up to 50 MHz (20 MHz for read operations).
To minimize both the power consumption of the device and
on-chip digital noise, the interface powers up fully only when
the device is being written to, that is, on the falling edge of
SYNC. The serial interface is 2.5 V LVTTL-compatible when
operating from a 2.5 V to 3.6 V DVCC supply. It is controlled by
four pins: SYNC (frame synchronization input), SDI (serial
data input pin), SCLK (clocks data in and out of the device),
and SDO (serial data output pin for data readback).
SPI WRITE MODE
The AD5372/AD5373 allow writing of data via the serial interface
to every register directly accessible to the serial interface, that is,
all registers except the X2A, X2B, and DAC registers. The X2A
and X2B registers are updated when writing to the X1A, X1B,
M, and C registers, and the DAC data registers are updated by
LDAC. The serial word (see or ) is 24 bits long:
16 (AD5372) or 14 (AD5373) of these bits are data bits; six bits
are address bits; and two bits are mode bits that determine what
is done with the data. Two bits are reserved on the AD5373.
Table 11 Table 12
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5372/AD5373 by clock pulses applied to SCLK. The first
falling edge of SYNC starts the write cycle. At least 24 falling
clock edges must be applied to SCLK to clock in 24 bits of data
before SYNC is taken high again. If SYNC is taken high before
the 24th falling clock edge, the write operation is aborted.
If a continuous clock is used,
SYNC
must be taken high before the
25th falling clock edge. This inhibits the clock within the AD5372/
AD5373. If more than 24 falling clock edges are applied before
SYNC is taken high again, the input data becomes corrupted. If
an externally gated clock of exactly 24 pulses is used, SYNC can
be taken high any time after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
SPI READBACK MODE
The AD5372/AD5373 allow data readback via the serial
interface from every register directly accessible to the serial
interface, that is, all registers except the X2A, X2B, and DAC
data registers. To read back a register, it is first necessary to tell
the AD5372/AD5373 which register is to be read. This is achieved
by writing a word whose first two bits are the Special Function
Code 00 to the device. The remaining bits then determine which
register is to be read back.
If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three-
stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See Figure 5 for the read timing diagram. Note that due to the
timing requirements of t22 (25 ns), the maximum speed of the
SPI interface during a read operation should not exceed 20 MHz.
REGISTER UPDATE RATES
The value of the X2A register or the X2B register is calculated
each time the user writes new data to the corresponding X1, C,
or M register. The calculation is performed by a three-stage
process. The first two stages take approximately 600 ns each, and
the third stage takes approximately 300 ns. When the write to an
X1, C, or M register is complete, the calculation process begins.
If the write operation involves the update of a single DAC
channel, the user is free to write to another register, provided
that the write operation does not finish until the first-stage
calculation is complete (that is, 600 ns after the completion of
the first write operation). If a group of channels is being updated
by a single write operation, the first-stage calculation is repeated
for each channel, taking 600 ns per channel. In this case, the
user should not complete the next write operation until this time
has elapsed.
Table 11. AD5372 Serial Word Bit Assignment
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 12. AD5373 Serial Word Bit Assignment
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11 I01
M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
1 Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.
AD5372/AD5373
Rev. C | Page 22 of 28
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, the data-word D15 to D0 (AD5372)
or D13 to D0 (AD5373) is written to the device. Address Bit A5
to Address Bit A0 determine which channels are written to, and
the mode bits determine to which register (X1A, X1B, C, or M)
the data is written, as shown in Table 13 and Table 14. Data is to
be written to the X1A register when the A/B bit in the control
register is 0, or to the X1B register when the A/B bit is 1.
The AD5372/AD5373 have very flexible addressing that allows
the writing of data to a single channel, all channels in a group,
the same channel in Group 0 to Group 3, the same channel in
Group 1 to Group 3, or all channels in the device. Table 14 shows
which groups and which channels are addressed for every
combination of Address Bit A5 to Address Bit A0.
Table 13. Mode Bits
M1 M0 Action
1 1 Write to DAC data (X) register
1 0 Write to DAC offset (C) register
0 1 Write to DAC gain (M) register
0 0 Special function, used in combination with other
bits of the data-word
Table 14. Group and Channel Addressing
Address Bit A5 to Address Bit A3
Address Bit A2
to Address Bit A0 000 001 010 011 100 101 110 111
000 All groups,
all channels
Group 0,
Channel 0
Group 1,
Channel 0
Group 2,
Channel 0
Group 3,
Channel 0
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 0
Group 1,
Group 2,
Group 3;
Channel 0
001 Group 0, all
channels
Group 0,
Channel 1
Group 1,
Channel 1
Group 2,
Channel 1
Group 3,
Channel 1
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 1
Group 1,
Group 2,
Group 3;
Channel 1
010 Group 1, all
channels
Group 0,
Channel 2
Group 1,
Channel 2
Group 2,
Channel 2
Group 3,
Channel 2
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 2
Group 1,
Group 2,
Group 3;
Channel 2
011 Group 2, all
channels
Group 0,
Channel 3
Group 1,
Channel 3
Group 2,
Channel 3
Group 3,
Channel 3
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 3
Group 1,
Group 2,
Group 3;
Channel 3
100 Group 3, all
channels
Group 0,
Channel 4
Group 1,
Channel 4
Group 2,
Channel 4
Group 3,
Channel 4
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 4
Group 1,
Group 2,
Group 3;
Channel 4
101 Reserved Group 0,
Channel 5
Group 1,
Channel 5
Group 2,
Channel 5
Group 3,
Channel 5
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 5
Group 1,
Group 2,
Group 3;
Channel 5
110 Reserved Group 0,
Channel 6
Group 1,
Channel 6
Group 2,
Channel 6
Group 3,
Channel 6
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 6
Group 1,
Group 2,
Group 3;
Channel 6
111 Reserved Group 0,
Channel 7
Group 1,
Channel 7
Group 2,
Channel 7
Group 3,
Channel 7
Reserved Group 0,
Group 1,
Group 2,
Group 3;
Channel 7
Group 1,
Group 2,
Group 3;
Channel 7