TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
TWO-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIER
Check for Samples: TAS5412-Q1
1FEATURES • TAS5412-Q1 - 64-Pin QFP (PHD) PowerPAD™
Surface-Mount Package
234• TAS5412-Q1 - Single-Ended Input • Pin Compatible With 4-Channel Devices
• 2-Channel Digital Power Amplifier • Designed for Automotive EMC Requirements
• 2 Analog Inputs, 2 BTL Power Outputs • Will Be Qualified According to AEC-Q100
• Typical Output Power per Channel at 10% • ISO9000:2002 TS16949 Certified
– 28 Watts/Ch, Into 4 Ωat 14.4 VDC • –40 to 105°C Ambient Temperature Range
– 46 Watts/Ch, Into 2 Ωat 14.4 VDC
– 79 Watts/Ch, Into 4 Ωat 24 VDC APPLICATIONS
– 150 Watts Into 2 Ωat 24 VDC PBTL • Radio Head Units
– 90 Watts Into 1 Ωat 14.4 VDC PBTL • External Amplifiers
• THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
• Patented Pop- and Click-Reduction DESCRIPTION
Technology The device is a two-channel digital audio amplifier
• Patented AM Interference Avoidance designed for use in automotive head units and
external amplifiers. It provides two channels at 28 W
• Patented Cycle-by-Cycle Current Limit into 4 Ωat 10% THD+N from 14.4 V or 46 W into 2 Ω
• 75-dB PSRR at 10% THD+N. The digital PWM topology provides
• Four-Address I2C Serial Interface for Device dramatic improvements in efficiency over traditional
Configuration and Control linear amplifier solutions. This reduces the power
dissipated by the amplifier by a factor of ten under
• Channel Gains: 12 dB, 20 dB, 26 dB, 32 dB typical music playback conditions. The device
• Load Diagnostic Functions: incorporates a patented PWM design that provides
– Output Open and Shorted Load excellent power-supply rejection in the harsh
electrical environment common in automotive
– Output-to-Power and -to-Ground Shorts applications. Applications attain high efficiency
– Patented Tweeter Detection without the need for complicated power supply
• Protection and Monitoring Functions: schemes. The design allows synchronization of
multiple devices.
– Short-Circuit Protection
– 50-V Load-Dump Protection The device incorporates all the functionality needed
to perform in the demanding OEM applications area,
– Fortuitous Open-Ground and -Power including load diagnostic functions for detecting and
Tolerant diagnosing misconnected outputs.
– Patented Output DC Level Detection While This text, unrelated to other data-sheet content, is
Music Is Playing intended only for adjusting column lengths on the first
– Overtemperature Protection page.
– Over- and Undervoltage Protection
– Clip Detection
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3Ceramique is a trademark of Arctic Silver Inc.
4Arctic Silver is a registered trademark of Arctic Silver Inc.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TAS5412-Q1 FUNCTIONAL BLOCK DIAGRAM
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments are as follows:
2Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19
16
20
17 21
18 22
36
44
45
46
47
48
35
43
34
42
33
41
32
40
31
39
30
38
29
37
28
27
2625
24
23
62 61
64 60
63 59 495051
5253
54
5556
57
58
OSC_SYNC
I2C_ADDR
SDA
SCL
FAULT
MUTE
GND
GND
GND
GND
GND
GND
GND
STANDBY
D_BYP
CLIP_OTW
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
REXT
A_BYP
CM_CAP1
IN2_P
IN_M
IN1_P
CM_CAP2
PVDD
PVDD
PVDD
NU
NU
GND
GND
OUT1_M
OUT1_P
CPC_TOP
CP
CP_BOT
GND
GND
GND
GND
GND
OUT2_M
OUT2_P
NU
GND
PVDD
GND
GND
GND
PVDD
NU
PVDD
P0070-03
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
TAS5412-Q1
PHD Package
(Top View)
Table 1. TERMINAL FUNCTIONS
TERMINAL TYPE DESCRIPTION
NAME NO.
A_BYP 11 PBY Bypass pin for the AVDD analog regulator
Reports clip detect, tweeter detection, and overtemperature warning with open-drain
CLIP_OTW 6 DO output
CM_CAP1 13 AI Common mode capacitor
CM_CAP2 20 AI Common mode capacitor
CP 41 CP Top of main storage capacitor for charge pump
CPC_BOT 40 CP Bottom of flying capacitor for charge pump
CPC_TOP 42 CP Top of flying capacitor for charge pump
D_BYP 5 PBY Bypass pin for DVDD regulator output
FAULT 1 DO Global fault output (open-drain): UV, OV, OTSD, OCSD, dc
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL TYPE DESCRIPTION
NAME NO.
3, 7-9, 12,14,
16, 17, 21–26,
GND 30–32, 35, 38, GND Ground
39, 43, 49–51,
55–60
I2C_ADDR 62 AI I2C address bit
IN1_P 15 AI Non-inverting analog input for channel 1
IN2_P 19 AI Non-inverting analog input for channel 2
IN_M 18 ARTN Signal return for both analog channel inputs
MUTE 2 DI Gain-ramp control
NU 33, 34, 47, 48 NC No connect, do not connect to ground
OSC_SYNC 61 DI, DO Oscillator input from master or output to slave amplifiers
OUT1_M 45 PO – polarity output for bridge 1
OUT1_P 44 PO + polarity output for bridge 1
OUT2_M 37 PO – polarity output for bridge 2
OUT2_P 36 PO + polarity output for bridge 2
PVDD 27–29, 52–54 PWR PVDD supply
REXT 10 AI Precision resistor pin to set analog reference
SCL 64 DI I2C clock input from system I2C master
SDA 63 DI, DO I2C data I/O for communication with system I2C master
STANDBY 4 DI Active-low STANDBY pin. Standby (low), power up (high)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
PVDD DC supply voltage range Relative to GND –0.3 to 30 V
PVDD MAX Pulsed supply-voltage range t ≤400 ms exposure –1 to 50 V
PVDD RAMP Supply-voltage ramp rate 15 V/ms
IPVDD Externally imposed dc supply current per PVDD or GND pin ±12 A
IPVDD_MAX Pulsed supply current per PVDD pin (one shot) t < 100 ms 17 A
IOMaximum allowed dc current per output pin ±13.5 A
IO_MAX (1) Pulsed output current per output pin (single pulse) t < 100 ms ±17 A
IIN_MAX Maximum current, all digital and analog input pins (2) DC or pulsed ±1 mA
IMUTE_MAX Maximum current on MUTE pin DC or pulsed ±20 mA
IIN_ODMAX Maximum sinking current for open-drain pins 7 mA
Input voltage range for logic pin relative to GND (SCL and
VLOGIC –0.3 to 6 V
SDA pins)
VI2C_ADDR Input voltage range for I2C_ADDR pin relative to GND –0.3 to 6 V
VSTANDBY Input voltage range for STANDBY pin –0.3 to 5.5 V
VOSC_SYNC Input voltage range for OSC_SYNC pin relative to GND –0.3 to 3.6 V
VAIN_AC_MAX_5412 Maximum ac-coupled input voltage(2), analog input pins 1.9 Vrms
VGND Maximum voltage between GND pins ±0.3 V
TJMaximum operating junction temperature range –55 to 150 °C
Tstg Storage temperature range –55 to 150 °C
(1) Pulsed-current ratings are maximum survivable currents externally applied to the TAS5412-Q1. Reverse-battery, fortuitous open-ground,
and fortuitous open-supply fault conditions may result in high currents.
(2) See Application Information section for information on analog input voltage and ac coupling.
4Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
THERMAL CHARACTERISTICS
PARAMETER VALUE (Typical) UNIT
RθJC Junction-to-case (heat slug) thermal resistance 1.7 °C/W
Exposed pad dimensions 8 × 8 mm
ELECTROSTATIC DISCHARGE (ESD)
PARAMETER PINS VALUE (Typical) UNIT
Human-body model (HBM) AEC- ALL 3000
Q100-002 Corner pins excluding SCL 750
Charged-device model (CDM) All pins (including SCL) except CP and CP_TOP 600 V
AEC-Q100-011 CP and CP_TOP pins 400
Machine model (MM) AEC-Q100- All 100
003
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
MIN NOM MAX UNIT
PVDDOP DC supply voltage range relative to GND 6 14.4 24 V
PVDDI2C 5 14.4 26.5 V
DC supply voltage range for I2C reporting
VAIN_5412 (2) Analog audio input signal level AC-coupled input voltage 0 0.25–1 (3) Vrms
TAAmbient temperature –40 105 °C
An adequate heat sink is required
TJJunction temperature –40 115 °C
to keep TJwithin specified range.
RLNominal speaker load impedance 2 4 Ω
VPU Pullup voltage supply (for open-drain logic outputs) 3 3.3 or 5 5.5 V
Resistor connected between open-
RPU_EXT External pullup resistor on open-drain logic outputs 10 47 100 kΩ
drain logic output and VPU supply
RPU_I2C 1 4.7 10 kΩ
I2C pullup resistance on SDA and SCL pins
Total resistance of voltage divider for I2C address
RI2C_ADD 10 100 kΩ
slave 1 or slave 2, connected between D_BYP and
GND pins
RREXT External resistance on REXT pin 1% tolerance required 19.8 20 20.2 kΩ
CD_BYP, CA_BYP External capacitance on D_BYP and A_BYP pins 10 120 nF
COUT External capacitnace to GND on OUT_X pins 150 680 nF
External capacitance to analog input pin in series
CIN 1 µF
with input signal
CFLY Flying capacitor on charge pump 0.47 1 1.5 µF
CPCharge-pump capacitor 50 V needed for load dump 0.47 1 1.5 µF
CMUTE Capacitance on MUTE pin 100 330 nF
COSCSYNC_MAX Allowed loading capacitance on OSC_SYNC pin 75 pF
(1) The Recommended Operating Conditionstable specifies only that the device is functional in the given range. See the Electrical
Characteristicstable for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.
6Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS= 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CURRENT
IPVDD_IDLE Both channels in MUTE mode 125 175
PVDD idle current mA
IPVDD_Hi-Z Both channels in Hi-Z mode 60
IPVDD_STBY PVDD standby current STANDBY mode, T J= 85°C 2 12 µA
OUTPUT POWER
4Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C 23
4Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C 25 28
4Ω, PVDD = 24 V, THD+N = 1%, 1 kHz, T c= 75°C 62
4Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, T c= 75°C 63 79
2Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C 38
POUT Output power per channel W
2Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C 40 50
PBTL 2-Ωoperation, PVDD = 24 V, THD+N = 10%, 150
1 kHz, T c= 75°C
PBTL 1-Ωoperation, PVDD = 14.4 V, THD+N = 10%, 90
1 kHz, T c= 75°C
2 channels operating, 23-W output power per ch, L = 10 %
EFFPPower efficiency 90
µH, T J= 85°C
AUDIO PERFORMANCE
VNOISE Noise voltage at output G = 26 dB, zero input, and A-weighting 60 100 µV
Crosstalk Channel crosstalk 1 W, G = 26 dB, 1 kHz 60 75 dB
PSRR Power-supply rejection ratio G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz 60 75 dB
THD+N Total harmonic distortion + noise P = 1 W, G = 26 dB, f = 1 kHz, 0°C = T J= 75°C 0.02% 0.1%
336 357 378
Switching frequency selectable for AM interference
fSSwitching frequency 392 417 442 kHz
avoidance 470 500 530
RAIN Analog input resistance Internal shunt resistance on each input pin 63 82 106 kΩ
AC-coupled common-mode input voltage (zero
VIN_CM Common-mode input voltage 1.3 Vrms
differential input)
VCM_INT Internal common-mode input bias voltage Internal bias applied to IN_M pin 3.37 V
11 12 13
19 20 21
Source impedance = 0 Ω, gain measurement taken at 1
G Voltage gain (VO/ VIN) dB
W of power per channel 25 26 27
31 32 33
GCH Channel-to-channel variation Any gain commanded –1 0 1 dB
PWM OUTPUT STAGE
rDSon FET drain-to-source resistance Not including bond-wire resistance, T J= 25°C 75 95 mΩ
Zero input signal, dc offset reduction enabled, and
VO_OFFSET Output offset voltage ±10 ±50 mV
G = 26 dB
PVDD OVERVOLTAGE (OV) PROTECTION
VOV PVDD overvoltage shutdown 24.6 26.4 28.2 V
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET PVDD undervoltage shutdown 5 5.3 5.6 V
VUV_CLEAR Recovery voltage for PVDD UV 6.2 6.6 7.2 V
AVDD
VA_BYP A_BYP pin voltage 6.5 V
VA_BYP_UV_SET A_BYP UV voltage 3.5 V
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV 4.3 V
DVDD
VD_BYP D_BYP pin voltage 3.3 V
POWER-ON RESET (POR)
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS= 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Maximum PVDD voltage for POR; I2C active
VPOR 4 V
above this voltage
VPOR_HY PVDD recovery hysteresis voltage for POR 0.1 V
REXT
VREXT Rext pin voltage 1.27 V
CHARGE PUMP (CP)
VCPUV_SET CP undervoltage 4.8 V
VCPUV_CLEAR Recovery voltage for CP UV 4.9 V
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR 96 112 128
TOTW1_SET/106 122 138
TOTW2_CLEAR Junction temperature for overtemperature
TOTW2_SET/warning 116 132 148
TOTW3_CLEAR °C
TOTW3_SET/126 142 158
TOTSD_CLEAR Junction temperature for overtemperature
TOTSD 136 152 168
shutdown
Junction temperature for overtemperature
TFB Per channel 130 150 170
foldback
CURRENT LIMITING PROTECTION
Level 1 5.5 7.3 9
ILIM Current limit (load current) A
Level 2 (default) 10.6 12.7 15
OVERCURRENT (OC) SHUTDOWN PROTECTION
Level 1, any short to supply, ground, or other channels 7.8 9.8 12.2
IMAX Maximum current (peak output current) A
Level 2 (default) 11.9 14.8 17.7
TWEETER DETECT
ITH_TW Load-current threshold for tweeter detect 330 445 560 mA
ILIM_TW Load-current limit for tweeter detect 2.1 A
STANDBY MODE
VIH_STBY STANDBY input voltage for logic-level high 2 V
VIL_STBY STANDBY input voltage for logic-level low 0.7 V
ISTBY_PIN STANDBY pin current 0.1 0.2 µA
MUTE MODE
GMUTE Output attenuation 100 dB
MUTE pin ≤0.5 Vdc for 200 ms, or I2C mute enabled
DC DETECT
VTH_DC_TOL DC-detect threshold tolerance 25%
DC-detect step-response time for two
tDCD 5.3 s
channels
CLIP REPORT
CLIP_OTW pin output voltage for logic level
VOH_CLIP_OTW 2.4 v
high (open-drain logic output) External 47-kΩpullup resistor to 3 V–5.5 V
CLIP_OTW pin output voltage for logic-level
VOL_CLIP_OTW 0.5 V
low (open-drain logic output)
TDELAY_CLIPDET Signal delay when output clipping detected 20 µs
MODE PINS (DIAG, SOFT_MUTE, I2C MODE)
Mode pin output voltage for logic-level high
VOH 2 5.5 V
(open-drain logic output)
Mode pin output voltage for logic-level low
VOL 0 0.7 V
(open-drain logic output)
FAULT REPORT
8Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS= 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FAULT pin output voltage for logic-level high
VOH_FAULT 2.4
(open-drain logic output) External 47-kΩpullup resistor to 3 V–5.5 V V
FAULT pin output voltage for logic-level low
VOL_FAULT 0.5
(open-drain logic output)
OPEN/SHORT DIAGNOSTICS
Maximum resistance to detect a short from
RS2P, RS2G 200 Ω
OUT pins to PVDD or ground
Minimum load resistance to detect open
ROPEN_LOAD Including speaker wires 300 800 1300 Ω
circuit
Maximum load resistance to detect short
RSHORTED_LOAD Including speaker wires 0.5 1.0 1.5 Ω
circuit
CHIP SELECT
tLATCH_CS 300 µs
Time delay to latch I2C address after POR
Voltage on CS pin for address 0 Connect to GND 0% 0% 15%
Voltage on CS pin for address 1 25% 35% 45%
External resistors in series between D_BYP and GND as
VCS VD_BYP
a voltage divider
Voltage on CS pin for address 2 55% 65% 75%
Voltage on CS pin for address 3 Connect to D_BYP 85% 100% 100%
I2C
Power-on hold time before I2C
tHOLD_I2C STANDBY high 1 ms
communication
fSCL SCL clock frequency 400 kHz
VIH_SCL SCL pin input voltage for logic-level high 2.1 5.5 V
RPU_I2C= 5-kΩpullup, supply voltage = 3.3 V or 5 V
VIL_SCL SCL pin input voltage for logic-level low –0.5 1.1 V
I2C read, RI2C= 5-kΩpullup,
VOH_SDA SDA pin output voltage for logic-level high 2.4 V
supply voltage = 3.3 V or 5 V
VOL_SDA SDA pin output voltage for logic-level low 0.4 V
I2C read, 3-mA sink current
I2C write, RI2C= 5-kΩpullup,
VIH_SDA SDA pin input voltage for logic-level high 2.1 5.5 V
supply voltage = 3.3 V or 5 V
I2C write, RI2C= 5-kΩpullup,
VIL_SDA SDA pin input voltage for logic-level low –0.5 1.1 V
supply voltage = 3.3 V or 5 V
CiCapacitance for SCL and SDA pins 10 pF
OSCILLATOR
OSC_SYNC pin output voltage for logic-
VOH_OSCSYNC 2.4 3.6 V
level high CS pin set to MASTER mode
OSC_SYNC pin output voltage for logic-
VOL_OSCSYNC 0.5 V
level low
OSC_SYNC pin input voltage for logic-level
VIH_OSCSYNC 2 3.6 V
high CS pin set to SLAVE mode
OSC_SYNC pin input voltage for logic-level
VIL_OSCSYNC 0.8 V
low
CS pin set to MASTER mode, fS= 500 kHz 3.76 4 4.24
fOSC_SYNC OSC_SYNC pin clock frequency CS pin set to MASTER mode, fS= 417 kHz 3.13 3.33 3.63 MHz
CS pin set to MASTER mode, fS= 357 kHz 2.68 2.85 3
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TAS5412-Q1
SCL
SDA
th2 t(buf)
tsu2 tsu3
Start
Condition
Stop
Condition
T0028-01
SCL
SDA
tw(H) tw(L) trtf
tsu1 th1
T0027-01
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
trRise time for both SDA and SCL signals 300 ns
tfFall time for both SDA and SCL signals 300 ns
tw(H) SCL pulse duration, high 0.6 µs
tw(L) SCL pulse duration, low 1.3 µs
tsu2 Setup time for START condition 0.6 µs
th2 START condition hold time after which first clock pulse is generated 0.6 µs
tsu1 Data setup time 100 ns
th1 Data hold time 0 (1) ns
tsu3 Setup time for STOP condition 0.6 µs
CBLoad capacitance for each bus line 400 pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
Figure 1. SCL and SDA Timing
Figure 2. Timing for Start and Stop Conditions
10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
TYPICAL CHARACTERISTICS
THD+N THD+N
versus versus
BTL OUTPUT POWER AT 1 kHz PBTL OUTPUT POWER at 1 kHz
Figure 3. Figure 4.
THD+N COMMON-MODE REJECTION RATIO
versus versus
FREQUENCY AT 1 W FREQUENCY
Figure 5. Figure 6.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TAS5412-Q1
P − Power Per Channel − W
0
10
20
30
40
50
60
70
80
90
100
0 4 8 12 16 20 24 28 32
Efficiency − %
G007
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CROSSTALK
versus
FREQUENCY NOISE FFT
Figure 7. Figure 8.
EFFICIENCY,
TWO CHANNELS AT 4 ΩEACH
Figure 9.
12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
DESCRIPTION OF OPERATION
OVERVIEW
The device is a two-channel analog-input audio amplifier for use in the automotive environment. The design uses
an ultra-efficient class-D technology developed by Texas Instruments. This technology allows for reduced power
consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio
sound system design with smaller size and lower weight than traditional class-AB solutions.
The device has the following major blocks:
• Preamplifier
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
Preamplifier
The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The
high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency
response. A dedicated, internally regulated supply powers the preamplifier, giving excellent noise immunity and
channel separation. Also included in the preamplifier are:
1. Mute Pop-and-Click Control—Application of a mute at the crest or trough of an audio input signal reshapes
and amplifies the signal as a step. Listeners perceive such a step as a loud click. The TAS5412-Q1 avoids
clicks by ramping the gain gradually on reception of a mute or play command. The start or stopping of
switching in a class-D amplifier can cause another form of click and pop. The TAS5412-Q1 incorporates a
patented method to reduce the pop energy during the switching start-up and shutdown sequences. Fault
conditions require rapid protection response by the TAS5412-Q1, which does not have time to ramp the gain
down in a pop-free manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or dc fault is
encountered. Also, activation of the STANDBY pin may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. Setting of the gain
outside of the global feedback resistors of the TAS5412-Q1 thus allows for stability in the system at all gain
settings with properly loaded conditions.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5412-Q1, the modulator is an advanced design
with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation capability. The
patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of PWMs when the
input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage.
Power FETs
The BTL output for each channel comprises four rugged N-channel FETs, each of which is low rDSon for high
efficiency and maximum power transfer to the load. These FETs handle large voltage transients during load
dump.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TAS5412-Q1
OUT1_M
OUT1_P
V
(OUT1_P – OUT1_M)
Speaker
Playback
/
Mute
Hi-Z Channel Synchronization
Phase1 Phase2 Phase3 Phase4
S2G
20 ms
<20 ms
S2P
20 ms
OL
150 ms
SL
200 ms
~50 ms ~50 ms
~50 ms
~50 ms
~50 ms ~50 ms
~50 ms
~50 ms
T0188-01
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Load Diagnostics
The device incorporates load-diagnostic circuitry designed to help pinpoint the nature of output misconnections
during installation. The diagnostics include functions for detecting and determining the status of output
connections. The following diagnostics are supported:
• Short to GND
• Short to PVDD
• Short across load
• Open load
• Tweeter detection
Reporting the presence of any of the short or open conditions to the system is via I2C register read. One can
read the tweeter detect status from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open
conditions on the outputs. One can only invoke the load diagnostic function when the output is in the Hi-Z
mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all
channels must be in the Hi-Z state. The diagnostic tests all four phases on each channel, and both channels
at the same time. When fewer than two channels are in Hi-Z, the reduced level of test is the only available
option. In the reduced level, the only available tests are short to PVDD and short to GND. Load diagnostics
can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play
mode, it must Mute and then Hi-Z to allow performing the load diagnostic. By performing the mute function,
the normal pop- and click-free transitions occur before the diagnostics begin. The device performs the
diagnostics as shown in Figure 10.Figure 11 shows the impedance ranges for the open-load and shorted-
load diagnostics. Reading of the diagnostic results is from the diagnostic register for each channel via I2C.
Figure 10. Load Diagnostics Sequence of Events
14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
ShortDetected OpenDetectedNormalLoadDetected
ShortDetection
Range
OpenDetection
Range
0.5 300
1.5 1300
1(Typ) 800(Typ)
R
(IncludingWires)
Load
M0067-01
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Figure 11. Open- and Shorted-Load Detection
2. Tweeter Detection—Tweeter detection is an alternate operating mode used to determine the proper
connection of a frequency-dependent load (such as a speaker with a crossover). Invocation of tweeter
detection is via I2C, and both channels should be tested individually. Tweeter detection uses the average
cycle-by-cycle current-limit circuit (see the CBC section) to measure the current delivered to the load. The
proper implementation of this diagnostic function depends on the amplitude of a user-supplied test signal and
on the impedance-versus-frequency curve of the acoustic load. The system (external to the device) must
generate a signal to which the load responds. The user must calibrate the frequency and amplitude of this
signal to result in a current draw that is greater than the tweeter detection threshold when the load under test
is present, and less than the detection threshold if the load is not properly connected. The current level for
the tweeter detection threshold, as well as the maximum current that can safely be delivered to a load when
in tweeter-detection mode, is in the Electrical Characteristics section of the datasheet. The tweeter-detection
results are available on the CLIP_OTW pin during the application of the test signal. During tweeter-detection
activation (when the tested load is present), pulses on the CLIP_OTW pin begin to toggle. The pulses on the
CLIP_OTW pin report low whenever the current exceeds the detection threshold, and the pin remains low
until the current no longer exceeds the threshold. The minimum low-pulse period that one can expect is
equal to one period of the switching frequency. Having an input signal that increases the duration of detector
activation (for example, increasing the amplitude of the input signal) increases the amount of time for which
the pin reports low.
NOTE: Because tweeter detection is an alternate operating mode, it is necessary to place the channels to be
tested in Play mode (via register 0x0C) after activation of tweeter detection in order to commence the
detection process. Additionally, the appropriate settings must be in register 0x0A, enabling the CLIP_OTW to
report the results of tweeter detection.
Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC)—The CBC current-limiting circuit terminates each PWM pulse to limit
the output-current flow when current exceeds the average current-limit (ILIM) threshold. The overall effect on
the audio in the case of a current overload is quite similar to a voltage-clipping event, where the device
temporarily limits power at the peaks of the musical signal and normal operation continues without disruption
on removal of the overload. The TAS5412-Q1 does not prematurely shut down in this condition. Both
channels continue in play mode and pass signal.
2. Overcurrent Shutdown (OCSD)—Under severe short-circuit events, such as a short to PVDD or ground,
the device uses a peak-current detector, and the affected channel shuts down in 200 µs to 390 µs if the
conditions are severe enough. The shutdown speed depends on a number of factors, such as the impedance
of the short circuit, supply voltage, and switching frequency. Only the shorted channels shut down in such a
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
scenario. The user may restart the affected channel via I2C. An OCSD event activates the fault pin, with the
I2C fault register recording the affected channels. If the supply or ground short is strong enough to exceed
the peak current threshold but not severe enough to trigger the OCSD, the peak current limiter prevents
excess current from damaging the output FETs, and operation returns to normal after the short is removed.
3. DC Detect—This circuit detects a dc offset continuously during normal operation at the output of the
amplifier. If the dc offset reaches the level defined in the I2C registers for the specified time period, the circuit
triggers. By default, a dc detection event does not shut the output down. One can enable or disable the
shutdown function via I2C. If enabled, the triggered channel shuts down, but the others remain playing, and
the device asserts the FAULT pin. The I2C registers define the dc level.
4. Clip Detect—The clip-detect circuit alerts the user to the presence of a 100% duty-cycle PWM due to a
clipped waveform. When this occurs, the device passes to the CLIP_OTW pin a signal that remains asserted
until the 100% duty-cycle PWM signal is no longer present. Through I2C, one can change the CLIP_OTW
signal to clip-only, OTW-only, or both. A fourth mode, used only during diagnostics, is the option to report
detected tweeter-detection events on these pins (see the Tweeter Detection section). The microcontroller in
the system can monitor the signal at the CLIP_OTW pin. The microcontroller configuration may be such as to
reduce the volume on the channel in an active clipping-prevention circuit.
5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD), and Thermal Foldback—The
device asserts the CLIP_OTW pin when the die temperature reaches 125°C. The OTW has three
temperature thresholds with a 10°C hysteresis. Indication of the thresholds is in I2C register 0x04 bits 5, 6,
and 7. The device still functions until the temperature reaches the OTSD threshold, 155°C, at which time it
places the outputs into Hi-Z mode and asserts the FAULT pin. I2C is still active in the event of an OTSD,
which allows reading the registers for faults, but all audio ceases abruptly. The OTSD resets at 145°C, to
allow the turning the TAS5412-Q1 back on through I2C. The OTW indication persists until the temperature
drops below 115°C. All temperatures are nominal values. The thermal foldback decreases the channel gain.
6. Undervoltage (UV) and Power-On Reset (POR)—The undervoltage (UV) protection detects low voltages
on PVDD, AVDD, and CP. In the event of an undervoltage, the device asserts the FAULT pin and updates
the I2C register for the voltage which caused the event. Power-on-reset (POR) occurs when PVDD drops low
enough. A POR event causes the I2C to go into a high-impedance state. After the device recovers from the
POR event, re-initialization of the device via I2C is necessary.
7. Overvoltage (OV) and Load Dump—The OV protection detects high voltages on PVDD. If PVDD reaches
the overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. If the voltage
increases beyond the load dump threshold of 29 Vdc, the device shuts down and must undergo a restart
once the voltage returns to a safe value. After the device recovers from a load-dump event, the device
requires re-initialization via I2C. The TAS5412-Q1 can withstand 50-V load-dump voltage spikes. Load
Diagnostics shows the regions of operating voltage and the profile of the load-dump event.
Power Supply
A car battery that can have a large voltage swing most commonly provides the power for the device. PVDD is a
filtered battery voltage, and is the supply for the output FETS and the low-side FET gate driver. A charge pump
(CP) supply provides power to the high-side FET gate driver. The charge pump supplies the gate-drive voltages.
AVDD, which comes from an internal linear regulator, powers the analog circuitry. This supply requires a 0.1-µF,
10-V external bypass capacitor at the A_BYP pin. TI recommends attaching no external components except the
bypass capacitor to this pin. DVDD, which comes from an internal linear regulator, powers the digital circuitry.
The D_BYP pin requires a 0.1-µF, 10-V external bypass capacitor. TI recommends that no external components
except the bypass capacitor be attached to this pin.
The device can withstand fortuitous open-ground and -power conditions. Fortuitous open-ground usually occurs
when a speaker wire is shorted to ground, allowing for a second ground path through the body diode in the
output FETs. The uniqueness of the diagnostic capabilities allows debugging of the speakers and speaker wires,
eliminating the need to remove the amplifier to diagnose the problem.
I2C Serial Communication Bus
The device communicates with the system processor via the I2C serial communication bus. It is an I2C slave-only
device. The processor can poll the device via I2C to determine the operating status. Reporting of all fault
conditions and detections is via I2C. The setting of numerous features and operating conditions is also via I2C.
The I2C bus allows control of the following configurations:
• Control the gain each channel independently. The gain settings are 12 dB, 20 dB, 26 dB, and 32 dB.
16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
• Select AM non-interference switching frequency
• Configure the CLIP_OTW pin
• Enable or disable the dc-detect function with selectable threshold
• Place channel in Hi-Z (switching stopped) mode (mute)
• Select tweeter detect, set detect threshold, and initiate function
• Initiate open- and shorted-load diagnostic
• Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the device includes a single pin that allows up to
four devices to work together in a system with no additional hardware required for communication or
synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the I2C address for that
device. Tie I2C_ADDR to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2, and to D_BYP for
slave 3. The OSC_SYNC pin synchronizes the internal clock oscillators and thereby avoids beat frequencies.
Optional application of an external oscillator to this pin allows external control of the switching frequency.
Table 2. I2C_ADDR Pin Connection
DESCRIPTION I2C_ADDR PIN CONNECTION I2C ADDRESS
Device 0 - OSC_SYNC clock master To SGND pin 0xD8/D9
Device 1 - OSC_SYNC clock slave 1 35% DVDD (resistive voltage divider between D_BYP pin and SGND pin) (1) 0xDA/DB
Device 2 - OSC_SYNC clock slave 2 65% DVDD (resistive voltage divider between D_BYP pin and SGND pin) (1) 0xDC/DD
Device 3 - OSC_SYNC clock slave 3 To D_BYP pin 0xDE/DF
(1) RCSwith 5% or better tolerance is recommended.
I2C Bus Protocol
The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only
device that does not support a multimaster bus environment or wait-state insertion. Use the control interface to
program the registers of the device and to read device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The address and data transfers are in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data terminal (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-
to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. Figure 12 shows these conditions. The master
generates the 7-bit slave address and the read/write bit to open communication with another device and then
wait for an acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate
an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Addressing of each
device is by a unique 7-bit slave address plus read/write bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. There must be an external pullup resistor for the
SDA and SCL signals to set the HIGH level for the bus. There is no limit on the number of bytes comprising a
transmission between start and stop conditions. When the last word transfers, the master generates a stop
condition to release the bus.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TAS5412-Q1
D7 D0 ACK
Stop
Condition
Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress LastDataByte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition Acknowledge Acknowledge Acknowledge
FirstDataByte
A4 A3A6
OtherDataBytes
ACK
Acknowledge
D0 D7 D0
T0036-02
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
T0036-01
7-BitSlave Address R/
W8-BitRegister Address(N)
A8-BitRegisterDataFor
Address(N)
Start Stop
SDA
SCL
765432 1 0765432 1 0765432 1 0765432 1 0
A8-BitRegisterDataFor
Address(N)
A A
T0035-01
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Figure 12. Typical I2C Sequence
Use the CS pin (pin 62) to program the device for one of four addresses. These four addresses are licensed I2C
addresses and do not conflict with other licensed I2C audio devices. To communicate with the device, the I2C
master uses addresses shown in Table 2. Read and write data transmissions can use single-byte or multiple-
byte data transfers.
Random Write
As shown in Figure 13, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address
and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte
or bytes corresponding to the internal memory address being accessed. After receiving the address byte, the
device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to
the memory address being accessed. After receiving the data byte, the device again responds with an
acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write
transfer.
Figure 13. Random Write Transfer
Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data
bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and
the I2C subaddress automatically increments by one.
Figure 14. Sequential Write Transfer
18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
A6 A0 ACK
Acknowledge
I CDevice Addressand
Read/WriteBit
2
R/WA6 A0 R/W ACK A0 ACK D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition Not
Acknowledge
I CDevice Addressand
Read/WriteBit
2Subaddress OtherDataBytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0036-04
A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I CDevice Addressand
2
Read/WriteBit
Subaddress DataByte
D7 D6 D1 D0 ACK
I CDevice Addressand
Read/WriteBit
2
Not
Acknowledge
R/WA1 A1
RepeatStart
Condition
T0036-03
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data
bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and
the I2C subaddress automatically increments by one.
Random Read
As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The data-read transfer actually performs a
write followed by a read. Initially, a write transfers the address byte or bytes of the internal memory address to be
read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds
with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the device address and the read/write bit again. This time the
read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again
responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being
read. After receiving the data byte, the master transmits a not-acknowledge followed by a stop condition to
complete the single-byte data-read transfer.
Figure 15. Random Read Transfer
Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that the device transmits
multiple data bytes to the master as shown in Figure 16. Except for the last data byte, the master responds with
an acknowledge bit after receiving each data byte and automatically increments the I2C subaddress by one.
Note: The fault registers do not have sequential read capabilities.
Figure 16. Sequential Read Transfer
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
A sequential data-write transfer is identical to a single-byte data-write transfer except that the master transmits multiple data
bytes to the device as shown in Figure 14. After receiving each data byte, the device responds with an acknowledge bit, and
the I2C subaddress automatically increments by one.
Table 3. TAS5412-Q1 I2C Addresses
SELECTABLE WITH READ/WRITE
FIXED ADDRESS I2C
ADDRESS PIN BIT
DESCRIPTION ADDRESS
MSB 6 5 4 3 2 1 LSB
0 – OSC MASTER I2C WRITE 1 1 0 1 1 0 0 0 0xD8
I2C READ 1 1 0 1 1 0 0 1 0xD9
1 – OSC SLAVE1 I2C WRITE 1 1 0 1 1 0 1 0 0xDA
I2C READ 1 1 0 1 1 0 1 1 0xDB
2 – OSC SLAVE2 I2C WRITE 1 1 0 1 1 1 0 0 0xDC
I2C READ 1 1 0 1 1 1 0 1 0xDD
3 – OSC SLAVE3 I2C WRITE 1 1 0 1 1 1 1 0 0xDE
I2C READ 1 1 0 1 1 1 1 1 0xDF
Table 4. I2C Address Register Definitions
ADDRESS TYPE REGISTER DESCRIPTION
0x00 Read Latched fault register 1, global and channel fault
0x01 Read Latched fault register 2, dc offset and overcurrent detect
0x02 Read Latched diagnostic register 1, load diagnostics, channel 1
0x03 Read Latched diagnostic register 2, load diagnostics, channel 2
0x04 Read External status register 1, temperature and voltage detect
0x05 Read External status register 2, Hi-Z and low-low state
0x06 Read External status register 3, mute and play modes
0x07 Read External status register 4, load diagnostics
0x08 Read, Write External control register 1, channel gain select
0x09 Read, Write Not used
0x0A Read, Write External control register 2, switching frequency and clip pin select
0x0B Read, Write External control register 3, load diagnostic, master mode select
0x0C Read, Write External control register 4, output state control
0x0D Read, Write External control register 5, output state control
0x0E Read, Write Not used
0x0F Read, Write Not used
0x10 Read, Write External control register 6, dc detect threshold selection
0x13 Read External status register 5, overtemperature shutdown and thermal foldback
Table 5. Fault Register 1 (0x00) Protection
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No protection-created faults, default value
– – – – – – – 1 Overtemperature warning has occurred
– – – – – – 1 – DC offset has occurred in any channel
– – – – – 1 – – Overcurrent shutdown has occurred in any channel
– – – – 1 – – – Overtemperature shutdown has occurred
– – – 1 – – – – Charge-pump undervoltage has occurred
– – 1 – – – – – AVDD, analog voltage, undervoltage has occurred
– 1 – – – – – – PVDD undervoltage has occurred
1 – – – – – – – PVDD overvoltage has occurred
20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Table 6. Fault Register 2 (0x01) Protection
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No protection-created faults, default value
– – – – – – 1 – Ovecurrent shutdown channel 1 has occurred
– – – – – 1 – – Overcurrent shutdown channel 2 has occurred
– – 1 – – – – – DC offset channel 1 has occurred
– 1 – – – – – – DC offset channel 2 has occurred
X – – X X – – X Reserved
Table 7. Diagnostic Register 1 (0x02) Load Diagnostics
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No load-diagnostic-created faults, default value
– – – 1 – – – – Output short to ground channel 1 has occurred
– – 1 – – – – – Output short to PVDD channel 1 has occurred
– 1 – – – – – – Shorted load channel 1 has occurred
1 – – – – – – – Open load channel 1 has occurred
– – – – X X X X Reserved
Table 8. Diagnostic Register 2(0x03) Load Diagnostics
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No load-diagnostic-created faults, default value
– – – – – – – 1 Output short to ground channel 2 has occurred
– – – – – – 1 – Output short to PVDD channel 2 has occurred
– – – – – 1 – – Shorted load channel 2 has occurred
– – – – 1 – – – Open load channel 2 has occurred
X X X X – – – – Reserved
Table 9. External Status Register 1 (0x04) Fault Detection
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No protection-created faults are present, default value
– – – – – – – 1 PVDD overvoltage fault is present
– – – – – – 1 – PVDD undervoltage fault is present
– – – – – 1 – – AVDD, analog voltage fault is present
– – – – 1 – – – Charge-pump voltage fault is present
– – – 1 – – – – Overtemperature shutdown is present
– – 1 – – – – – Overtemperature warning
– 1 1 – – – – – Overtemperature warning level 1
1 0 1 – – – – – Overtemperature warning level 2
1 1 1 – – – – – Overtemperature warning level 3
Table 10. External Status Register 2 (0x05) Output State of Individual Channels
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 1 1 0 Output is in Hi-Z mode, not in low-low mode (1), default value
– – – – – – 0 – Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
– – – – – 0 – – Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
– – 1 – – – – – Channel 1 low-low mode (0 = not low-low, 1 = low-low) (1)
– 1 – – – – – – Channel 2 low-low mode (0 = not low-low, 1 = low-low) (1)
X – – X X – – X Reserved
(1) Low-low is defined as both outputs actively pulled to ground.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Table 11. External Status Register 3 (0x06) Play and Mute Modes
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Mute mode is disabled, play mode disabled, default value, (Hi-Z mode)
– – – – – – 1 – Channel 1 is in play mode.
– – – – – 1 – – Channel 2 is in play mode.
– – 1 – – – – – Channel 1 is in mute mode.
– 1 – – – – – – Channel 2 is in mute mode.
X – – X X – – X Reserved
Table 12. External Status Register 4 (0x07) Load Diagnostics
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No channels are set in load diagnostics mode, default value
– – – – – – 1 – Channel 1 is in load diagnostics mode.
– – – – – 1 – – Channel 2 is in load diagnostics mode.
– – 1 – – – – – Channel 1 is in overtemperature foldback.
– 1 – – – – – – Channel 2 is in overtemperature foldback.
X – – X X – – X Reserved
Table 13. External Control Register 1 (0x08) Gain Select
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 0 1 0 1 0 1 0 Set gain for both channels to 26 dB, default value
– – – – 0 0 – – Set channel 1 gain to 12 dB
– – – – 0 1 – – Set channel 1 gain to 20 dB
– – – – 1 1 – – Set channel 1 gain to 32 dB
– – 0 0 – – – – Set channel 2 gain to 12 dB
– – 0 1 – – – – Set channel 2 gain to 20 dB
– – 1 1 – – – – Set channel 2 gain to 32 dB
X X – – – – X X Reserved
Table 14. External Control Register 2 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 1 1 0 1 Set f S= 417 kHz, configure clip and OTW detection, 45° phase, disable
hard stop
– – – – – – 0 0 Set f S= 500 kHz
– – – – – – 1 0 Set f S= 357 kHz
– – – – – – 1 1 Invalid frequency selection (do not set)
– – – – 0 0 – – Configure CLIP_OTW pin for tweeter detect only
– – – – 0 1 – – Configure CLIP_OTW pin for clip detect only
– – – – 1 0 – – Configure CLIP_OTW pin for overtemperature warning only
– – – 1 – – – – Enable hard-stop mode
– – 1 – – – – – Set fSto a 180° phase difference between adjacent channels
– 1 – – – – – – Send sync pulse from OSC_SYNC pin (device must be in master mode).
1 – – – – – – – Report thermal foldback to the CLIP_OTW pin.
Table 15. External Control Register 3 (0x0B) Load Diagnostics and Master-or-Slave Control
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 0 1 0 0 0 0 Disable load diagnostics, enable dc-detect SD, master mode
– – – – – – 1 – Enable channel 1, load diagnostics
– – – – – 1 – – Enable channel 2, load diagnostics
22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Table 15. External Control Register 3 (0x0B) Load Diagnostics and Master-or-Slave Control (continued)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– – – – X – – X Reserved
– – – 0 – – – – Disable dc detect shutdown on all channels
– – 1 – – – – – Enable tweeter-detect mode
– 0 – – – – – – Enable slave mode (provide external oscillator)
1 – – – – – – – Send clock, OSC_SYNC pin has clock output (valid only in master mode)
Table 16. External Control Register 4 (0x0C) Output Control
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 1 1 1 1 1 All channels, Hi-Z, mute, reset disabled
– – – – – – 0 – Set channel 1 to mute mode, non-Hi-Z
– – – – – 0 – – Set channel 2 to mute mode, non-Hi-Z
– X X – X – – X Reserved
– – – 0 – – – – Set non-Hi-Z channels to play mode, (unmute)
1 – – – – – – – Reset device
Table 17. External Control Register 5 (0x0D) Output Control
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Low-low state disabled, both channels
– – – – – – 1 – Set channel 1 to low-low state
– – – – – 1 – – Set channel 2 to low-low state
X X X X X – – X Reserved
Table 18. External Control Register 6 (0x10) DC Detect Threshold Selection
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 1 Default dc detect value (1.6 V)
– – – – – – 0 0 Minimum dc detect value (0.8 V)
– – – – – – 1 0 Maximum dc detect value (2.4 V) Note: a value of 11 is invalid
– – – – – 1 – – Enable enhanced-crosstalk mode
– – – – 1 – – – Add a 20-ms delay between load diagnostic phases
– – – 1 – – – – 4× longer short-to-power (S2P) and short-to-ground (S2G) phases
1 – – – – – – – Slower common mode (CM) ramp-down from mute mode
– X X – – – – – Reserved
Table 19. External Status Register 5 (0x13) Overtemperature and Thermal Foldback Status
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 Default overtemperature foldback status, no channel is in foldback
– – – – – – 1 – Channel 1 in thermal foldback
– – – – – 1 – – Channel 2 in thermal foldback
– – 1 – – – – – Channel 1 in overtemperature shutdown
– 1 – – – – – – Channel 2 in overtemperature shutdown
X – – X X – – X Reserved
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Hardware Control Pins
The device has several hardware pins for real-time control and indication of device status.
FAULT pin: This active-low, open-drain output pin indicates the presence of a fault condition that requires
the device to go automatically into the Hi-Z mode or standby mode. When asserting this pin high, the device
is protecting itself and the system from potential damage. One can read the exact nature of the fault via I2C,
with the exception of faults that are the result of PVDD voltage excursions below POR. In this case, the
device goes into standby mode and the I2C bus is no longer operational. However, the fault indication
remains, due to the fact that the FAULT pin is open-drain and active-high.
CLIP_OTW pin: The function of this active-low pin, configured by the user, indicates one of the following
conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.
Selection of the configuration is via I2C. During tweeter-detect diagnostics, detection of a tweeter also results
in assertion of this pin.
MUTE pin: This active-low pin is for hardware control of the mute-and-unmute function for all four channels.
Capacitor CMUTE controls the time constant for the gain ramp needed to produce a pop- and click-free mute
function. For pop- and click-free operation, implement the mute function through I2C commands. The use of a
hard mute with an external transistor does not ensure pop- and click-free operation; TI does not recommend
such use unless there is a requirement for an emergency hard mute function in case of a loss of I2C control.
Do not share the CMUTE capacitor between more than one device.
STANDBY pin: Asserting this active-low pin puts the device into a complete shutdown, limiting the current
draw to 2 µA, typical. Assertion typically occurs when the car ignition is in the off position. Another use of the
pin is to shut down the device rapidly on violation of certain operating conditions. Pin assertion causes the
loss of all I2C register content and causes the I2C bus to go into the high-impedance state.
EMI Considerations
Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) is a major consideration in all aspects of the
TAS5412-Q1 design.
The TAS5412-Q1 has minimal parasitic inductances due to the short leads on the PHD package. This
dramatically reduces the EMI that results from current passing from the die to the system PCB. Each channel of
the TAS5412-Q1 also operates at a different phase. The phase between channels is I2C selectable to either 45°
or 180°, to reduce EMI caused by high-current switching. The TAS5412-Q1 incorporates patent-pending circuitry
that optimizes output transitions that cause EMI.
AM Radio EMI Reduction
To reduce interference in the AM radio band, the TAS5412-Q1 has the ability to change the switching frequency
via I2C commands. Table 20 lists the recommended frequencies. The fundamental frequency and its second
harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching
frequency being demodulated by the AM radio. To function properly, AM avoidance requires the use of a 20-kΩ,
1% tolerance Rext resistor.
Table 20. Recommended Switching Frequencies for AM Mode Operation
US EUROPEAN
SWITCHING SWITCHING
AM FREQUENCY AM FREQUENCY
FREQUENCY FREQUENCY
(kHz) (kHz)
(kHz) (kHz)
522-540 417
540–917 500 540–914 500
917–1125 417 914–1122 417
1125–1375 500 1122–1373 500
1375–1547 417 1373–1548 417
1547–1700 357 1548–1701 357
24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Operating States
the following tables depict the operating regions, or states, of the TAS5412-Q1.
Table 21. Operating States and Supplies
STATE NAME OUTPUT FETS CHARGE PUMP OSCILLATOR I2C AVDD and DVDD
STANDBY Hi-Z, floating Stopped Stopped Stopped OFF
Hi-Z Hi-Z, weak pulldown Active Active Active ON
Mute Switching at 50% Active Active Active ON
Normal operation Switching with audio Active Active Active ON
Table 22. Global Faults and Actions
FAULT OR LATCHED/
FAULT OR MONITORING REPORTING ACTION ACTION
EVENT SELF-
EVENT MODES METHOD TYPE RESULT
CATEGORY CLEARING
POR Voltage fault All FAULT pin Hard mute (no ramp) Standby Self-clearing
Undervoltage Hi-Z, mute, normal I2C + FAULT pin Hi-Z Latched
Overvoltage
Overtemperatu Thermal warning Hi-Z, mute, normal I2C + OTW pin None None Self-clearing
re warning
Overtemperatu Thermal fault Hi-Z, mute, normal I2C + FAULT pin Hard mute (no ramp) Standby Latched
re shutdown
Table 23. Channel Faults and Actions
LATCHED or
FAULT OR FAULT OR EVENT MONITORING REPORTING ACTION ACTION SELF-
EVENT CATEGORY MODES METHOD TYPE RESULT CLEARING
Open/short Diagnostic Hi-Z (I2C activated) I2C None None Latched
diagnostic
Output clipping Warning Mute or play CLIP_OTW pin None None Self-clearing
CBC load current Online protection Current limit Start OC Self-clearing
limit timer
OC fault Output channel fault I2C + FAULT pin Hard mute Hi-Z Latched
DC detect Hard mute Hi-Z Latched
OT foldback Warning I2C + OTW pin Current limit None Self-clearing
Power Shutdown and Restart Sequence Control
The gain ramp of the filtered output signal and the updating of the I2C registers correspond to the MUTE pin
voltage during the ramping process. The value of the external capacitor on the MUTE pin dictates the length of
time that the MUTE pin takes to complete its ramp.
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TAS5412-Q1
MUTE Pin
PLAY_Report_x
HIZ_Report_x
(All Channels)
LOW_LOW_Report_x
(All Channels)
MUTE_Report_x
(All Channels)
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
tGAIN tGAIN
tCM tCM
T0192-02
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Figure 17. Click- and Pop-Free Shutdown and Restart Sequence Timing Diagram
With Two Channels Sharing the Mute Pin
26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
T0193-02
HIZ_Report_1
HIZ_Report_2,3,4
LOW_LOW_Report_1
LOW_LOW_
Report_2,3,4
MUTE_Report
MUTE Pin
OUT1_P
(Filtered)
OUT2,3,4_P
(Filtered)
tGAIN tGAIN
tCM tCM
Pop Pop
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Figure 18. Individual Channel Shutdown and Restart Sequence Timing Diagram
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TAS5412-Q1
MUTE_Report
HIZ_x
MUTE Pin
OUTx_P (Filtered)
UV_LATCH
FAULT Pin
PVDD
V + V
UV UV_HY
VUV
VPOR
UV_DET
Pop
tDEGLITCH
tI2C_CL
tDEGLITCH
tGAIN
PVDD Normal Operating Region
PVDD UV Hysteresis Region
External I C Read
to Fault Register 1
2
Internal I C Write
2
UV
Detect
UV
Reset
T0194-02
tCM
Cleared by
External I C Read
2
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
Latched-Fault Shutdown and Restart Sequence Control
Figure 19. Latched Global-Fault Shutdown and Restart Timing Diagram
(UV Shutdown and Recovery)
28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
MUTE_Report
HIZ_Report_1
MUTE Pin
OUT1_P (Filtered)
UV_LATCH
FAULT Pin
PVDD
UV_DET
HIZ_Report_2,3,4
OUT2,3,4_P (Filtered)
V + V
UV UV_HY
VUV
VPOR
tDEGLITCH
tI2C_CL
tDEGLITCH
tGAIN
tCM
PVDD Normal Operating Region
PVDD UV Hysteresis Region
Internal I C Write
2
UV
Detect
UV
Reset
External I C Read
to Fault Register 1
2
Cleared by
External I C Read
2
T0195-02
Pop Pop
Pop
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Figure 20. Latched Global-Fault Shutdown and Individual-Channel Restart Timing Diagram
(UV Shutdown and Recovery)
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
Parallel Operation (PBTL)
One can parallel the device outputs on the load side of the LC output filter. Parallel operation requires identical
I2C settings for any paralleled channels in order to have reliable system performance and evenly dissipated
power on multiple channels. Having identical gain and current-limit settings can also prevent energy feeding back
from one channel to the other. For smooth power up, power down, and mute operation, send the same control
commands (such as mute, play, Hi-Z, etc.) to the paralleled channels at the same time. The device also supports
load diagnostics for parallel connection. There is no support for paralleling on the device side of the LC output
filter, and device failure can result.
Input Filter Design
For the TAS5412-Q1, the IN_M pin should have an impedance to GND that is equivalent to the parallel
combination of the input impedances of all IN_P channels combined, including any source impedance from the
previous stage in the system design. For example, if each of the two IN_P channels has a 1-µF dc blocking
capacitor, 1 kΩof series resistance due to an input RC filter, and 1 kΩof source resistance from the DAC
supplying the audio signal, the IN_M channel should have a 2-µF capacitor in series with a 1-kΩresistor to GND
(2 × 1 µF in parellel = 2 µF; 2 × 2 kΩin parallel = 1 kΩ).
Demodulation Filter Design
High-current LDMOS transistors in an H-bridge configuration drive the amplifier outputs. These transistors are
either off or on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of
the audio signal. TI recommends the use of a second-order LC filter to recover the audio signal. The main
purpose of the demodulation filter is to attenuate the high-frequency components of the output signals that are
out of the audio band. Design of the demodulation filter significantly affects the audio performance of the power
amplifier. Therefore, to meet the device THD+N specification, carefully consider the selection of the inductors
used in the output filter. The rule is that the inductance should remain stable within the range of peak current
seen at maximum output power and deliver approximately 5 µH of inductance at 16 A. If this rule is observed, the
device should not have distortion issues due to the output inductors. Another parameter to be considered is the
idle-current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target
specification for dissipation is less than 0.05. If the dissipation factor is above this value, idle current increases. In
general, 10-µH inductors suffice for most applications. The change in output load resistance slightly alters the
frequency response of the amplifier; however, unless tight control of frequency response is necessary (better
than 0.5 dB), it is not necessary to deviate from 10 µH.
Line-Driver Applications
In many automotive audio applications, the end user would like to use the same head unit to drive either a
speaker (with several ohms of impedance) or an external amplifier (with several kilohms of impedance). The
device is capable of supporting both applications. However, the output filter must be sized appropriately to
handle the expected output load in either case (that is, one must populate different output-filter values to handle
the two different cases).
Thermal Information
The thermally augmented package interfaces directly to a heat sink using a thermal interface compound (for
example, Arctic Silver®Ceramique™ thermal compound.) The heat sink then absorbs heat from the IC and
couples it to the local air. With proper thermal managerment this process can reach equilibrium and heat can be
continually removed from the ICs. Because of the efficiency of the TAS5412-Q1, heat sinks can be smaller than
those required for linear amplifiers of equivalent performance.
RθJAis a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
• RθJC (the thermal resistance from junction to case, or in this case the heat slug)
• Thermal resistance of the thermal grease
• Heat-sink thermal resistance
One can calculate the thermal resistance of the thermal grease from the exposed heat slug area and the thermal
grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The area thermal
resistance of the example thermal grease with a 0.001 inch (0.0254 mm) thick layer is about 0.007°C-in2/W
(4.52°C-mm2/W). The approximate exposed heat slug size is as follows:
Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TAS5412-Q1
TAS5412-Q1
SLOS685A –AUGUST 2013–REVISED OCTOBER 2013
www.ti.com
TAS5412-Q1, 64-pin PHD……….. 0.099 in2(64 mm2)
Dividing the example thermal grease area resistance by the area of the heat slug gives the actual resistance
through the thermal grease for both parts:
TAS5412-Q1, 64-pin PHD……….. 0.07 °C/W
The thermal resistance of thermal pads is generally considerably higher than a thin layer of thermal grease.
Because of its even-higher thermal resistance, do not use thermal tape at all. The heat sink vendor generally
predicts heat-sink thermal resistance, modeled using a continuous-flow-dynamics (CFD) model, or measured.
Thus, for a single monaural channel in the IC, the system RθJA= RθJC+ thermal-grease resistance + heat-sink
resistance.
The following table indicates modeled parameters for one TAS5412-Q1 IC on a heat sink. The junction
temperature is set at 115°C in both cases, while delivering 20 Wrms per channel into 4-Ωloads with no clipping.
Assume that the thermal grease is about 0.001 inches (0.0254 mm) thick.
Device TAS5412-Q1, 64-Pin PHD
Ambient temperature 25°C
Power to load 20 W × 2
Power dissipation 1.90 W × 2
ΔT inside package 6.46°C
ΔT through thermal grease 0.27°C
Required heatsink thermal resistance 21.91°C/W
Junction temperature 115°C
System RθJA 23.68°C/W
RθJA × power dissipation 90°C
Electrical Connection of Heat Slug and Heat Sink
Connect electrically to ground or leave floating any heat sink that connects to the heat slug of the device. Never
connect the heat slug to any electrical node other than GND.
SPACER
SPACER
REVISION HISTORY
Changes from Revision Original (August 2013) to Revision A Page
• Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA ......................................................................... 1
32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TAS5412TPHDRQ1 ACTIVE HTQFP PHD 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 TAS5412TQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TAS5412TPHDRQ1 HTQFP PHD 64 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5412TPHDRQ1 HTQFP PHD 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Oct-2013
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated
