ASIX ELECTRONICS CORPORATION Released Date: 11/05/2013
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw/
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Features
Single chip USB 2.0 to 10/100/1000M Gigabit
Ethernet controller with Energy Efficient
Ethernet (EEE) base on digital signal processing
(DSP) technology with low dissipation
USB Device Controller
Integrates on-chip USB 2.0 PHY and
controller compliant to USB Spec 2.0 and 1.1
Supports USB High/Full Speed modes with
Bus-power or Self-power device auto-detect
capability
High performance packet transfer rate over
USB bus using proprietary burst transfer
mechanism (US Patent Approval)
Gigabit Ethernet Controller
Supports IEEE 802.3az (Energy Efficient
Ethernet)
IEEE 802.3, 802.3u, and 802.3ab compatible
Integrates 10/100/1000Mbps Gigabit
Ethernet MAC/PHY
Supports dynamic cable length detection and
dynamic power adjustment Green Ethernet
(Gigabit mode only)
Supports parallel detection and automatic
polarity correction
Supports crossover detection and auto-
correction
Supports IPv4/IPv6 packet Checksum
Offload Engine (COE) to reduce CPU
loading, including IPv4
IP/TCP/UDP/ICMP/IGMP & IPv6
TCP/UDP/ICMPv6 checksum check &
generation
Supports TCP Large Send Offload V1
Supports full duplex operation with IEEE
802.3x flow control and half duplex
operation with back-pressure flow control.
Supports IEEE 802.1P Layer 2 Priority
Encoding and Decoding
Supports IEEE 802.1Q VLAN tagging and
2 VLAN ID filtering; received VLAN Tag (4
bytes) can be stripped off or preserved
Supports Jumbo frame
PHY loop-back diagnostic capability
Support Wake-on-LAN Function
Supports suspend mode and remote wakeup
via link-change, Magic Packet, Microsoft
wakeup frame and external wakeup pin
Supports Bonjour wake-on-demand
Advanced Power Management Features
Supports power management offload (ARP &
NS)
Supports dynamic power management to
reduce power dissipation during idle or light
traffic
Supports AutoDetach power saving.
Soft-disconnected from USB host when
Ethernet cable is unplugged
Supports advanced link down power saving
during Ethernet cable is unplugged
Supports optional serial EEPROM (93c56/66)
for storing USB Descriptors, Node-ID, etc
Supports embedded eFuse (64-byte) to store
USB Device Descriptors, Node-ID, etc. to save
external EEPROM
Supports automatic loading of USB Device
Descriptors, Node-ID, etc. from embedded
eFuse or external EEPROM after power-on
initialization
Single 25MHz clock input from either crystal or
oscillator source
Integrates on-chip power-on reset circuit
Integrates pipelined RISC (System on a Chip,
SoC) for handling protocol and control functions
68-pin QFN 8mm x 8mm RoHS/REACH
compliant package
Operating over 0°C to 70°C temperature range
Target Applications
USB Dongle
Docking Station
USB Port Replicator
Network Printer
POS, Card Reader
UMPC, MID, Netbook
Ultrabook
Game Console
IP STB, IP TV
Embedded system
Document No: AX88178A/V1.11/11/05/13
1
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
Typical System Block Diagrams
Hosted by USB to operate with internal Ethernet PHY only
Figure 1 : USB 2.0 to Gigabit LAN Adaptor
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked reserved, undefined or
NC. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of
their respective owners.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
Table of Contents
1 INTRODUCTION ....................................................................................................................................................... 6
1.1 GENERAL DESCRIPTION .......................................................................................................................................... 6
1.2 BLOCK DIAGRAM ................................................................................................................................................... 6
1.3 PINOUT DIAGRAM ................................................................................................................................................... 7
2 SIGNAL DESCRIPTION ........................................................................................................................................... 8
2.1 68-PIN PINOUT DESCRIPTION .................................................................................................................................. 8
2.2 HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ......................................................... 10
3 FUNCTION DESCRIPTION ................................................................................................................................... 11
3.1 USB CORE AND INTERFACES ................................................................................................................................ 11
3.2 ENERGY EFFICIENT ETHERNET (EEE) .................................................................................................................. 11
3.3 10/100/1000M ETHERNET PHY ........................................................................................................................... 11
3.4 GMAC CORE ....................................................................................................................................................... 12
3.5 CHECKSUM OFFLOAD ENGINE (COE) ................................................................................................................... 12
3.6 MEMORY ARBITER ............................................................................................................................................... 12
3.7 USB TO ETHERNET BRIDGE .................................................................................................................................. 13
3.8 EFUSE AND CONTROL ........................................................................................................................................... 13
3.9 SEEPROM LOADER INTERFACE .......................................................................................................................... 13
3.10 GENERAL PURPOSE I/O AND LED ........................................................................................................................ 13
3.11 PLL CLOCK GENERATOR ..................................................................................................................................... 14
3.12 RESET GENERATION ............................................................................................................................................. 15
4 SERIAL EEPROM/EFUSE MEMORY MAP ........................................................................................................ 16
4.1 DETAILED DESCRIPTION ....................................................................................................................................... 18
4.1.1 Node ID (00~02h) ........................................................................................................................................ 18
4.1.2 Flag (EEPROM: 05h, eFuse:18h) ............................................................................................................... 18
4.1.3 Max. Power for Self/Bus Power (07h) ......................................................................................................... 19
4.1.4 EndPoint1 for HS/FS (EEPROM:08h, eFuse: 06h) ..................................................................................... 19
4.1.5 LED Mode (EEPROM: 42h, eFuse: 19h~1Ah) ............................................................................................ 20
4.1.6 Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah) ................................................................................. 21
4.2 INTERNAL ROM DEFAULT SETTINGS ................................................................................................................... 22
4.2.1 Internal ROM Description ........................................................................................................................... 23
4.2.2 External EEPROM Description ................................................................................................................... 26
5 USB CONFIGURATION STRUCTURE ................................................................................................................ 27
5.1 USB CONFIGURATION .......................................................................................................................................... 27
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
5.2 USB INTERFACE ................................................................................................................................................... 27
5.3 USB ENDPOINTS ................................................................................................................................................... 27
6 ELECTRICAL SPECIFICATIONS ........................................................................................................................ 28
6.1 DC CHARACTERISTICS ......................................................................................................................................... 28
6.1.1 Absolute Maximum Ratings ......................................................................................................................... 28
6.1.2 Recommended Operating Condition ............................................................................................................ 28
6.1.3 Leakage Current and Capacitance .............................................................................................................. 29
6.1.4 DC Characteristics of 3.3V I/O Pins ........................................................................................................... 29
6.2 THERMAL CHARACTERISTICS ............................................................................................................................... 29
6.3 POWER CONSUMPTION ......................................................................................................................................... 30
6.4 POWER-UP SEQUENCE .......................................................................................................................................... 31
6.5 AC TIMING CHARACTERISTICS ............................................................................................................................. 32
6.5.1 Clock Timing ................................................................................................................................................ 32
6.5.2 Reset Timing ................................................................................................................................................ 32
6.5.3 Serial EEPROM Timing ............................................................................................................................... 33
7 PACKAGE INFORMATION ................................................................................................................................... 34
7.1 68-PIN QFN 8X8 PACKAGE ................................................................................................................................... 34
7.2 RECOMMENDED PCB FOOTPRINT FOR 68-PIN QFN 8X8 PACKAGE ....................................................................... 35
8 ORDERING INFORMATION ................................................................................................................................. 36
9 REVISION HISTORY .............................................................................................................................................. 37
APPENDIX A. DEFAULT WAKE-ON-LAN (DWOL) READY MODE ..................................................................... 38
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
List of Figures
FIGURE 1 : USB 2.0 TO GIGABIT LAN ADAPTOR ............................................................................................................... 1
FIGURE 2 : BLOCK DIAGRAM ............................................................................................................................................. 6
FIGURE 3 : PINOUT DIAGRAM ............................................................................................................................................. 7
FIGURE 4 : 25MHZ CRYSTAL REFERENCE CIRCUIT ......................................................................................................... 14
List of Tables
TABLE 1 : PINOUT DESCRIPTION ....................................................................................................................................... 9
TABLE 2 : MFA_3 ~ MFA_0 PIN CONFIGURATION .......................................................................................................... 10
TABLE 3 : THE EXTERNAL 25MHZ CRYSTAL UNITS SPECIFICATIONS ............................................................................. 14
TABLE 4 : SERIAL EEPROM MEMORY MAP ................................................................................................................... 16
TABLE 5 : EFUSE (64-BYTE) MEMORY MAP .................................................................................................................... 17
TABLE 6 : LED MODE SETTING TABLE ........................................................................................................................... 21
TABLE 7 : INTERNAL ROM MEMORY MAP ..................................................................................................................... 22
TABLE 8 : INTERNAL ROM DESCRIPTION ....................................................................................................................... 23
TABLE 9 : POWER CONSUMPTION .................................................................................................................................... 30
TABLE 10 : REMOTE WAKEUP TRUTH TABLE ............................................................................................................... 39
6
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
1 Introduction
1.1 General Description
The AX88178A USB 2.0 to 10/100/1000M Gigabit Ethernet controller is a high performance and highly integrated ASIC
which enables low cost, small form factor, and simple plug-and-play Gigabit Ethernet network connection capability for
desktops, notebook PC’s, Ultrabook’s, docking stations, game consoles, digital-home appliances, and any embedded
system using a standard USB port.
The AX88178A features a USB interface to communicate with a USB Host Controller and is compliant with USB
specification V2.0, and V1.1. It implements a 10/100/1000Mbps Ethernet LAN function based on IEEE802.3, IEEE802.3u,
and IEEE802.3ab standards with embedded SRAMs for packet buffering. And, it also integrates an on-chip
10/100/1000Mbps EEE-compliant Ethernet PHY to simplify system design.
1.2 Block Diagram
Figure 2 : Block Diagram
7
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
1.3 Pinout Diagram
68-pin QFN package
TEST_N4
CK25_IN
VCC12A_X
RSET_BG
TEST_X
VCCK
TEST_N3
VCC3IO
CK25_OUT
EXTWAKE_N
GND
XTL25N
VCC33IO
TEST_N2
GND12A_RX
51
50
48
47
46
45
44
43
42
41
40
39
37
36 35
TEST_N5
52
AX88178A
34
TEST_N7
MDIP0
53
33
GND12A_RX
MDIN0
54
32
TEST_N8
VCC12A
55
31
VCC12A_RX
MDIP1
56
30
GND12A_TX
MDIN1
57
29
TEST_N9
VCC33A_G
58
28
GND12A_TX
MDIP2
59
27
TEST_N10
MDIN2
60
26
VCC12A_TX
VCC12A
61
25
VCC33A
MDIP3
62
24
D-
MDIN3
63
23
D+
TEST_N6
64
22
GND33A
VCCK
65
21
VBUS
TEST0
66
20
SELF_PWR
TEST1
67
19
VCCK
TCLK_EN
68
1
2
4
5
6
7
8
9
10
11
12
13
15
16
18
RESET_N
TCLK_0
TCLK_1
GPIO_2
GPIO_1
GPIO_0/PME
MFA_3
MFA_2
GNDK
VCCK
TEST_N1
VCC3IO
MFA_1
EEDIO
EECK
EECS
Figure 3 : Pinout Diagram
17
8
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
2 Signal Description
The following abbreviations apply to the following pin description table.
I12
Input, 1.2V
AI
Analog Input
I3
Input, 3.3V
AO
Analog Output
I5
Input, 3.3V with 5V tolerant
AB
Analog Bi-directional I/O
O3
Output, 3.3V
PU
Internal Pull Up (75K ohm)
B5
Bi-directional I/O, 3.3V with 5V tolerant
PD
Internal Pull Down (75K ohm)
B3
P
Bi-directional I/O, 3.3V
Power/GND
S
T
Schmitt Trigger
Tri-stateable
2.1 68-pin Pinout Description
Pin Name
Type
Pin No
Pin Description
USB Interface
D+
AB
23
USB 2.0 data positive pin.
D-
AB
24
USB 2.0 data negative pin.
VBUS
I5/PD/S
21
VBUS pin input. Please connect to USB bus power.
Gigabit EEE Ethernet PHY Interface
RSET_BG
AO
47
For Ethernet PHYs internal biasing. Please connect to GND through a
2.49Kohm ±1% resistor.
MDIP0
AB
53
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/-
pair, and is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
MDIN0
AB
54
MDIP1
AB
56
In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/-
pair, and is the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
MDIN1
AB
57
MDIP2
AB
59
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/-
pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
MDIN2
AB
60
MDIP3
AB
62
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/-
pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
MDIN3
AB
63
Clock Pins
XTL25P
I3
38
25Mhz ± 0.005% crystal or oscillator clock input.
XTL25N
O3
39
25Mhz crystal or oscillator clock output.
CK25_OUT
O3
42
A controllable 25Mhz clock output. Please connect it to CK25_IN pin
with a 22 Ohm termination resistor near to CK25_OUT pin.
CK25_IN
I3
50
25Mhz clock input. Please connect it to CK25_OUT pin with a 22
Ohm termination resistor.
Serial EEPROM Interface
EECK
B5/PD/T
16
EEPROM Clock. EECK is an output clock to EEPROM to provide
timing reference for the transfer of EECS, and EEDIO signals. EECK
only drive high / low when access EEPROM otherwise keep at tri-state
and internal pull-down.
Note: Please pull high this EECK signal on circuit for normal
operation.
EECS
B5/PD/T
17
EEPROM Chip Select. EECS is asserted high synchronously with
respect to rising edge of EECK as chip select signal. EECS only drive
high / low when access EEPROM otherwise keep at tri-state and
internal pull-down.
EEDIO
B5/PU/T
15
EEPROM Data. EEDIO is the serial output data to EEPROMs data
input pin and is synchronous with respect to the rising edge of EECK.
EEDIO only drive high / low when access EEPROM otherwise keep at
tri-state and internal pull-up.
Misc. Pins
9
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
RESET_N
I5/PU/S
18
Chip reset input. Active low. This is the external reset source used to
reset this chip. This input feeds to the internal power-on reset circuitry,
which provides the main reset source of this chip.
EXTWAKE_N
I3/PU/S
41
Remote-wakeup trigger from external pin. EXTWAKE_N should be
asserted low for more than 2 cycles of 25MHz clock to be effective.
SELF_PWR
I5/PD/S
20
Self_power Indication Input.
0: will respond to Host that this device is a bus-power-device when
Host query device.
1: will respond to Host that this device is a self-power-device when
Host query device.
GPIO_3
B3/PD
3
General Purpose Input/ Output Pin 3.
GPIO_2
B3/PD
4
General Purpose Input/ Output Pin 2.
Note that please keep this signal at logic 0 (pull down) during
hardware reset for normal operation.
GPIO_1
B3/PD
5
General Purpose Input/ Output Pin 1. Please refer to section 2.2.
GPIO_0/PME
B3/PD
6
General Purpose Input/ Output Pin 0 or PME (Power Management
Event). This pin is default as input pin after power-on reset. GPIO_0
also can be defined as PME output to indicate wake up event detected.
MFA_3
B3
7
It is a multi-function pin but can only work as a GPIO pin. Please refer
to Table 2 for details.
MFA_2
B3
8
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000+Active) and programmable. It also can
be a GPIO pin. Please refer to Table 2 for details.
MFA_1
B3
13
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000) and programmable. It also can be a GPIO
pin. Please refer to Table 2 for details.
MFA_0
B3
14
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Active) and programmable. It also can be a GPIO pin. Please
refer to Table 2 for details.
TCLK_EN
I3/PD/S
68
Test pin. User can keep this pin NC.
TCLK_0
I3/PD
1
Test pin. User can keep this pin NC.
TCLK_1
I3/PD
2
Test pin. User can keep this pin NC.
TEST0
I3/S
66
Test pin. For normal operation, user should pull down this pin.
TEST1
I3/S
67
Test pin. For normal operation, user should pull down this pin.
TEST_X
I3
46
Test pin. For normal operation, user should pull down this pin.
TEST_N1, 2, 3,
4, 5, 6, 7, 8, 9, 10
O3
11, 36, 44,
51, 52, 64,
34, 32, 29, 27
Test pin. No connection
Power and Ground Pins
VCC33A
P
25
Analog Power for USB transceiver. 3.3V.
GND33A
P
22
Analog Ground for USB transceiver.
VCC12A_TX
P
26
Analog Power for USB transceiver. 1.2V.
GND12A_TX
P
28,30
Analog Ground for USB transceiver.
VCC12A_RX
P
31
Analog Power for USB transceiver. 1.2V.
GND12A_RX
P
33,35
Analog Ground for USB transceiver.
VCC12A_X
P
48
Analog Power for Ethernet PHY. 1.2V.
VCC33A_X
P
49
Analog Power for Ethernet PHY. 3.3V.
VCC12A
P
55,61
Analog Power for Ethernet PHY. 1.2V.
VCC33A_G
P
58
Analog Power for Ethernet PHY. 3.3V.
VCC33IO
P
37
Digital I/O Power for Clock pins. 3.3V.
GND
P
40
Digital Ground for clock pins.
VCCK
P
10, 19, 45, 65
Digital Core Power. 1.2V.
GNDK
P
9
Digital Ground to E-pad
VCC3IO
P
12, 43
Digital I/O Power. 3.3V.
Table 1 : Pinout Description
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
2.2 Hardware Setting For Operation Mode and Multi-Function Pins
The following hardware settings define the desired operation mode and some multi-function pins. The logic level shown on
setting pin below is loaded from the chip I/O pins during power on reset based on the setting of the pins pulled-up (as logic
1’) or pulled-down (as logic ‘0’) resister on the schematic.
EEPROM Offset 05h or eFuse Offset 18h, Flag[4]: Defines the multi-function pin GPIO_0 / PME
GPIO_0 is a general purpose I/O normally controlled by vendor commands. Users can change this pin to operate as a PME
(Power Management Event) for remote wake up purpose. Please refer to Section 4.1.2 Flag of bit 4 (PME_PIN).
GPIO_1 pin: Determines whether this chip will go to Default WOL Ready Mode after power on reset. The WOL stands
for Wake-On-LAN.
GPIO_1
Description
0
Normal operation mode (default, see Note 1).
1
Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7Kohm.
For more details, please refer to APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
Note 1: This is the default with internal pulled-down resistor and doesnt need an external one.
MFA_3 ~ MFA_0 pins: There are 4 multi-function pins. The MFA_2 ~ MFA_0 support the LED indication or GPIO
functionality, but the MFA_3 only supports the GPIO functionality that can be controlled by vendor command PIN
Control Register MFA_EN.
Table 2 : MFA_3 ~ MFA_0 pin configuration
PIN Name
Default definition
Section
4.1.5
MFA Control Register
MFA_3
-
-
MFAIO_3
MFA_2
Programmable LED
(Link 10/100/1000+Active)
LED_2
MFAIO_2
MFA_1
Programmable LED
(Link 10/100/1000)
LED_1
MFAIO_1
MFA_0
Programmable LED
(Active)
LED_0
MFAIO_0
11
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
3 Function Description
3.1 USB Core and Interfaces
The USB core and interfaces contains USB 2.0 transceiver interface (UTMI) and a USB 2.0 SIE
The USB 2.0 transceiver (or PHY) processes USB 2.0/1.1 Physical layer signals. And, the USB 2.0 SIE is interfacing with
USB 2.0 transceiver by UTMI bus and it processes USB packets. Also, The USB 2.0 SIE contains Bulk IN and Bulk OUT
buffers for handling Bulk transfer traffic, a FIFO for Interrupt IN transfers, and control transfer handling.
The USB core and interfaces are used to communicate with a USB host controller and is compliant with USB specification
V2.0, and V1.1.
3.2 Energy Efficient Ethernet (EEE)
It supports IEEE 802.3az also known as Energy Efficient Ethernet (EEE) at 10Mbps, 100Mbps and 1000Mbps. And also
supports EEE specified a negotiation method to enable link partner to determine whether EEE is supported and to select the
best set of parameters common to both device. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the system
goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to normal mode, and
does this without changing the link status and without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however, the transition time
to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and applications.
3.3 10/100/1000M Ethernet PHY
The 10/100/1000M Ethernet PHY is compliant with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. It
provides all the necessary physical layer functions to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT
3 UTP (10Mbps only) cable. It uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed
data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity
correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
3.4 GMAC Core
The MAC core supports IEEE 802.3, IEEE 802.3u and IEEE 802.3ab MAC sub-layer functions, such as basic MAC frame
receive and transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and
collision-detection and handling in half-duplex mode, etc. It supports virtual local area network (VLAN)-tagged frames
according to IEEE 802.1Q specification in both transmit and receive functions, CRC-32 checking at full speed using a
multi-stage, cyclic redundancy code (CRC) calculation architecture with optional forwarding of the frame check sequence
(FCS) field to the user application CRC-32 generation and append on transmit.
3.5 Checksum Offload Engine (COE)
The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header
processing functions and real time checksum calculation in hardware
The COE supports the following features in layer 3:
IP header parsing, including IPv4 and IPv6
IPv6 routing header type 0 supported
IPv4 header checksum check and generation (There is no checksum field in IPv6 header)
Detecting on RX direction for IP packets with error header checksum
The COE supports the following features in layer 4:
TCP and UDP checksum check and generation for non-fragmented packet
TCP Large Send Offload V1
ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet
3.6 Memory Arbiter
The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then
forwarding it to the USB bus upon request from the USB host via Bulk IN transfer. It also monitors the packet buffer usage
in full-duplex mode for triggering PAUSE frame (or in half-duplex mode to activate Backpressure jam signal) transmission
out on transmit (TX) direction. The memory arbiter block is also responsible for storing MAC frames received from the
USB host via Bulk OUT transfer and scheduling transmission out towards Ethernet network.
13
AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
3.7 USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa. This
block supports proprietary burst transfer mechanism (US Patent Approval) to offload software burden and to offer very high
packet transfer throughput over USB bus.
This USB to Ethernet bridge block not only co-work with eFuse and Control, “SEEPROM Loader I/F”, and General
Purpose I/Os and LEDs, but also handle USB Control transfers of Endpoint 0.
3.8 eFuse and Control
The eFuse (64-byte) and Control supports user to program USB descriptions and some device information. The data format
is shown at Section 4.
3.9 SEEPROM Loader Interface
The SEEPROM loader interface is responsible for reading configuration data automatically from the external serial
EEPROM or eFuse after power-on reset.
If the content of EEPROM offset 05h (low byte) was equal to (0xFF - SUM [EEPROM offset 03h ~ 04h]), the EEPROM is
the first candidate for SEEEPROM loader. If failed checksum checking the eFuse will be the second candidate.
If this SEEPROM Loader checks the 1st byte data of efuse is not equal to 0xFF and the eFuse Checksum [7:0] of eFuse
offset 19h is correct, the content of eFuse is valid for SEEPROM loader. If eFuse Checksum [7:0] is incorrect, the chip’s
internal default setting will be brought up to configure the corresponding valus and respond to USB standard commands,
etc.
3.10 General Purpose I/O and LED
There are 4 general-purpose I/O pins (named GPIO_0/1/2/3) and 4 multi-function pins group A (named MFA_0/1/2/3)
provided by this chip. The MFA_0/1/2 pins are also used for LED indication. Please refer to Section 4.1.5 for details.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
3.11 PLL Clock Generator
The AX88178A integrates internal oscillator circuits for 25 MHz, respectively, which allow the chip to operate cost
effectively with just external 25 MHz crystals.
The external 25 MHz crystal or oscillator, via pins XTL25P/XTL25N, provides the reference clock to internal oscillation
circuit to generate clock source for the embedded Ethernet PHY, embedded USB PHY, and base clock for ASIC use.
The external 25MHz Crystal spec is listed in below table. For more details on crystal timing, please refer to Section 6.5.1
Clock Timing and AX88178A demo board reference schematic.
Parameter
Symbol
Typical Value
Nominal Frequency
Fo
25.000000MHz
Oscillation Mode
Fundamental
Frequency Tolerance (@25)
±30ppm
Frequency Stability Over Operating
Temperature Range
±30ppm
Equivalent Series Resistance
ESR
70 Ohm max.
Load Capacitance
CL
12pF
Drive Level
350uW
Operation Temperature Range
0 ~ +70
Aging
±3ppm/year
Table 3 : The external 25MHz Crystal Units specifications
R26
200R
XTL25P
C14
15pF
C16
15pF
XTL25N
R6 NC,1M
Y1
25M CRYSTAL
41
2 3
Figure 4 : 25MHz Crystal Reference Circuit
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
3.12 Reset Generation
The AX88178A integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on PCB design.
The power-on-reset circuit generates a reset pulse to reset chip logic after 1.2V core power ramping up to 0.72V (typical
threshold). The external hardware reset input pin, RESET_N, is fed directly to the input of the power-on-reset circuit and
can also be used as additional hardware reset source to reset the system logic. For more details on RESET_N timing, please
refer to Reset Timing
.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
4 Serial EEPROM/eFuse Memory Map
EEPROM
OFFSET
HIGH BYTE
LOW BYTE
00h
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Flag
EEPROM Checksum (Note_2)
06h
Reserved
Reserved
07h
Max. Power for Self Power
Max. Power for Bus Power
08h
EndPoint1 for HS
EndPoint1 for FS
09h
Language ID High Byte
Language ID Low Byte
0Ah
Length of Product String (bytes)
Offset of Product String (0Eh)
0Bh
Length of Manufacturer String (bytes)
Offset of Manufacturer String (1Ah)
0Ch
Length of Serial Number String (bytes)
Offset of Serial Number String (26h)
0Dh
Reserved
19~0Eh
Product String: (Max.) 24 bytes
25~1Ah
Manufacturer String: (Max.) 24 bytes
2C~26h
Serial Number String: (Max.) 14 bytes
3C~2Dh
Reserved
41~3Dh
Fixed_pattern (10 bytes)
42h
LED_Mode_HB
LED_Mode_LB
Table 4 : Serial EEPROM Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to 1 (i.e. cannot be set to
multicast MAC address).
Note_2: The value of EEPROM Checksum field located at EEPROM offset 05h (low byte). The correct value must be equal
to (0xFF - SUM [EEPROM offset 03h ~ 04h]). If SUM [EEPROM offset 03h ~ 04h] has carry, please add 1 to its
result.
Note_3: Total usage is about 134 bytes.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
eFuse
OFFSET
HIGH BYTE
LOW BYTE
00h
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Reserved
Max. Power for Bus Power
06h
EndPoint1 for HS
EndPoint1 for FS
07h
Language ID High Byte
Language ID Low Byte
08h
Length of Product String (bytes)
Offset of Product String (0Bh)
09h
Length of Manufacturer String (bytes)
Offset of Manufacturer String (11h)
0Ah
Reserved
Reserved
10~0Bh
Product String: (Max.) 12 bytes
15~11h
Manufacturer String: (Max.) 10 bytes
17~16h
Reserved
18h
Flag
Reserved
19h
LED_Mode_LB
eFuse Checksum[7:0] (Note_2)
1Ah
Fixed_pattern (First byte)
LED_Mode_HB
1E~1Bh
Fixed_pattern (9th~2nd bytes)
1Fh
Max. Power for Self Power [3:0] and
Reserved [7:4]
Fixed_pattern (10th byte)
Table 5 : eFuse (64-byte) Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to 1 (i.e. cannot be set to
multicast MAC address).
Note_2: The correct value of eFuse Checksum field must be equal to (0xFF - SUM [eFuse offset 00h ~ 1Fh excluding eFuse
Checksum field]). If SUM [eFuse offset 00h ~ 1Fh excluding eFuse Checksum field] has carry, please add 1 to its
result.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
4.1 Detailed Description
The following sections provide detailed descriptions for some of the fields in memory maps of serial EEPROM and eFuse.
Please refer to AX88178A EEPROM User Guide for more details.
4.1.1 Node ID (00~02h)
The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 04-23-45-67-89-AB,
then Node ID 0 = 04h, Node ID 1 = 23h, Node ID 2 = 45h, Node ID 3 = 67h, Node ID 4 = 89h, and Node ID 5 = ABh.
Default values: Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-78-01.
4.1.2 Flag (EEPROM: 05h, eFuse:18h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PME_IND
PME_TYPE
PME_POL
PME_PIN
SNT
0
WOLLP
RWU
RWU: Remote Wakeup support.
1: Indicate that this device supports Remote Wakeup (default).
0: Not support.
WOLLP: Wake-On-LAN Low Power function.
1: Enabled (default).
0: Disabled.
SNT: Serial Number Type. (Only valid for eFuse)
When SEEPROM loader selected EEPROM:
Please set this bit to ‘0’ for EEPROM. The Serial Number String will refer to Table 4 EEPROM offset 26h ~2Ch.
When SEEPROM loader selected eFuse:
1: Serial Number String is fixed to 00000000000001.
0: Use Node ID as Serial Number String (default).
For example, when Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-78-01,
Serial Number String = 00000EC6817801.
PME_PIN: PME / GPIO_0.
1: Set GPIO_0 pin as PME (default).
0: GPIO_0 pin is controlled by vendor command.
PME_POL: PME pin active Polarity.
1: PME active high (default).
0: PME active low.
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
PME_TYP: PME I/O Type.
1: PME output is a Push-Pull driver (default).
0: PME output to function as an open-drain buffer.
PME_IND: PME indication.
1: A 1.363ms pulse active when detecting wake-up event.
0: A static signal active when detecting wake-up event (default).
4.1.3 Max. Power for Self/Bus Power (07h)
They are Max power values setting of powerd device for EEPROM at offset 07h. Bus power setting for eFuse is at
offset 05h (Low Byte), and Self power setting for eFuse at offset 1Fh (High Byte) [3:0].
The default value of Bus Power is 3Eh: For USB 2.0, the power value is 248mA (Unit = 4mA).
Self power setting follows conversion above.
4.1.4 EndPoint1 for HS/FS (EEPROM:08h, eFuse: 06h)
It's Interval (named “bInterval”) for polling Interrupt IN endpoint 1 for data transfers of High-Speed/Full-Speed.
Expressed in frames or microframes depending on the device operating speed (i.e. either 1 millisecond or 125 μs
units).
The default “bInterval” value is 0Bh for High-Speed (the polling time of endpoint 1= 2(11-1) * 125 μs=128ms) and is
80h for Full-Speed (the polling time of endpoint 1= 128 * 1ms=128ms).
Keep this field as the recommended default values (0Bh for High-Speed & 80h for Full-Speed).
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
4.1.5 LED Mode (EEPROM: 42h, eFuse: 19h~1Ah)
Its to define the indication setting for LED_0/1/2 function of MFA_0/1/2 pins.
Bit 7~Bit 0: LED_Mode_LB; Bit 15~Bit 8: LED_Mode_HB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LED1_100
LED1_10
LED1_Active
LED0_Duplex
LED0_1000
LED0_100
LED0_10
LED0_Active
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
LED2_Duplex
LED2_1000
LED2_100
LED2_10
LED2_Active
LED1_Duplex
LED1_1000
Note: Bit 15 must be 1 to enable the LED_mode setting; otherwise, it will work at default LED mode.
The LED mode table is as below:
bit
4
3
2
1
0
Description of indication
LED_0
Full duplex
Link speed(Mbps)
Active
(TX/RX)
1000
100
10
0
0
0
0
0
Reserved.
0
0
0
0
1
Active (Default)
0
0
0
1
0
Link 10
0
0
0
1
1
Link 10+Active
0
0
1
0
0
Link 100
0
0
1
0
1
Link 100+Active
0
0
1
1
0
Link 100/10
0
0
1
1
1
Link 100/10+Active
0
1
0
0
0
Link 1000
0
1
0
0
1
Link 1000+Active
0
1
0
1
0
Link 1000/10
0
1
0
1
1
Link 1000/10+Active
0
1
1
0
0
Link 1000/100
0
1
1
0
1
Link 1000/100+Active
0
1
1
1
0
Link 1000/100/10
0
1
1
1
1
Link 1000/100/10+Active
1
0
0
0
0
Full duplex
bit
9
8
7
6
5
Description of indication
LED_1
Full duplex
Link speed(Mbps)
Active
(TX/RX)
1000
100
10
0
0
0
0
0
Reserved.
0
0
0
0
1
Active
0
0
0
1
0
Link 10
0
0
0
1
1
Link 10+Active
0
0
1
0
0
Link 100
0
0
1
0
1
Link 100+Active
0
0
1
1
0
Link 100/10
0
0
1
1
1
Link 100/10+Active
0
1
0
0
0
Link 1000
0
1
0
0
1
Link 1000+Active
0
1
0
1
0
Link 1000/10
0
1
0
1
1
Link 1000/10+Active
0
1
1
0
0
Link 1000/100
0
1
1
0
1
Link 1000/100+Active
0
1
1
1
0
Link 1000/100/10 (Default)
0
1
1
1
1
Link 1000/100/10+Active
1
0
0
0
0
Full duplex
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AX88178A
USB 2.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2012-2013 ASIX Electronics Corporation. All rights reserved.
bit
14
13
12
11
10
Description of indication
LED_2
Full duplex
Link speed(Mbps)
Active
(TX/RX)
1000
100
10
0
0
0
0
0
Reserved.
0
0
0
0
1
Active
0
0
0
1
0
Link 10
0
0
0
1
1
Link 10+Active
0
0
1
0
0
Link 100
0
0
1
0
1
Link 100+Active
0
0
1
1
0
Link 100/10
0
0
1
1
1
Link 100/10+Active
0
1
0
0
0
Link 1000
0
1
0
0
1
Link 1000+Active
0
1
0
1
0
Link 1000/10
0
1
0
1
1
Link 1000/10+Active
0
1
1
0
0
Link 1000/100
0
1
1
0
1
Link 1000/100+Active
0
1
1
1
0
Link 1000/100/10
0
1
1
1
1
Link 1000/100/10+Active (Default)
1
0
0
0
0
Full duplex
Table 6 : LED Mode Setting Table
4.1.6 Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah)
Please write these 10 bytes of fixed_pattern with hexadecimal (from low bytes to high bytes) = 40 4A 40 00 40 30 0D
49 90 41.