TSSOP8
SO8
Flip-chip with backcoating
Features
• Rail-to-rail input and output
• Low noise: 9 nV/√Hz
• Low distortion
• High output current: 80 mA (able to drive 32 Ω loads)
• High-speed: 4 MHz, 1 V/μs
• Operating from 2.7 to 12 V
• Low input offset voltage: 900 μV max. (TS922A)
• ESD internal protection: 2 kV
• Latch-up immunity
Applications
• Line drivers and actuator drivers
• Portable speakers
• Instrumentation with low noise as key factor
• Multimedia systems and portable equipments
Description
The TS922 and the TS922A devices are rail-to-rail dual BiCMOS operational
amplifiers optimized and fully specified for 3 V and 5 V operations. These devices
have high output currents which allow low-load impedances to be driven.
Very low noise, low distortion, low offset, and a high output current capability make
these devices an excellent choice for high quality, low voltage, or battery operated
audio systems.
The devices are stable for capacitive loads up to 500 pF.
Product status link
TS922 and TS922A
Rail-to-rail, high output current, dual operational amplifier
TS922, TS922A
Datasheet
DS1117 - Rev 13 - July 2018
For further information contact your local STMicroelectronics sales office. www.st.com
1Pin diagrams
Figure 1. Pinout for Flip-chip package (top view)
Figure 2. Pin connections for SO8 and TSSOP8 (top view)
TS922, TS922A
Pin diagrams
DS1117 - Rev 13 page 2/18
2Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage (1) 14
V
Vid Differential input voltage (2) ±1
Vin Input voltage (3) (VCC-) - 0.3 to (VCC+) + 0.3
Tstg Storage temperature -65 to 150
°C
TjMaximum junction temperature 150
— Soldering temperature (10 s), leaded version 250
— Soldering temperature (10 s), unleaded version 260
Rthja Thermal resistance junction-to-ambient (4)
Flip-chip 90
°C/W
SO8 125
TSSOP8 120
Rthjc Thermal resistance junction-to-case (4) SO8 40
TSSOP8 37
ESD
HBM: human body model (5) 2000
V
MM: machine model (6) 120
CDM: charged device model (7) 1500
— Latch-up immunity 200 mA
— Output short-circuit duration See note (8)
1. All voltage values, except the differential voltage are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. If Vid >
±1 V, the maximum input current must not exceed ±1 mA. In this case (Vid > ±1 V), an input series resistor
must be added to limit the input current.
3. Do not exceed 14 V.
4. Short-circuits can cause excessive heating. Destructive dissipation can result from simultaneous short-
circuits on all amplifiers. These values are typical.
5. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of
pin combinations with other pins floating.
7. Charged device model: all pins and plus package are charged together to the specified voltage and then
discharged directly to ground.
8. There is no short-circuit protection inside the device: short-circuits from the output to VCC can cause
excessive heating. The maximum output current is approximately 80 mA, independent of the magnitude of
VCC. Destructive dissipation can result from simultaneous short-circuits on all amplifiers.
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 2.7 to 12 V
Vicm Common mode input voltage range (VCC-) - 0.2 to (VCC+) + 0.2
Toper Operating free air temperature range -40 to 125 °C
TS922, TS922A
Absolute maximum ratings and operating conditions
DS1117 - Rev 13 page 3/18
3Electrical characteristics
Table 3. Electrical characteristics measured at VCC = 3 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL connected to
VCC/2 (unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Vio Input offset voltage
TS922 3
mV
TS922A 0.9
TS922EIJT 1.5
Tmin ≤ Tamb ≤ Tmax, TS922 5
Tmin ≤ Tamb ≤ Tmax, TS922A 1.8
Tmin ≤ Tamb ≤ Tmax, TS922EIJT 2.5
ΔVio/ΔT Input offset voltage drift 2 μV/°C
Iio Input offset current
Vout = VCC/2 1 30
nA
Tmin ≤ Tamb ≤ Tmax 30
Iib Input bias current
Vout = VCC/2 15 100
Tmin ≤ Tamb ≤ Tmax 100
VOH High level output voltage
RL= 10 kΩ 2.90
V
Tmin ≤ Tamb ≤ Tmax 2.90
RL = 600 Ω 2.87
Tmin ≤ Tamb ≤ Tmax 2.87
RL = 32 Ω 2.63
VOL Low level output voltage
RL= 10 kΩ 50
mV
Tmin ≤ Tamb ≤ Tmax 50
RL = 600 Ω 100
Tmin ≤ Tamb ≤ Tmax 100
RL = 32 Ω 180
Avd Large signal voltage gain
RL= 10 kΩ, Vout = 2 Vp - p200
V/mV
Tmin ≤ Tamb ≤ Tmax 70
RL = 600 Ω, Vout = 2 Vp - p35
Tmin ≤ Tamb ≤ Tmax 15
RL = 32 Ω, Vout = 2 Vp - p16
ICC Total supply current
No load, Vout = VCC/2 2 3 mA
Tmin ≤ Tamb ≤ Tmax 3.2
GBP Gain bandwidth product RL = 600 Ω 4 MHz
CMR Common mode rejection ratio
Vicm = 0 to 3 V 60 80 dB
Tmin ≤ Tamb ≤ Tmax 56
SVR Supply voltage rejection ratio
VCC = 2.7 to 3.3 V 60 85 dB
Tmin ≤ Tamb ≤ Tmax 60
IoOutput short-circuit current 50 80 mA
TS922, TS922A
Electrical characteristics
DS1117 - Rev 13 page 4/18
Symbol Parameter Test conditions Min. Typ. Max. Unit
SR Slew rate 0.7 1.3 V/μs
ɸm Phase margin at unit gain RL = 600 Ω, CL = 100 pF 68 Degrees
GmGain margin RL = 600 Ω, CL = 100 pF 12 dB
enEquivalent input noise voltage f = 1 kHz 9 nV/√Hz
THD Total harmonic distortion Vout = 2 Vp - p , f = 1 kHz, Av = 1, RL = 600 Ω 0.005 %
CsChannel separation 120 dB
Table 4. Electrical characteristics measured at VCC = 5 V, VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and RL connected to
VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
Vio Input offset voltage
TS922 3
mV
TS922A 0.9
TS922EIJT 1.5
Tmin ≤ Tamb ≤ Tmax, TS922 5
Tmin ≤ Tamb ≤ Tmax, TS922A 1.8
Tmin ≤ Tamb ≤ Tmax, TS922EIJT 2.5
ΔVio/ΔT Input offset voltage drift 2 μV/°C
Iio Input offset current
Vout = VCC/2 1 30
nA
Tmin ≤ Tamb ≤ Tmax 30
Iib Input bias current
Vout = VCC/2 15 100
Tmin ≤ Tamb ≤ Tmax 100
VOH High level output voltage
RL= 10 kΩ 4.9
V
Tmin ≤ Tamb ≤ Tmax 4.9
RL = 600 Ω 4.85
Tmin ≤ Tamb ≤ Tmax 4.85
RL = 32 Ω 4.4
VOL Low level output voltage
RL= 10 kΩ 50
mV
Tmin ≤ Tamb ≤ Tmax 50
RL = 600 Ω 120
Tmin ≤ Tamb ≤ Tmax 120
RL = 32 Ω 300
Avd Large signal voltage gain
RL= 10 kΩ, Vout = 2 Vp - p200
V/mV
Tmin ≤ Tamb ≤ Tmax 70
RL = 600 Ω, Vout = 2 Vp - p35
Tmin ≤ Tamb ≤ Tmax 20
RL = 32 Ω, Vout = 2 Vp - p16
Icc Total supply current
No load, Vout = VCC/2 2 3 mA
Tmin ≤ Tamb ≤ Tmax 3.2
TS922, TS922A
Electrical characteristics
DS1117 - Rev 13 page 5/18
Symbol Parameter Conditions Min. Typ. Max. Unit
GBP Gain bandwidth product RL = 600 Ω 4 MHz
CMR Common mode rejection ratio
Vicm = 0 to 5 V 60 80
dB
Tmin ≤ Tamb ≤ Tmax 56
SVR Supply voltage rejection ratio
VCC = 4.5 to 5.5 V 60 85
Tmin ≤ Tamb ≤ Tmax 60
IoOutput short-circuit current 50 80 mA
SR Slew rate 0.7 1.3 V/μs
ɸm Phase margin at unit gain RL = 600 Ω, CL =100 pF 68 Degrees
GmGain margin 12 dB
enEquivalent input noise voltage f = 1 kHz 9 nV/√Hz
THD Total harmonic distortion Vout = 2 Vp - p , f = 1 kHz, Av = 1, RL = 600 Ω 0.005 %
CsChannel separation 120 dB
TS922, TS922A
Electrical characteristics
DS1117 - Rev 13 page 6/18
4Electrical characteristic curves
Figure 3. Output short-circuit current vs. output voltage
Output short-circuit current (mA)
Output voltage (V)
VCC = 0/3 V
Source
Sink
Figure 4. Total supply current vs. supply voltage
Supply current (mA)
Supply voltage (V)
Figure 5. Voltage gain and phase vs. frequency
1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08
-20
0
20
40
60
-60
0
60
120
180
Frequency (Hz)
Gain ( dB)
Phase
CI = 100 pF
RI = 10 kΩ
Gain
Phase (deg.)
Figure 6. Equivalent input noise voltage vs. frequency
0.01 0.1 1 10 100
Frequency (kHz)
0
5
10
15
20
25
30
Equivalent input noise (nV/√Hz)
VCC
= ±1.5 V
RL = 100 Ω
Figure 7. THD + noise vs. frequency (RL = 2 kΩ, Vo =
10 Vpp, VCC = ± 6 V)
0.01 0.1 1 10 100
0
0.005
0.01
0.015
0.02
Frequency (kHz)
THD + noise (%)
RL = 2 kΩ, Vo = 10 Vpp
VCC = ±6 V, Av = 1
Figure 8. THD + noise vs. frequency (RL = 32 Ω, Vo =
4 Vpp, VCC = ± 2.5 V)
0.01 0.1 1 10 100
0
0.008
0.016
0.024
0.032
0.04
R = 32 Ω, Vo = 4 Vpp
VCC = ±2.5 V, Av = 1
Frequency (kHz)
THD + noise (%)
L
TS922, TS922A
Electrical characteristic curves
DS1117 - Rev 13 page 7/18
Figure 9. THD + noise vs. frequency (RL = 32 Ω, Vo =
2 Vpp, VCC = ± 1.5 V)
0.01 0.1 1 10 100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (kHz)
THD + noise (%)
R = 32 Ω, Vo
= 2 Vpp
VCC = ±1.5 V, Av = 10
L
Figure 10. THD + noise vs. output voltage (RL = 600 Ω, f =
1 kHz, VCC = 0/3 V)
0 0,2 0,4 0,6 0,8 1 1,2
0,001
0,010
0,100
1,000
10,000
Vout (Vrms)
THD + noise (%)
R = 600 Ω, f = 1 kHz
VCC
= 0/3 V, Av = 10
L
Figure 11. THD + noise vs. output voltage (RL = 32 Ω, f =
1 kHz, VCC = ± 1.5 V)
0 0.2 0.4 0.6 0.
0.01
0.1
1
10
THD + noise (%)
Vout (Vrms)
R = 32 Ω, f = 1 kHz
VCC = ±1.5 V, Av = 1
L
Figure 12. THD + noise vs. output voltage (RL = 2 kΩ, f =
1 kHz, VCC = ± 1.5 V)
0 0.2 0.4 0.6 0.8 1 1.2
0.001
0.01
0.1
1
10
THD + noise (%)
Vout (Vrms)
R = 2 kΩ, f = 1 kHz
VCC = ±1.5 V, Av = -1
L
Figure 13. Open loop gain and phase vs. frequency
1E+2 1E+3 1E+4 1E+5 1E+6 1E+7 1E+8
0
10
20
30
40
50
0
60
120
180
Frequency (Hz)
Gain (dB)
Phase (deg.)
CL = 500 pF
TS922, TS922A
Electrical characteristic curves
DS1117 - Rev 13 page 8/18
5Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.1 8-bump Flip-chip package information
Figure 14. 8-bump Flip-chip package dimensions (top view)
1. Die size: 1600 µm x 1600 µm ±30 µm, Die height: 350 µm ±20 µm, die height (including bumps): 650 µm,
bump diameter: 315 µm ±50 µm, bump height: 250 µm ±40 µm, pitch: 500 µm ±10 µm, backcoating.
TS922, TS922A
Package information
DS1117 - Rev 13 page 9/18
Figure 15. 8-bump Flip-chip recommended footprint (TS922EIJT)
Figure 16. 8-bump Flip-chip marking (top view)
1. ST logo
2. Part number
3. Date code: Y = year, WW = week
4. This dot indicates the bump corner 1A
TS922, TS922A
8-bump Flip-chip package information
DS1117 - Rev 13 page 10/18
Figure 17. 8-bump Flip-chip tape and reel specification (top view)
A
1
A
1
User direction of fee d
A
1
A
1
Use r direction of fee d
1. Device orientation: the devices are oriented in the carrier pocket with bump number A1 adjacent to the
pocket holes.
TS922, TS922A
8-bump Flip-chip package information
DS1117 - Rev 13 page 11/18
5.2 SO8 package information
Figure 18. SO8 package outline
Table 5. SO8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
L1 1.04 0.040
k 0° 8° 0° 8°
ccc 0.10 0.004
TS922, TS922A
SO8 package information
DS1117 - Rev 13 page 12/18
5.3 TSSOP8 package information
Figure 19. TSSOP8 package outline
a a a
Table 6. TSSOP8 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.2 0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.008
D 2.90 3.00 3.10 0.114 0.118 0.122
E 6.20 6.40 6.60 0.244 0.252 0.260
E1 4.30 4.40 4.50 0.169 0.173 0.177
e 0.65 0.0256
k 0° 8° 0° 8°
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1 0.039
aaa 0.1 0.004
TS922, TS922A
TSSOP8 package information
DS1117 - Rev 13 page 13/18
6Ordering information
Table 7. Ordering information
Order code Temperature range Package Packing Marking
TS922ID
-40 °C to 125 °C
SO8 Tube or tape and reel
922I
TS922IDT
TS922AID 922AI
TS922AIDT
TS922IYDT (1)
SO8 (automotive grade) 922IY
TS922AIYDT (1)
Tape and reel
922AIY
TS922IPT TSSOP8 922I
TS922AIPT 922AI
TS922IYPT (1)
TSSOP8 (automotive grade) 922IY
TS922AIYPT (1) 922AY
TS922EIJT Flip-chip with backcoating 922
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
and Q 002 or equivalent.
TS922, TS922A
Ordering information
DS1117 - Rev 13 page 14/18
Revision history
Table 8. Document revision history
Date Revision Changes
01-Feb-2001 1 First release.
01-Jul-2004 2 Flip-chip package inserted in the document.
02-May-2005 3 Modifications in AMR Table 1 (explanation of Vid and Vi limits, ESD MM and CDM values added,
Rthja added).
01-Aug-2005 4 PPAP references inserted in the datasheet, see Table 8.
01-Mar-2006 5 TS922EIJT part number inserted in the datasheet, see Table 8.
26-Jan-2007 6 Modifications in AMR Table 1 (Rthjc added), parameter limits on full temperature range added in
Table 3 and Table 4.
12-Nov-2007 7
Added notes on ESD in AMR table.
Re-formatted package information.
Added notes for automotive grade in order codes table.
02-Feb-2010 8
Document reformatted.
Added root part number TS922A on cover page.
Removed TS922AIYD order code from Table 8.
15-Jan-2013 9
Added MiniSO8 package.
Modified test conditions for CMR in Table 3 and Table 4.
Replaced VDD by VCC- in title of Table 3, Table 4, and Table 5.
Updated titles of Figure 7 to Figure 12 (added conditions to differentiate them).
Removed TS922IYD device from Table 8.
Minor corrections throughout document.
04-Jun-2013 10
Features: updated package information for Flip-chip
Figure 2: Updated title
Table 1: updated footnotes 5, 6, and 7
Table 3 and Table 4: replaced DVio with ΔVio/ΔT
Figure 14: added backcoating to package information
Figure 16: updated footnote 3
Table 8: updated package information for Flip-chip
27-Jun-2013 11 Figure 14: updated to include new height for backcoating
20-Jan-2016 12
Updated document layout
Removed MiniSO8 and DIP8 packages
Updated cover image: removed J, D (plastic micropackage), and P (thin shrink small outline
package) respectively from Flip-chip with backcoating, SO8, and TSSOP packages.
Table 6: updated SO8 information for min “k” parameter (mm dimensions)
Table 7: updated “aaa” information. These are “typ” not "max" values.
Table 8: "Order codes": removed following order codes: TS922IST, TS922AIST, TS922IN,
TS922IYST. TS922AIYST, and TS922IJT.
TS922, TS922A
DS1117 - Rev 13 page 15/18
Contents
1Pin diagrams ......................................................................2
2Absolute maximum ratings and operating conditions ..............................3
3Electrical characteristics...........................................................4
4Electrical characteristic curves ....................................................7
5Package information...............................................................9
5.1 8-bump Flip-chip package information .............................................9
5.2 SO8 package information.......................................................12
5.3 TSSOP8 package information ...................................................13
6Ordering information .............................................................14
Revision history .......................................................................15
TS922, TS922A
Contents
DS1117 - Rev 13 page 17/18
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TS922, TS922A
DS1117 - Rev 13 page 18/18
