8XC196NT CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE Y 20 MHz Operation Y Oscillator Fail Detection Circuitry Y High Performance CHMOS 16-Bit CPU Y Y Up to 32 Kbytes of On-Chip OTPROM High Speed Peripheral Transaction Server (PTS) Up to 1 Kbyte of On-Chip Register RAM Y Y Y Up to 512 Bytes of Internal RAM Two Dedicated 16-Bit High-Speed Compare Registers Y Register-Register Architecture 10 High Speed Capture/Compare (EPA) Y Y Y 4 Channel/10-Bit A/D with Sample/Hold Full Duplex Synchronous Serial I/O Port (SSIO) Y 37 Prioritized Interrupt Sources Y Two Flexible 16-Bit Timer/Counters Y Up to Seven 8-Bit (56) I/O Ports Y Quadrature Counting Inputs Y Full Duplex Serial I/O Port Y Y Dedicated Baud Rate Generator Flexible 8-/16-Bit External Bus (Programmable) Y Interprocessor Communication Slave Port Y Programmable Bus (HOLD/HLDA) Y 1.4 ms 16 x 16 Multiply Y 2.4 ms 32/16 Divide Y 68-Pin Package Y Selectable Bus Timing Modes for Flexible External Memory Interfacing Device 8XC196NT Pins/Package 68P PLCC OTPROM Reg RAM Code RAM Address Space I/O EPA A/D 32K 1K 512 1 Mbyte 56 10 4 X e 7 OTPROM Device X e 0 ROMLESS The 8XC196NT 16-bit microcontroller is a high performance member of the MCSE 96 microcontroller family. The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space, 1000 bytes of register RAM, 512 bytes of internal RAM, 20 MHz operation and an optional 32 Kbytes of OTPROM. Intel's CHMOS III-E process provides a high performance processor along with low power consumption. Ten high-speed capture/compare modules are provided. As capture modules event times with 200 ns resolution can be recorded and generate interrupts. As compare modules events such as toggling of a port pin, starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be based on the timer or up/down counter. December 1996 Order Number: 272267-005 8XC196NT 272267- 1 Figure 1. 8XC196NT Block Diagram PROCESS INFORMATION This device is manufactured on P629.5, a CHMOS III-E process. Additional process and reliability information is available in the Intel(R) Quality System Handbook . All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology. Table 1. Thermal Characteristics Package Type PLCC iJA 36.5 C/W iJC 13 C/W 272267 - 2 EXAMPLE: N87C196NT is 68-Lead PLCC OTPROM. For complete package dimensional data, refer to the Intel Packaging Handbook (Order Number 240800). Figure 2. The 8XC186NT Familiy Nomenclature 2 8XC196NT 8XC196NT Memory Map Address (Note 7) Description FFFFFFH FFA000H External Memory FF9FFFH FF2080H Internal OTPROM or External Memory (Determined by EA Pin) RESET at FF2080H FF207FH FF2000H Reserved Memory (Internal OTPROM or External Memory) (Determined by EA Pin) FF1FFFH FF0600H External Memory FF05FFH FF0400H Internal RAM (Identically Mapped into 00400H - 005FFH) FF03FFH FF0100H External Memory FF00FFH FF0000H Reserved for ICE FEFFFFH 100000H External Memory for future devices FFFFFH 00A000H 984 Kbytes External Memory 009FFFH 002080H Internal OTPROM or External Memory (Note 1) 00207FH 002000H Reserved Memory (Internal OTPROM or External Memory) (Notes 1, 3, and 6) 001FFFH 001FE0H Memory Mapped Special Function Registers (SFR's) 001FDFH 001F00H Internal Special Function Registers (SFR's) (Note 5) 001EFFH 000600H External Memory 0005FFH 000400H Internal RAM (Address with Indirect or Indexed Modes) 0003FFH Upper Register File (Address with Indirect or Register RAM 000100H 0000FFH 000018H Register RAM 000017H 000000H CPU SFR's * * Indexed Modes or through Windows.) (Note 2) Lower Register File (Address with Direct, Indirect, or Indexed Modes.) (Notes 2, 4) NOTES: 1. These areas are mapped internal OTPROM if the REMAP bit (CCB2.2) is set and EA e 5V. Otherwise they are external memory. 2. Code executed in locations 00000H to 003FFH will be forced external. 3. Reserved memory locations must contain 0FFH unless noted. 4. Reserved SFR bit locations must be written with 0. 5. Refer to 8XC196NT User's Guide and Quick Reference for SFR descriptions. 6. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly. 7. The 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 Mbyte external address space. 3 8XC196NT 272267 - 3 Figure 3. 68-Pin PLCC Package Diagram 4 8XC196NT PIN DESCRIPTIONS Symbol Name and Function VCC Main supply voltage ( a 5V). VSS, VSS1, VSS1 Digital circuit ground (0V). There are multiple VSS pins, all of which MUST be connected. VREF Reference for the A/D converter ( a 5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. VPP Programming voltage for the OTPROM parts. It should be a 12.5V for programming. It is also the timing pin for the return from powerdown circuit. Connect to VCC if powerdown not being used. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the oscillator inverter. P2.7/CLKOUT Output of the internal clock generator. The frequency is (/2 the oscillator frequency. It has a 50% duty cycle. Also LSIO pin. RESET Reset input to and open-drain output from the chip. RESET has an internal pullup. P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ``0'' and CCR1 bit 2 is ``1'', all bus cycles are 8-bit, if CCR bit 1 is ``1'' and CCR1 bit 2 is ``0'', all bus cycles are 16-bit. CCR bit 1 e ``0'' and CCR1 bit 2 e ``0'' is illegal. Also an LSIO pin when not used as BUSWIDTH. NMI A positive transition causes a non maskable interrupt vector through memory location 203EH. P5.1/INST/SLPCS Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is active only during external memory fetches, during internal OTPROM fetches INST is held low. Also LSIO when not INST. SLPCS is the Slave Port Chip Select. EA Input for memory select (External Access). EA equal to a high causes memory accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip OTPROM. EA equal to a low causes accesses to these locations to be directed to off-chip memory. EA e a 12.5V causes execution to begin in the Programming Mode. EA is latched at reset. HOLD Bus Hold Input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. P5.0/ALE/ADV/ SLPADDR/ SLPALE Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip select for external memory. ALE/ADV is active only during external memory accesses. Also LSIO when not used as ALE. SLPADDR is the Slave Port Address Control Input and SLPALE is the Slave Port Address Latch Enable Input. P5.3/RD/SLPRD Read signal output to external memory. RD is active only during external memory reads or LSIO when not used as RD. SLPRD is the Slave Port Read Control Input. 5 8XC196NT PIN DESCRIPTIONS (Continued) Symbol 6 Name and Function P5.2/WR/WRL/SLPWR Write and Write Low output to external memory, as selected by the CCR, WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is active during external memory writes. Also an LSIO pin when not used as WR/WRL. SLPWR is the Slave Port Write Control Input P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHE e 0 selects the bank of memory that is connected to the high byte of the data bus. A0 e 0 selects that bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0, BHE e 1), to the high byte only (A0 e 1, BHE e 0) or both bytes (A0 e 0, BHE e 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is only valid during 16-bit external memory read/write cycles. Also an LSIO pin when not BHE/WRH. P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO pin when READY is not selected. P5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The system function is a Slave Port Interrupt Output Pin. P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on both positive and negative edges of this pin. P6.3/T1DIR Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Direction input. The TIMER1 will increment when this pin is high and decrements when this pin is low. PORT1/EPA0-7 P6.0-6.1/EPA8-9 Dual function I/O port pins. Primary function is that of bidirectional I/O. System function is that of High Speed capture and compare. EPA0 and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer/counter. PORT 0/ACH4-7 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to OTPROM parts to select the Programming Mode. P6.3-6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data, providing full duplex capability. PORT 2 8-bit multi-functional port. All of its pins are shared with other functions. PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. EPORT 8-bit bidirectional standard and I/O port. These bits are shared with the extended address bus, A16 - A19. Pin function is selected on a per pin basis. INTOUT Interrupt Output. This active-low output indicates that a pending interrupt requires use of the external bus. SLP0-SLP7 Slave Port Address/Data Bus 8XC196NT ABSOLUTE MAXIMUM RATINGS* Storage Temperature AAAAAAAAAA b 60 C to a 150 C Voltage from VPP or EA to VSS or ANGND AAAAAAAAAAAAAA b 0.5V to a 13.0V Voltage from Any Other Pin to VSS or ANGND AAAAAAAAAAAAAA b 0.5 to a 7.0V This includes VPP on ROM and CPU devices . Power DissipationAAAAAAAAAAAAAAAAAAAAAAAAAA0.5W NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability. OPERATING CONDITIONS Parameter Min Max Units TA Symbol Ambient Temperature Under Bias 0 a 70 C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 4 20 MHz (Note 4) NOTE: ANGND and VSS should be nominally at the same potential. DC CHARACTERISTICS Symbol (Under Listed Operating Conditions) Parameter Max Units 90 mA A/D Reference Supply Current 5 mA Idle Mode Current 40 mA XTAL1 e 20 MHz, VCC e VPP e VREF e 5.5V 75 mA VCC e VPP e VREF e 5.5V(11) b 0.5V 0.3 VCC V For PORT0(10) 0.7 VCC VCC a 0.5 V For PORT0(10) 0.7 VCC VCC a 0.5 V XTAL1 Input Pin Only(1) 0.7 VCC VCC a 0.5 V RESET input pin only 0.3 0.45 1.5 V V V IOL e 200 mA(3,5) IOL e 3.2 mA IOL e 7.0 mA V V V IOH e b 200mA(3,5) IOH e b 3.2 mA IOH e b 7.0 mA ICC VCC Supply Current IREF IIDLE IPD Powerdown Mode Current(6) VIL Input Low Voltage (all pins) VIH Input High Voltage VIH1 Input High Voltage XTAL1 VIH2 Input High Voltage on RESET VOL Output Low Voltage (Outputs Configured as Complementary) VOH Output High Voltage (Outputs Configured as Complementary) ILI Input Leakage Current (Std. Inputs) ILI1 Input Leakage Current (Port 0) IIL Logical 0 Input Current Min Typ 50 VCC b 0.3 VCC b 0.7 VCC b 1.5 Test Conditions XTAL1 e 20 MHz, VCC e VPP e VREF e 5.5V (While device in Reset) g 10 mA VSS k VIN k VCC g3 mA VCC k VIN k VREF b 70 mA VIN e 0.45V(1) 7 8XC196NT DC CHARACTERISTICS Symbol (Under Listed Operating Conditions) (Continued) Parameter Min Typ Max Units 0.8 Test Conditions VOL1 Output Low Voltage in RESET V (Note 7) VOH1 SLPINT (P5.4) and HLDA (P2.6) Output High Voltage in RESET 2.0 V IOH e 0.8 mA(7) VOH2 Output High Voltage in RESET VCC b 1V V IOH e b 6 mA(1) CS Pin Capacitance (Any pin to VSS) pF ftest e 1.0 MHz RWPU Weak Pullup Resistance X (Note 6) RRST Reset Pullup 10 150K 65K 180K X NOTES: 1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5, Port6 and EPORT except SPLINT (P5.4) and HLDA (P2.6). 2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 and EPORT when setup as inputs. 3. All bidirectional I/O pins when configured as Outputs (Push/Pull). 4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum IDL/IDH currents per pin are as follows: a.) Test Condition: VOH e VCC b 0.7V Part 1: Part 2: Part 3: Part 4: Part 5: Part 6: IOL IOL IOL IOL IOL IOL e e e e e e 0.65 mA 8.0 mA 7.5 mA 7.5 mA 9.0 mA 8.0 mA IOH IOH IOH IOH IOH IOH e e e e e e VOL e 0.45V 7.5 mA 12.0 mA 7.5 mA 7.5 mA 9.0 mA 9.0 mA b.) Test Condition: VOH e VCC b 1.5V VOL e 1.5V 21.0 mA IOH 26.0 mA Part 1: IOL 26.0 mA IOH 29.0 mA Part 2: IOL 17.0 mA IOH 25.0 mA Part 3: IOL 16.0 mA IOH 25.0 mA Part 4: IOL 21.0 mA IOH 28.0 mA Part 5: IOL 19.0 mA IOH 26.0 mA Part 6: IOL 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF e VCC e 5.5V. 7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). 8. TBD e To Be Determined. 9. Pullup present during return from powerdown condition. 10. When P0 is used as analog inputs, refer to A/D specifications. 11. For temperatures k100 C typical is 10 mA. e e e e e e e e e e e e 272267 - 24 8 8XC196NT 8XC196NT ADDITIONAL BUS TIMING MODES The 8XC196NT device has 3 additional bus timing modes for external memory interfacing. MODE 1: MODE 3: Mode 1 is the long R/W mode. This mode advances RD and WR signals by 1 TOSC creating a 2 TOSC RD/WR low time. ALE is also advanced by 0.5 TOSC but ALE high time remains 1 TOSC. Mode 3 is the standard timing mode. Use this mode for systems that emulate the 8XC196KR bus timings. MODE 0: Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles. MODE 2: Mode 2 is the long R/W mode with Early Address. Mode 2 is similar to Mode 1 with respect to RD, WR, and ALE signals. Additionally, the address is output on the bus 0.5 TOSC earlier in the bus cycle. 272267 - 4 Figure 4. Detailed MODE 1, 2, 3, Comparison 9 8XC196NT EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ``T'' for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: HHigh LLow VValid XNo Longer Valid ZFloating Signals: AAddress BBHE BRBREQ CCLKOUT DDATA GBuswidth HHOLD HAHLDA LALE/ADV QData Out RDRD WWR/WRH/WRI XXTAL1 YREADY BUS MODE 0 and 3AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The system must meet these specifications to work with the 8XC196NT. Symbol Parameter TAVYV Address Valid to Ready Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TAVGV Address Valid to BUSWIDTH Setup TLLGV ALE Low to BUSWIDTH Setup TCLGX BUSWIDTH Hold after CLKOUT Low Min Max Units 2 TOSC b 75 ns(3) No Upper Limit 0 ns TOSC b 30 ns(1) 2 TOSC b 75 ns(2, 3) TOSC b 60 ns(2, 3) 0 ns 3 TOSC b 55 ns(2) TAVDV Address Valid to Input Data Valid TRLDV RD active to input Data Valid TOSC b 30 ns(2) TCLDV CLKOUT Low to Input Data Valid TOSC b 60 ns TRHDZ End of RD to Input Data Float TOSC ns TRHDX Data Hold after RD High 0 ns NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC c n, where n e number of wait states. 3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 TOSC to the specification. 10 8XC196NT BUS MODE 0 and 3AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The 8XC196NT will meet these specifications Symbol Parameter Min Max Units 4.0 20 MHz(1) 50 250 ns a 20 110 ns 40 ms FXTAL Frequency on XTAL1 TOSC XTAL1 Period (1/FXTAL) TXHCH XTAL1 High to CLKOUT High or Low TOFD Clock Failure to Reset Pulled Low(6) 4 TCLCL CLKOUT Period TCHCL CLKOUT High Period TOSC b 10 TOSC a 30 ns TCLLH CLKOUT Low to ALE/ADV High b 10 a 15 ns TLLCH ALE/ADV Low to CLKOUT High b 25 a 15 TLHLH ALE/ADV Cycle Time TLHLL ALE/ADV High Time TOSC b 10 TAVLL Address Valid to ALE Low TOSC b 15 ns TLLAX Address Hold After ALE/ADV Low TOSC b 40 ns TLLRL ALE/ADV Low to RD Low TOSC b 40 TRLCL RD Low to CLKOUT Low b5 TRLRH RD Low Period TRHLH RD High to ALE/ADV High TRLAZ RD Low to Address Float 2 TOSC ns TOSC a 10 TLLWL ALE/ADV Low to WR Low TOSC b 10 TCLWL CLKOUT Low to WR Low b 10 TQVWH Data Valid before WR High TOSC b 23 TCHWH CLKOUT High to WR High b 10 ns ns a 35 ns ns(5) TOSC b 5 TOSC ns ns(5) 4 TOSC TOSC a 25 ns(3) a5 ns ns a 25 ns ns a 15 ns ns(5) TWLWH WR Low Period TOSC b 30 TWHQX Data Hold after WR High TOSC b 35 TWHLH WR High to ALE/ADV High TOSC b 10 TWHBX BHE, INST Hold after WR High TOSC b 10 ns TWHAX AD8-15 Hold after WR High TOSC b 30 ns(4) TRHBX BHE, INST Hold after RD High TOSC b 10 ns TRHAX AD8-15 Hold after RD High TOSC b 30 ns(4) ns TOSC a 15 ns(3) NOTES: 1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 TOSC c n, where n e number of wait states. If mode 0 (1 automatic wait state added) operation is selected, add 2 TOSC to specification. 6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. NT/NQ customer QROM codes need to equate location 2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit enables oscillator fail detection. 11 8XC196NT BUS MODE 0 and 38XC196NT SYSTEM BUS TIMING 272267 - 5 *If mode 0 operation is selected, add 2 TOSC to this time. 12 8XC196NT 8XC196NT MODE 0 and 3READY TIMINGS (ONE WAIT STATE) 272267 - 6 *If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 TOSC to these specifications. MODE 0 and 38XC196NT BUSWIDTH TIMINGS 272267 - 7 *If mode 0 selected, add 2 TOSC to these specifications. 13 8XC196NT BUS MODE 1AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The system must meet these specifications to work with the 8XC196NT. Symbol Parameter TAVYV Address Valid to Ready Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TAVGV Address Valid to BUSWIDTH Setup TLLGV ALE Low to BUSWIDTH Setup TCLGX BUSWIDTH Hold after CLKOUT Low Min 2 TOSC b 75 No Upper Limit 0 Units ns ns TOSC b 30 ns(1) 2 TOSC b 75 ns 1.5 TOSC b 60 ns 0 ns ns(2) TAVDV Address Valid to Input Data Valid 3 TOSC b 60 TRLDV RD active to input Data Valid 2 TOSC b 44 ns(2) TOSC b 60 ns TOSC ns TCLDV CLKOUT Low to Input Data Valid TRHDZ End of RD to Input Data Float TRHDX Data Hold after RD High 0 NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC c n, where n e number of wait states. 14 Max ns 8XC196NT BUS MODE 1AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The 8XC196NT will meet these specifications Min Max Units FXTAL Symbol Frequency on XTAL1 Parameter 8.0 20 MHz(1) TOSC XTAL1 Period (1/FXTAL) 50 125 ns TXHCH XTAL1 High to CLKOUT High or Low 110 ns TCLCL CLKOUT Period a 20 2 TOSC ns TCHCL CLKOUT High Period TCHLH CLKOUT HIGH to ALE/ADV High TOSC b 10 0.5 TOSC b 15 TOSC a 27 0.5 TOSC a 15 ns TCLLL CLKOUT LOW to ALE/ADV Low 0.5 TOSC b 25 0.5 TOSC a 15 ns TLHLH ALE/ADV Cycle Time TLHLL ALE/ADV High Time TAVLL Address Valid to ALE Low 0.5 TOSC b 20 ns TLLAX Address Hold After ALE/ADV Low 0.5 TOSC b 25 ns TLLRL ALE/ADV Low to RD Low 0.5 TOSC b 15 TRLCL RD Low to CLKOUT Low TOSC b 10 TRLRH RD Low Period TRHLH RD High to ALE/ADV High ns(5) 4 TOSC TOSC b 20 TOSC a 10 ns ns TOSC a 30 ns ns(5) 2 TOSC b 20 0.5 TOSC ns 0.5 TOSC a 25 a5 TRLAZ RD Low to Address Float TLLWL ALE/ADV Low to WR Low 0.5 TOSC b 10 TCLWL CLKOUT Low to WR Low TOSC b 15 TOSC a 25 a 15 ns(3) ns ns ns TQVWH Data Valid before WR High TCHWH CLKOUT High to WR High 2 TOSC b 23 b 10 ns TWLWH WR Low Period 2 TOSC b 15 TWHQX Data Hold after WR High 0.5 TOSC b 12 TWHLH WR High to ALE/ADV High 0.5 TOSC b 10 TWHBX BHE Hold after WR High TOSC b 15 TWHIX INST Hold after WR High 0.5 TOSC b 15 TWHAX AD8-15 Hold after WR High 0.5 TOSC b 30 ns(4) TRHBX BHE Hold after RD High ns TRHIX INST Hold after RD High TOSC b 32 0.5 TOSC b 32 TRHAX AD8-15 Hold after RD High 0.5 TOSC b 30 ns(4) ns ns(5) ns 0.5 TOSC a 15 ns(3) ns NOTES: 1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 TOSC c n, where n e number of wait states. 15 8XC196NT MODE 18XC196NT SYSTEM BUS TIMING 272267 - 8 16 8XC196NT MODE 18XC196NT READY TIMINGS (ONE WAIT STATE) 272267 - 9 MODE 18XC196NT BUSWIDTH TIMINGS 272267 - 10 17 8XC196NT BUS MODE 2AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The system must meet these specifications to work with the 8XC196NT. Symbol Parameter TAVYV Address Valid to Ready Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TAVGV Address Valid to BUSWIDTH Setup TLLGV ALE Low to BUSWIDTH Setup TCLGX BUSWIDTH Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid TRLDV RD active to input Data Valid TCLDV CLKOUT Low to Input Data Valid TRHDZ End of RD to Input Data Float TRHDX Data Hold after RD High Min 2.5 TOSC b 75 No Upper Limit 0 0 Units ns ns TOSC b 30 ns(1) 2.5 TOSC b 75 ns 1.5 TOSC b 60 ns 0 NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC c n, where n e number of wait states. 18 Max ns 3.5 TOSC b 55 ns(2) 2 TOSC b 44 ns(2) TOSC b 60 ns 0.5 TOSC ns ns 8XC196NT BUS MODE 2AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. The 8XC196NT will meet these specifications Symbol Parameter Min Max Units 8.0 20 MHz(1) 50 125 ns a 20 a 85 ns TOSC b 10 TOSC a 27 ns CLKOUT HIGH to ALE/ADV High 0.5 TOSC b 15 0.5 TOSC a 15 ns CLKOUT LOW to ALE/ADV Low 0.5 TOSC b 25 0.5 TOSC a 15 ns FXTAL Frequency on XTAL1 TOSC XTAL1 Period (1/FXTAL) TXHCH XTAL1 High to CLKOUT High or Low TCLCL CLKOUT Period TCHCL CLKOUT High Period TCHLH TCLLL TLHLH ALE/ADV Cycle Time TLHLL ALE/ADV High Time TOSC b 20 TAVLL Address Valid to ALE Low TOSC b 15 ns TLLAX Address Hold After ALE/ADV Low 0.5 TOSC b 20 ns TLLRL ALE/ADV Low to RD Low 0.5 TOSC b 15 TRLCL RD Low to CLKOUT Low TOSC b 10 2 TOSC ns ns(5) 4 TOSC TRLRH RD Low Period 2 TOSC b 20 TRHLH RD High to ALE/ADV High 0.5 TOSC b 5 TOSC a 10 ns ns TOSC a 30 ns ns(5) 0.5 TOSC a 25 a5 ns(3) TRLAZ RD Low to Address Float TLLWL ALE/ADV Low to WR Low 0.5 TOSC b 10 ns TCLWL CLKOUT Low to WR Low TOSC b 22 TQVWH Data Valid before WR High 2 TOSC b 25 TCHWH CLKOUT High to WR High b 10 TWLWH WR Low Period TWHQX Data Hold after WR High 0.5 TOSC b 12 TWHLH WR High to ALE/ADV High 0.5 TOSC b 10 TWHBX BHE Hold after WR High TOSC b 15 TWHIX INST Hold after WR High 0.5 TOSC b 15 TWHAX AD8-15 Hold after WR High 0.5 TOSC b 30 ns(4) TRHBX BHE Hold after RD High TOSC b 32 ns TRHIX INST Hold after RD High 0.5 TOSC b 32 TRHAX AD8-15 Hold after RD High 0.5 TOSC b 30 ns TOSC a 25 ns ns a 15 ns ns(5) 2 TOSC b 20 ns 0.5 TOSC a 10 ns(3) ns ns(4) NOTES: 1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2 TOSC c n, where n e number of wait states. 19 8XC196NT MODE 28XC196NT SYSTEM BUS TIMING 272267 - 11 20 8XC196NT MODE 28XC196NT READY TIMINGS (ONE WAIT STATE) 272267 - 12 MODE 28XC196NT BUSWIDTH TIMINGS 272267 - 13 21 8XC196NT BUS MODE 0, 1, 2, and 3HOLD/HLDA TIMINGS (Over Specified Operation Conditions) Test Conditions: Capacitance Load on All Pins e 100 pF, Rise and Fall Times e 10 ns. Symbol Parameter Min Max Units ns(1) THVCH HOLD Setup Time a 65 TCLHAL CLKOUT Low to HLDA Low b 15 a 15 ns TCLBRL CLKOUT Low to BREQ Low b 15 a 15 ns THALAZ HLDA Low to Address Float a 25 ns THALBZ HLDA Low to BHE, INST, RD, WR Weakly Driven a 25 ns TCLHAH CLKOUT Low to HLDA High b 25 a 15 ns TCLBRH CLKOUT Low to BREQ High b 25 a 25 ns THAHAX HLDA High to Address No Longer Float b 15 ns THAHBV HLDA High to BHE, INST, RD, WR Valid b 10 ns NOTE: 1. To guarantee recognition at next clock. 8XC196NT HOLD/HLDA TIMINGS 272267 - 14 22 8XC196NT AC CHARACTERISTICSSLAVE PORT SLAVE PORT WAVEFORM(SLPL e 0) 272267 - 15 SLAVE PORT TIMING(SLPL e 0) Symbol Parameter Min Max Units TSAVWL Address Valid to WR Low 50 ns TSRHAV RD High to Address Valid 60 ns TSRLRH RD Low Period TOSC ns TSWLWH WR Low Period TOSC ns TSRLDV RD Low to Output Data Valid TSDVWH Input Data Setup to WR High TSWHQX WR High to Data Invalid 30 ns TSRHDZ RD High to Data Float 15 ns 60 20 ns ns NOTES: 1. Test Conditions: FOSC e 20 MHz, TOSC e 50 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. 23 8XC196NT AC CHARACTERISTICSSLAVE PORT (Continued) SLAVE PORT WAVEFORM(SLPL e 1) 272267 - 16 SLAVE PORT TIMING(SLPL e 1) Parameter Min TSELLL Symbol CS Low to ALE Low 20 Max Units ns TSRHEH RD or WR High to CS High 60 ns TSLLRL ALE Low to RD Low TOSC ns TSRLRH RD Low Period TOSC ns TSWLWH WR Low Period TOSC ns TSAVLL Address Valid to ALE Low 20 ns TSLLAX ALE Low to Address Invalid 20 ns TSRLDV RD Low to Output Data Valid TSDVWH Input Data Setup to WR High TSWHQX WR High to Data Invalid 30 ns TSRHDZ RD High to Data Float 15 ns 60 20 NOTES: 1. Test Conditions: FOSC e 20 MHz, TOSC e 50 ns. Rise/Fall Time e 10 ns. Capacitive Pin Load e 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. 24 ns ns 8XC196NT EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TXLXL Oscillator Frequency 4 20 MHz TXLXL Oscillator Period (TOSC) 50 250 ns TXHXX High Time 0.35 c TOSC 0.65 TOSC ns TXLXX Low Time 0.35 c TOSC 0.65 TOSC ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CLOCK DRIVE WAVEFORMS 272267 - 17 AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS 272267 - 19 272267 - 18 AC Testing inputs are driven at 3.5V for a logic ``1'' and 0.45V for a logic ``0''. Timing measurements are made at 2.0V for a logic ``1'' and 0.8V for logic ``0''. For timing purposes a Port Pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs IOL/IOH s 15 mA. 25 8XC196NT WAVEFORMSERIAL PORTSHIFT REGISTER MODE SERIAL PORT WAVEFORMSHIFT REGISTER MODE (MODE 0) 272267 - 20 AC CHARACTERISTICSSERIAL PORT-SHIFT REGISTER MODE SERIAL PORT TIMINGSHIFT REGISTER MODE (MODE 0) Test Conditions: TA e b 40 C to a 125 C; VCC e 5.0V g 10%; VSS e 0.0V; Load Capacitance e pF Symbol TXLXL(2) Parameter Serial Port Clock Period (BRR t 8002H) Receive Only Min Max 6 TOSC Units ns TXLXH(2) Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) 4 TOSC b 50 4 TOSC a 50 ns TXLXL(2) ns Serial Port Clock Period (BRR e 8001H) Transmit Only 4 TOSC TXLXH(2) Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 2 TOSC a 50 TQVXH Output Data Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge TXHQV Next Output Data Valid after Clock Rising Edge TDVXH Input Data Setup to Clock Rising Edge TXHDX(1) Input Data Hold after Clock Rising Edge TXHQZ(1) Last Clock Rising to Output Float ns 3 TOSC ns 2 TOSC b 50 ns 2 TOSC a 50 2 TOSC a 200 ns ns 0 ns 5 TOSC ns NOTES: 1. Parameters not tested. 2. The minimum baud rate register value for Receive is 8002H. The minimum baud rate register value for Transmit is 8001H. 26 8XC196NT A to D CHARACTERISTICS The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. 10-BIT MODE A/D OPERATING CONDITIONS Description Min Max Units TA Symbol Ambient Temperature 0 a 70 C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time 10 15 ms(2) FOSC Oscillator Frequency 4.0 20 MHz ms(2) NOTES: 1. VREF must be within 0.5V of VCC. 2. The value of ADTIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS Parameter (Using Above Operating Conditions)(6) Typ*(1) Resolution Absolute Error Min Max Units* 1024 10 1024 10 Level Bits 0 g 3.0 LSBs Full Scale Error 0.25 g 0.5 LSBs Zero Offset Error 0.25 g 0.5 LSBs Non-Linearity 1.0 g 2.0 Differential Non-Linearity Channel-to-Channel Matching g 3.0 LSBs b 0.75 a 0.75 LSBs g 1.0 g 0.1 0 Repeatability g 0.25 0 Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 Off Isolation LSBs LSBs(1) LSB/C(1) LSB/C(1) LSB/C(1) dB(1,2,3) b 60 Feedthrough b 60 dB(1,2) VCC Power Supply Rejection b 60 dB(1,2) Input Resistance DC Input Leakage g 1.0 Voltage on Analog Input Pin Sampling Capacitor 750 1.2K X(4) 0 g 3.0 mA ANGND b 0.5 VREF a 0.5 V(5) 3.0 pF *An ``LSB'' as used here has a value of approximately 5 mV. NOTES: 1. These values are expected for most parts at 25 C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode. 27 8XC196NT 8-BIT MODE A/D OPERATING CONDITIONS Symbol Description Min Max Units TA Ambient Temperature 0 a 70 C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V(1) TSAM Sample Time 1.0 TCONV Conversion Time FOSC Oscillator Frequency ms(2) 7 20 ms(2) 4.0 20 MHz NOTES: 1. VREF must be within 0.5V of VCC. 2. The value of ADTIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS Parameter (Using Above Operating Conditions)(6) Typ*(1) Resolution Absolute Error Full Scale Error g 0.5 Zero Offset Error g 0.5 Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability g 0.25 Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 Off Isolation Feedthrough VCC Power Supply Rejection b 60 Input Resistance Units* 256 8 256 8 Level Bits 0 g 1.0 LSBs LSBs LSBs 0 g 1.0 LSBs b 0.5 a 0.5 LSBs 0 g 1.0 LSBs LSBs(1) 0 LSB/C(1) LSB/C(1) LSB/C(1) dB(1,2,3) dB(1,2) dB(1,2) 750 g 1.0 Voltage on Analog Input Pin Sampling Capacitor Max b 60 b 60 DC Input Leakage Min 1.2K 0 g 3.0 mA ANGND b 0.5 VREF a 0.5 V(5) 3.0 *An ``LSB'' as used here has a value of approximately 5 mV. NOTES: 1. These values are expected for most parts at 25 C, but are not tested or guaranteed. 2. DC to 100 KHz. 3. Multiplexer break-before-make is guaranteed. 4. Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode. 28 X(4) pF 8XC196NT OTPROM SPECIFICATIONS OPERATING CONDITIONS Min Max Units TA Symbol Ambient Temperature During Programming Description 20 30 C VCC Supply Voltage During Programming 4.5 5.5 V(1) VREF Reference Supply Voltage During Programming 4.5 5.5 V(1) VPP Programming Voltage 12.25 12.75 V(2) VEA EA Pin Voltage 12.25 12.75 V(2) FOSC Oscillator Frequency during Auto and Slave Mode Programming 6.0 8.0 MHz FOSC Oscillator Frequency during Run-Time Programming 6.0 20.0 MHz NOTES: 1. VCC and VREF should nominally be at the same voltage during programming. 2. VPP and VEA must never exceed the maximum specification, or the device may be damaged. 3. VSS and ANGND should nominally be at the same potential (0V). 4. Load capacitance during Auto and Slave Mode programming e 150 pF. AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) Symbol Parameter Min Max Units TAVLL Address Setup Time 0 TOSC TLLAX Address Hold Time 100 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TLLLH PALE Pulse Width 50 TOSC TPLPH PROG Pulse Width(2) 50 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHLL PROG High to next PALE Low 220 TOSC TPHDX Word Dump Hold Time TPHPL PROG High to next PROG Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPLDV PROG Low to Word Dump Valid TSHLL RESET High to First PALE Low TPHIL PROG High to AINC Low TILIH AINC Pulse Width TILVH TILPL TPHVL PROG High to PVER Valid 50 50 1100 TOSC TOSC TOSC 0 TOSC 240 TOSC PVER Hold after AINC Low 50 TOSC AINC Low to PROG Low 170 TOSC 220 TOSC NOTES: 1. Run-time programming is done with FOSC e 6.0 MHz to 10.0 MHz, VCC, VPD, VREF e 5V g 0.5V, TC e 25 C g 5 C and VPP e 12.5V g 0.25V. For run-time programming over a full operating range, contact factory. 2. This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm. 29 8XC196NT DC OTPROM PROGRAMMING CHARACTERISTICS Symbol Parameter IPP VPP Programming Supply Current Min Max Units 200 mA NOTE: Do not apply VPP unti VCC is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. OTPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 272267 - 21 NOTE: P3.0 must be high (``1'') SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT 272267 - 22 NOTE: P3.0 must be low (``0'') 30 8XC196NT SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT 272267 - 23 This data sheet (272267-004) applies to devices marked with a ``D'' at the end of the top side tracking number. The following are differences between the 272267003 and 272267-004 datasheets: 1. Changed all references of ``EPROM'' to ``OTPROM''. 8XC196NT Design Considerations 2. 1. When operating in bus timing modes 1 or 2, the upper and lower address/data lines must be latched. Even in 8-bit bus mode, the upper address lines must be latched. In modes 0 and 3, the upper address lines DO NOT NEED to be latched in 8-bit bus width mode. But in 16-bit buswidth mode the upper address lines need to be latched. 3. 4. 5. 6. 7. 8XC196NT ERRATA see Faxback Y2344 8. 1. ILLEGAL Opcode interrupt vector. 2. Aborted Interrupt vectors to lowest priority. 9. 3. PTS Request during Interrupt latency. 10. DATA SHEET REVISION HISTORY This datasheet applies to devices marked with a ``D'' at the end of the topside tracking number. The topside tracking number consists of nine characters and is the second line on the top side of the device. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. 11. 12. 13. 14. Added all the Slave Port pins to the package diagram and pin descriptions. Added INTOUT pin to pin descriptions. Changed ILI1 (input leakage current for Port 0) from g 1 mA to g 3 mA. Removed TLLYV from AC characterisics and waveform diagrams. TRLCL in Mode 0 and 3, changed from a 4 ns min. to b 5 ns min. TWHQX in Mode 0 and 3, changed from TOSC b 30 min. to TOSC b 35 min. Clarified the Ready waveform timings for Mode 0 and 3, by adding `` a 2 TOSC*''. TLHLL in Mode 1, changed from TOSC b 10 min. to TOSC b 20 min. TAVLL in Mode 1, changed from 0.5 TOSC b 15 min. to 0.5 TOSC b 20 min. TLLAX in Mode 1, changed from 0.5 TOSC b 20 min. to 0.5 TOSC b 25 min. TLHLL in Mode 2, changed from TOSC b 10 min. to TOSC b 20 min. TXLXL and TXLXH for the Serial Port timings were changed to reflect the minimum baudrate for receive and transmit modes. Added the 8XC196NT ERRATA section. 31