AFE5805ZCF - Texas Instruments - Datasheet.Directory

LNA8Channels

SPI

IN1

IN8

.CH1

LVDS

OUT

CH8

VCA/PGA

Clamp

and

LPF

Logic/Controls

Reference

CWSwitchMatrix(8 10)´

I (10)

OUT

12-Bit

ADC

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND

0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel

Check for Samples: AFE5805

1FEATURES DESCRIPTION

23• 8-Channel Complete Analog Front-End: The AFE5805 is a complete analog front-end device

specifically designed for ultrasound systems that

– LNA, VCA, PGA, LPF, and ADC require low power and small size.

• Ultra-Low, Full-Channel Noise: The AFE5805 consists of eight channels, including a

– 0.85nV/√Hz (TGC) low-noise amplifier (LNA), voltage-controlled

– 1.1nV/√Hz (CW) attenuator (VCA), programmable gain amplifier

• Low Power: (PGA), low-pass filter (LPF), and a 12-bit

analog-to-digital converter (ADC) with low voltage

– 122mW/Channel (40MSPS) differential signaling (LVDS) data outputs.

– 74mW/Channel (CW Mode) The LNA gain is set for 20dB gain, and has excellent

• Low-Noise Pre-Amp (LNA): noise and signal handling capabilities, including fast

– 0.75nV/√Hz overload recovery. VCA gain can vary over a 46dB

– 20dB Fixed Gain range with a 0V to 1.2V control voltage common to all

channels of the AFE5805.

– 250mVPP Linear Input Range

• Variable-Gain Amplifier: The PGA can be programmed for gains of 20dB,

25dB, 27dB, and 30dB. The internal low-pass filter

– Gain Control Range: 46dB can also be programmed to 10MHz or 15MHz.

• PGA Gain Settings: 20dB, 25dB, 27dB, 30dB The LVDS outputs of the ADC reduce the number of

• Low-Pass Filter: interface lines to an ASIC or FPGA, thereby enabling

– Selectable BW: 10MHz, 15MHz the high system integration densities desired for

– 2nd-Order portable systems. The ADC can either be operated

with internal or external references. The ADC also

• Gain Error: ±0.5dB features a signal-to-noise ratio (SNR) enhancement

• Channel Matching: ±0.25dB mode that can be useful at high gains.

• Distortion, HD2: –65dBFS at 5MHz The AFE5805 is available in a 15mm × 9mm,

• Clamping Control 135-ball BGA package that is Pb-free

• Fast Overload Recovery: Two Clock Cycles (RoHS-compliant) and green. It is specified for

operation from 0°C to +70°C.

• 12-Bit Analog-to-Digital Converter:

– 10MSPS to 50MSPS

– 69.5dB SNR at 10MHz

– Serial LVDS Interface

• Integrated CW Switch Matrix

• 15mm × 9mm, 135-BGA Package:

– Pb-Free (RoHS-Compliant) and Green

APPLICATIONS

• Medical Imaging, Ultrasound

– Portable Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Infineon is a registered trademark of Infineon Technologies.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGING/ORDERING INFORMATION(1) (2)

OPERATING

PACKAGE TEMPERATURE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY ECO STATUS

AFE5805ZCFR Tape and Reel, 1000

AFE5805 mFBGA-135 ZCF 0°C to +70°C AFE5805ZCFT Tape and Reel, 250 Pb-Free, Green

AFE5805ZCF Tray, 160

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content

can be accessed at www.ti.com/leadfree.

GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including

bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion

dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that

does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering

processes.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. AFE5805 UNIT

Supply voltage range, AVDD1 –0.3 to +3.9 V

Supply voltage range, AVDD2 –0.3 to +3.9 V

Supply voltage range, AVDD_5V –0.3 to +6 V

Supply voltage range, DVDD –0.3 to +3.9 V

Supply voltage range, LVDD –0.3 to +2.2 V

Voltage between AVSS1 and LVSS –0.3 to +0.3 V

Voltage at analog inputs –0.3 to minimum [3.6, (AVDD2 + 0.3)] V

External voltage applied to REFT-pin –0.3 to +3 V

External voltage applied to REFB-pin –0.3 to +2 V

Voltage at digital inputs –0.3 to minimum [3.9, (AVDD2 + 0.3)] V

Peak solder temperature(2) +260 °C

Maximum junction temperature, TJ+125 °C

Storage temperature range –55 to +150 °C

Operating temperature range 0 to +70 °C

HBM 2000 V

ESD ratings CDM 1000 V

MM 100 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not supported.

(2) Device complies with JSTD-020D.

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SBOS421D –MARCH 2008–REVISED MARCH 2010

ELECTRICAL CHARACTERISTICS

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),

VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer

setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted. AFE5805

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PREAMPLIFIER (LNA)

Gain A SE-input to differential output 20 dB

Input voltage VIN Linear operation (HD2 ≤–40dB) 250 mVPP

blankMaximum input voltage Limited by internal diodes 600 mVPP

Input voltage noise (TGC) en(RTI) RS= 0Ω, f = 1MHz 0.75 nV/√Hz

Input current noise In(RTI) 3 pA/√Hz

Common-mode voltage, input VCMI Internally generated 2.4 V

Bandwidth BW Small-signal, –3dB 70 MHz

Input resistance(1) At f = 4MHz 8 kΩ

Input capacitance(1) Includes internal ESD and clamping diodes 16 pF

FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC)

Input voltage noise (TGC) enRS= 0Ω, f = 2MHz, PGA = 30dB 0.85 nV/√Hz

RS= 0Ω, f = 2MHz, PGA = 20dB 1.08 nV/√Hz

Noise figure NF RS= 200Ω, f = 5MHz 1.5 dB

Low-pass filter bandwidth LPF at –3dB, selectable through SPI 10, 15 MHz

Bandwidth tolerance ±10 %

High-pass filter HPF (First-order, due to internal ac-coupling) 200 kHz

Group delay variation ±3 ns

Overload recovery ≤6dB overload to within 1% 2 Clock Cycles

ACCURACY

Gain (PGA) Selectable through SPI 20, 25, 27, 30 dB

Total gain, max(2) LNA + PGA gain, VCNTL = 1.2V 48 49.5 51 dB

Gain range VCNTL = 0V to 1.2V 46 dB

VCNTL = 0.1V to 1.0V 40 dB

Gain error, absolute(3) 0V < VCNTL < 0.1V ±0.5 dB

0.1V < VCNTL < 1.0V –1.5 ±0.5 +1.5 dB

1.0V < VCNTL < 1.2V ±0.5 dB

Gain matching Channel-to-channel –0.5 ±0.25 +0.5 dB

Offset error VCNTL = 1.0V, PGA = 30dB –39 +39 LSB

Offset error drift (tempco) ±5 ppm/°C

Clamp level CL = 0 1.7 VPP

CL = 1 (clamp disabled) 2.8 VPP

GAIN CONTROL (VCA)

Input voltage range VCNTL Gain range = 46dB 0 to 1.2 V

Gain slope VCNTL = 0.1V to 1.0V 44.4 dB/V

Input resistance 25 kΩ

Response time VCNTL = 0V to 1.2V step; to 90% signal 0.5 ms

DYNAMIC PERFORMANCE

Signal-to-noise ratio SNR fIN = 2MHz; –1dBFS, PGA = 30dB 59.8 dBFS

fIN = 5MHz; –1dBFS, PGA = 30dB 59.6 dBFS

fIN = 10MHz; –1dBFS, PGA = 30dB 58.8 dBFS

(1) See Figure 33.

(2) Excludes digital gain within ADC.

(3) Excludes error of internal reference.

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ELECTRICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),

VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer

setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted. AFE5805

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC PERFORMANCE (continued)

Second-harmonic distortion HD2 fIN = 2MHz; –1dBFS, PGA = 30dB –70 dBFS

fIN = 5MHz; –1dBFS, PGA = 30dB –54 –65 dBFS

fIN = 5MHz; –6dBFS, PGA = 20dB –61 –69 dBFS

Third-harmonic distortion HD3 fIN = 2MHz; –1dBFS, PGA = 30dB –58 dBFS

fIN = 5MHz; –1dBFS, PGA = 30dB –51 –59 dBFS

fIN = 5MHz; –6dBFS, PGA = 20dB –56 –78 dBFS

f1= 4.99MHz at –6dBFS,

Intermodulation distortion IMD3 58.5 dBc

f2= 5.01MHz at –32dBFS

Crosstalk fIN = 5MHz, –1dBFS, PGA = 30dB –67 dBc

CW—SIGNAL CHANNELS

Input voltage noise (CW) enRS= 0Ω, f = 1MHz 1.1 nV/√Hz

Output noise correlation factor Summing of eight channels 0.6 dB

Output transconductance At VIN = 100mVPP 14 15.6 18 mA/V

(IOUT/VIN)

Dynamic CW output current, IOUTAC 2.9 mAPP

maximum

Static CW output current (sink) IOUTDC 0.9 mA

Output common-mode VCM 2.5 V

voltage(4)

Output impedance 50 kΩ

Output capacitance 10 pF

INTERNAL REFERENCE VOLTAGES (ADC)

Reference top VREFT 0.5 V

Reference bottom VREFB 2.5 V

VREFT – VREFB 1.95 2 2.05 V

Common-mode voltage VCM 1.425 1.5 1.575 V

(internal)

VCM output current ±2 mA

EXTERNAL REFERENCE VOLTAGES (ADC)

Reference top VREFT 2.4 2.5 2.6 V

Reference bottom VREFB 0.4 0.5 0.6 V

VREFT – VREFB 1.9 2.1 V

Switching current(5) 2.5 mA

(4) CW outputs require an externally applied bias voltage of +2.5V.

(5) Current drawn by the eight ADC channels from the external reference voltages; sourcing for VREFT, sinking for VREFB.

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SBOS421D –MARCH 2008–REVISED MARCH 2010

ELECTRICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),

VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer

setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted. AFE5805

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER SUPPLY

Supply Voltages

AVDD1, AVDD2, DVDD Operating 3.15 3.3 3.47 V

AVDD_5V Operating 4.75 5 5.25 V

LVDD 1.7 1.8 1.9 V

Supply Currents

IAVDD1 (ADC) at 40MSPS 99 110 mA

IAVDD2 (VCA) TGC mode 146 156 mA

CW mode 79 85 mA

IAVDD_5V (VCA) TGC mode 8 10 mA

CW mode 55 61 mA

IDVDD (VCA) 1.5 3.0 mA

ILVDD (ADC) At 40MSPS 70 80 mA

Power dissipation, total All channels, TGC mode, no signal 980 1080 mW

All channels, CW mode , no signal(6) 580 620 mW

TGC mode, no clock applied, no signal 615 mW

POWER-DOWN MODES

Power-down dissipation, total Complete power-down mode 64 85 mW

Power-down response time(7) 1.0 ms

Power-up response time(7) PD to valid output (90% level) 50 ms

Power-down dissipation(7) Partial power-down mode 233 mW

THERMAL CHARACTERISTICS

Temperature range 0 +70 °C

Thermal resistance TJA 32 °C/W

TJC 4.2 °C/W

(6) The ADC section is powered down during CW mode operation.

(7) With VCA_PD and ADC_PD pins = high. The ADC_PD pin is configured for partial power-down (see the Power-Down Modes section).

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DIGITAL CHARACTERISTICS

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level

'0' or '1'. At CLOAD = 5pF(1), IOUT = 3.5mA(2), RLOAD = 100Ω(2), and no internal termination, unless otherwise noted.

AFE5805

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS

High-level input voltage 1.4 3.3 V

Low-level input voltage 0 0.3 V

High-level input current 10 mA

Low-level input current(3) –10 mA

Input capacitance 3 pF

LVDS OUTPUTS

High-level output voltage 1375 mV

Low-level output voltage 1025 mV

Output differential voltage, |VOD| 350 mV

VOS output offset voltage(2) Common-mode voltage of OUTP and OUTM 1200 mV

Output capacitance inside the device,

Output capacitance 2 pF

from either output to ground

FCLKP and FCLKM 10 1x (clock rate) 50 MHz

LCLKP and LCLKM 60 6x (clock rate) 300 MHz

CLOCK

Clock input rate 10 50 MSPS

Clock duty cycle 50 %

Clock input amplitude, differential Sine-wave, ac-coupled 3 VPP

(VCLKP – VCLKM)

LVPECL, ac-coupled 1.6 VPP

LVDS, ac-coupled 0.7 VPP

Clock input amplitude, single-ended

(VCLKP)

High-level input voltage, VIH CMOS 2.2 V

Low-level input voltage, VIL CMOS 0.6 V

(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(3) Except pin J3 (INT/EXT), which has an internal pull-up resistor (52kΩ) to 3.3V.

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12-Bit

ADC

PLL

Serializer

1xADCLK

6xADCLK

IN1 OUT1P

OUT1M

LCLKP

LCLKM

FCLKP

FCLKM

12xADCLK

12-Bit

ADC

Serializer

DigitalLPFPGA

Digital

Reference

REFT

INT/EXT

CW[0:9]

REFB

OUT8P

OUT8M

ISET

Registers

SDATA

SCLK

ADC

Control

Clock

Buffer

CLKP

AVSS2

AVDD2

(3.3V)

CLKM

AVDD1

(3.3V)

LVDD

(1.8V)

Power-

Down

TestPatterns

DriveCurrent

OutputFormat

DigitalGain

(0dBto12dB)

VCALNA

IN8

VCNTL

LPFPGAVCA

CWSwitchMatrix

(8x10)

LNA

Channels

2to7

ADC_RESET

SCLK

AVDD_5V

DVDD(3.3V)

AVSS1

20,25,27

30dB 10,15MHz

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

FUNCTIONAL BLOCK DIAGRAM

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Columns

1 3 52 4 6

VBL8VBL4

VBL2 DNC

VBL3VBL1

AVSS2

AVSS2AVDD2 DVDDCW9

AVSS2

AVSS2VCNTL DVDDCW8

AVSS2AVSS2AVDD_5V AVSS2CW7

IN8

IN4

IN2 VCA_PDIN3

IN1

87 9

VBL5VBL7 VBL6

CW0

AVSS2 AVDD2

CW1

AVSS2 VB2

CW2VB4 AVDD_5V

IN5

IN7 IN6

AVSS2AVSS2

AVDD2 AVSS2

VCMCW5

SCLK

VCA_CSDNC RSTADS_PD

AVSS2

AVSS2AVDD1 AVSS2

AVSS1

AVDD1DNCDNC AVDD1AVDD1CLKM

AVSS2

VB1 AVSS2VB5

CW6

Rows

AVSS2

VB3

AVSS2

CW4VREFL AVDD2

ADS_

RESET

CS SDATA

REFB

AVDD1 REFT

ISETAVDD1 CM

CW3

VREFH VB6

AVSS1AVSS1

DNC AVSS1

AVSS1DNC

LVDD

LVSSLCLKM LVSSLCLKP

OUT5P

OUT1POUT3P LVDDOUT4P

OUT5MOUT1MOUT3M LVSSOUT2MOUT4M

AVSS1

AVDD1 AVSS1AVSS1

CLKP

LVSS

OUT2P

DNC

INT/EXT

DNCAVSS1 DNC

FCLKP

LVDD FCLKM

OUT8P

OUT6P OUT7P

OUT8MOUT6M OUT7M

EN_SM

AVSS1 AVDD1

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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PIN CONFIGURATION

ZCF PACKAGE

135-BGA

BOTTOM VIEW

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ROUT8M OUT7M OUT6M OUT5M LVSS OUT1M OUT2M OUT3M OUT4M

9 8 7 6 5 4 3 2 1

POUT8P OUT7P OUT6P OUT5P LVDD OUT1P OUT2P OUT3P OUT4P

NFCLKP FCLKM LVDD LVDD LVSS LVSS LVSS LCLKM LCLKP

MDNC DNC AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 DNC DNC

LEN_SM AVDD1 AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 AVDD1 CLKP

KISET CM AVDD1 AVDD1 AVDD1 DNC AVDD1 DNC CLKM

JREFB REFT AVDD1 AVSS2 AVSS2 AVSS2 INT/EXT AVDD1 AVSS1

HADS_RESET SDATA CS SCLK RST VCA_CS DNC DNC ADS_PD

GCW4 AVDD2 VREFL AVSS2 AVSS2 AVSS2 VCM AVDD2 CW5

FCW3 VB6 VREFH AVSS2 AVSS2 AVSS2 VB5 VB1 CW6

ECW2 AVDD_5V VB4 AVSS2 AVSS2 AVSS2 VB3 AVDD_5V CW7

DCW1 VB2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 VCNTL CW8

CCW0 AVDD2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 AVDD2 CW9

BVBL5 VBL6 VBL7 VBL8 DNC VBL4 VBL3 VBL2 VBL1

AIN5 IN6

Legend: AVDD1 +3.3V;Analog

AVDD2 +3.3V;Analog

+3.3V;Analog

+1.8V;Digital

+5V;Analog

DVDD

LVDD

AVDD_5V

AnalogGround

DigitalGround

AVSS1

AVSS2

LVSS

IN7 IN8 VCA_PD IN4 IN3 IN2 IN1

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SBOS421D –MARCH 2008–REVISED MARCH 2010

ZCF PACKAGE

135-BGA

CONFIGURATION MAP (TOP VIEW)

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Table 1. TERMINAL FUNCTIONS

PIN NO. PIN NAME FUNCTION DESCRIPTION

H7 CS Input Chip select for serial interface; active low

H1 ADS_PD Input Power-down pin for ADS; active high. See the Power-Down Modes section for more information.

H9 ADS_RESET Input RESET input for ADS; active low

H6 SCLK Input Serial clock input for serial interface

H8 SDATA Input Serial data input for serial interface

J2, L2, K7, J7, AVDD1 POWER 3.3V analog supply for ADS

K3, L8, K5, K6

L3, M3, L4, M4,

L5, M5, L6, M6, AVSS1 GND Analog ground for ADS

L7, M7, J1

P5, N6, N7 LVDD POWER 1.8V digital supply for ADS

N3, N4, N5, R5 LVSS GND Digital ground for ADS

C5, D5 DVDD POWER 3.3V digital supply for the VCA; connect to the 3.3V analog supply (AVDD2).

C2, C8, G2, G8 AVDD2 POWER 3.3V analog supply for VCA

E2, E8 AVDD_5V POWER 5V supply for VCA

C3, D3, C4, D4,

E4, F4, G4, E5,

F5, G5, C6, D6, AVSS2 GND Analog ground for VCA

E6, F6, G6, C7,

D7, J4, J5, J6

K1 CLKM Input Negative clock input for ADS (connect to Ground in single-ended clock mode)

L1 CLKP Input Positive clock input for ADS

K8 CM Input/Output 1.5V common-mode I/O for ADS. Becomes input pin in one of the external reference modes.

C9 CW0 Output CW output 0

D9 CW1 Output CW output 1

E9 CW2 Output CW output 2

F9 CW3 Output CW output 3

G9 CW4 Output CW output 4

G1 CW5 Output CW output 5

F1 CW6 Output CW output 6

E1 CW7 Output CW output 7

D1 CW8 Output CW output 8

C1 CW9 Output CW output 9

L9 EN_SM Input Enables access to the VCA register. Active high. Connect permanently to 3.3V (AVDD1).

N8 FCLKM Output LVDS frame clock (negative output)

N9 FCLKP Output LVDS frame clock (positive output)

A1 IN1 Input LNA input Channel 1

A2 IN2 Input LNA input Channel 2

A3 IN3 Input LNA input Channel 3

A4 IN4 Input LNA input Channel 4

A9 IN5 Input LNA input Channel 5

A8 IN6 Input LNA input Channel 6

A7 IN7 Input LNA input Channel 7

A6 IN8 Input LNA input Channel 8

J3 INT/EXT Input Internal/ external reference mode select for ADS; internal = high (internal pull-up resistor)

K9 ISET Input Current bias pin for ADS. Requires 56kΩto ground.

N2 LCLKM Output LVDS bit clock (6x); negative output

N1 LCLKP Output LVDS bit clock (6x); positive output

R4 OUT1M Output LVDS data output (negative), Channel 1

P4 OUT1P Output LVDS data output (positive), Channel 1

R3 OUT2M Output LVDS data output (negative), Channel 2

P3 OUT2P Output LVDS data output (positive), Channel 2

R2 OUT3M Output LVDS data output (negative), Channel 3

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Table 1. TERMINAL FUNCTIONS (continued)

PIN NO. PIN NAME FUNCTION DESCRIPTION

P2 OUT3P Output LVDS data output (positive), Channel 3

R1 OUT4M Output LVDS data output (negative), Channel 4

P1 OUT4P Output LVDS data output (positive), Channel 4

R6 OUT5M Output LVDS data output (negative), Channel 5

P6 OUT5P Output LVDS data output (positive), Channel 5

R7 OUT6M Output LVDS data output (negative), Channel 6

P7 OUT6P Output LVDS data output (positive), Channel 6

R8 OUT7M Output LVDS data output (negative), Channel 7

P8 OUT7P Output LVDS data output (positive), Channel 7

R9 OUT8M Output LVDS data output (negative), Channel 8

P9 OUT8P Output LVDS data output (positive), Channel 8

J9 REFB Input/Output 0.5V Negative reference of ADS. Decoupling to ground. Becomes input in external ref mode.

J8 REFT Input/Output 2.5V Positive reference of ADS. Decoupling to ground. Becomes input in external ref mode.

H5 RST Input RESET input for VCA. Connect to the VCA_CS pin (H4).

H4 VCA_CS Output Connect to RST–pin (H5)

F2 VB1 Output Internal bias voltage. Bypass to ground with 2.2mF.

D8 VB2 Output Internal bias voltage. Bypass to ground with 0.1mF.

E3 VB3 Output Internal bias voltage. Bypass to ground with 0.1mF.

E7 VB4 Output Internal bias voltage. Bypass to ground with 0.1mF

F3 VB5 Output Internal bias voltage. Bypass to ground with 0.1mF.

F8 VB6 Output Internal bias voltage. Bypass to ground with 0.1mF.

B1 VBL1 Input Complementary LNA input Channel 1; bypass to ground with 0.1mF.

B2 VBL2 Input Complementary LNA input Channel 2; bypass to ground with 0.1mF.

B3 VBL3 Input Complementary LNA input Channel 3; bypass to ground with 0.1mF.

B4 VBL4 Input Complementary LNA input Channel 4; bypass to ground with 0.1mF.

B9 VBL5 Input Complementary LNA input Channel 5; bypass to ground with 0.1mF.

B8 VBL6 Input Complementary LNA input Channel 6; bypass to ground with 0.1mF.

B7 VBL7 Input Complementary LNA input Channel 7; bypass to ground with 0.1mF.

B6 VBL8 Input Complementary LNA input Channel 8; bypass to ground with 0.1mF.

A5 VCA_PD Input Power-down pin for VCA; low = normal mode, high = power-down mode.

G3 VCM Output VCA reference voltage. Bypass to ground with 0.1mF.

D2 VCNTL Input VCA control voltage input

F7 VREFH Output Clamp reference voltage (2.7V). Bypass to ground with 0.1mF.

G7 VREFL Output Clamp reference voltage (2.0V). Bypass to ground with 0.1mF.

B5, H2, H3, K2,

K4, M1, M2, DNC Do not connect

M8, M9

Product Folder Link(s): AFE5805

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

Sample n Sample n+12

tPROP

t (A)

12clockslatency

ADC

Input(1)

Clock

Input

6XFCLK

LCLKM

LCLKP

1XFCLK

FCLKM

FCLKP

SERIAL DATA

OUTP

OUTM

tSAMPLE

Sample n+13

tH1 tSU1 tH2 tSU2

LCLKM

LCLKP

OUTM

OUTP

t =min(t ,t )

SU SU1 SU2

H H1 H2

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

LVDS TIMING DIAGRAM

(1) Referenced to ADC Input (internal node) for illustration purposes only.

DEFINITION OF SETUP AND HOLD TIMES

TIMING CHARACTERISTICS(1)

AFE5805

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tD(A) ADC aperture delay 1.5 4.5 ns

Aperture delay variation Channel-to-channel within the same device (3s) ±20 ps

tJAperture jitter 400 fS, rms

Time to valid data after coming out of 50 ms

COMPLETE POWER-DOWN mode

Time to valid data after coming out of PARTIAL

tWAKE Wake-up time POWER-DOWN mode (with clock continuing to 2 ms

run during power-down)

Time to valid data after stopping and restarting 40 ms

the input clock Clock

Data latency 12 cycles

(1) Timing parameters are ensured by design and characterization; not production tested.

Product Folder Link(s): AFE5805

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)

Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling

frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise noted.

AFE5805

40MSPS 50MSPS

PARAMETER TEST CONDITIONS(5) MIN TYP MAX MIN TYP MAX UNIT

tSU Data setup time(6) Data valid(7) to zero-crossing of LCLKP 0.67 0.47 ns

Zero-crossing of LCLKP to data becoming

tHData hold time(6) 0.85 0.65 ns

invalid(7)

ADC input clock rising edge cross-over to

tPROP Clock propagation delay 10 14 16.6 10 12.5 14.1 ns

output clock (FCLKP) rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle 45.5 50 53 45 50 53.5

(LCLKP – LCLKM)

Bit clock cycle-to-cycle jitter 250 250 ps, pp

Frame clock cycle-to-cycle jitter 150 150 ps, pp

Rise time is from –100mV to +100mV

tRISE, tFALL Data rise time, data fall time 0.09 0.2 0.4 0.09 0.2 0.4 ns

Fall time is from +100mV to –100mV

tCLKRISE, Output clock rise time, output Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 ns

tCLKFALL clock fall time Fall time is from +100mV to –100mV

(1) All characteristics are at the maximum rated speed for each speed grade.

(2) Timing parameters are ensured by design and characterization; not production tested.

(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5) Measurements are done with a transmission line of 100Ωcharacteristic impedance between the device and the load.

(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.

LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)

Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling

frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise noted.

AFE5805

30MSPS 20MSPS 10MSPS

PARAMETER TEST CONDITIONS(5) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Data valid(7) to zero-crossing of

tSU Data setup time(6) 0.8 1.5 3.7 ns

LCLKP

Zero-crossing of LCLKP to data

tHData hold time(6) 1.2 1.9 3.9 ns

becoming invalid(7)

ADC input clock rising edge

tPROP Clock propagation delay cross-over to output clock (FCLKP) 9.5 13.5 17.3 9.5 14.5 17.3 10 14.7 17.1 ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle 46.5 50 52 48 50 51 49 50 51

(LCLKP – LCLKM)

Bit clock cycle-to-cycle 250 250 750 ps, pp

jitter

Frame clock cycle-to-cycle 150 150 500 ps, pp

jitter

tRISE, Data rise time, data fall Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tFALL time Fall time is from +100mV to –100mV

tCLKRISE, Output clock rise time, Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tCLKFALL output clock fall time Fall time is from +100mV to –100mV

(1) All characteristics are at the speeds other than the maximum rated speed for each speed grade.

(2) Timing parameters are ensured by design and characterization; not production tested.

(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5) Measurements are done with a transmission line of 100Ωcharacteristic impedance between the device and the load.

(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.

Product Folder Link(s): AFE5805

V (V)

CNTL

01.2

Gain(dB)

0.60.40.2 0.8 1.0

-40°C

+50 C°

+85 C°

+25 C°

-4

-10

0.0 0.1 1.2

Gain(dB)

V (V)

CNTL

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

30dB

25dB

20dB

27dB

3000

2500

2000

1500

1000

500

Channel

Gain(dB)

-0.50

0.50

-0.40

-0.30

-0.20

-0.10

0.10

0.20

0.30

0.40

0.45

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

-0.45

Channel-to-Channel

3000

2500

2000

1500

1000

500

Channel

Gain(dB)

-0.50

0.50

-0.40

-0.30

-0.20

-0.10

0.10

0.20

0.30

0.40

0.45

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

-0.45

Channel-to-Channel

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

TYPICAL CHARACTERISTICS

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

GAIN vs VCNTL GAIN vs VCNTL vs TEMPERATURE

Figure 1. Figure 2.

GAIN MATCH AT VCNTL = 0.1V GAIN MATCH AT VCNTL = 0.6V

Figure 3. Figure 4.

Product Folder Link(s): AFE5805

4000

3500

3000

2500

2000

1500

1000

500

Channel

Code

2072

2024

2032

2048

2056

2060

2068

2064

2052

2044

2040

2036

2028

3500

3000

2500

2000

1500

1000

500

Channel

Gain(dB)

-0.50

0.50

-0.40

-0.30

-0.20

-0.10

0.10

0.20

0.30

0.40

0.45

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

-0.45

Channel-to-Channel

V (V)

CNTL

01.2

SNRandSINAD(dBFS)

0.30.20.1 0.4 1.10.5 1.00.90.80.70.6

SNR

SINAD

Input= 45dBm

Frequency=5MHz

PGA=30dB

PGA=20dB

1.2

1.0

0.8

0.6

0.4

0.2

GainSetting(PGA)

20dB

Noise(nV/ )ÖHz

25dB 30dB27dB

R =0

V =1.2V

CNTL

2MHz

5MHz

10MHz

2MHz

10MHz

5MHz

130

120

110

100

V (V)

CNTL

01.2

Noise(nV/ )ÖHz

0.30.20.1 0.4 1.10.5 1.00.90.80.70.6

Frequency=2MHz

PGA=30dB

PGA=20dB

130

120

110

100

V (V)

CNTL

01.2

Noise(nV/ )ÖHz

0.30.20.1 0.4 1.10.5 1.00.90.80.70.6

Frequency=5MHz

PGA=30dB

PGA=20dB

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

GAIN MATCH AT VCNTL = 1.0V OUTPUT OFFSET

Figure 5. Figure 6.

SNR AND SINAD vs VCNTL INPUT-REFERRED NOISE vs PGA

Figure 7. Figure 8.

INPUT-REFERRED NOISE vs VCNTL INPUT-REFERRED NOISE vs VCNTL

Figure 9. Figure 10.

Product Folder Link(s): AFE5805

300

250

200

150

100

V (V)

CNTL

01.2

Noise(nV/ )ÖHz

0.30.20.1 0.4 1.10.5 1.00.90.80.70.6

Frequency=2MHz

PGA=30dB

PGA=20dB

300

250

200

150

100

V (V)

CNTL

01.2

Noise(nV/ )ÖHz

0.30.20.1 0.4 1.10.5 1.00.90.80.70.6

Frequency=5MHz

PGA=30dB

PGA=20dB

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

Frequency(MHz)

110

Noise(nV/ )ÖHz

R =1kW

R =400W

R =200W

R =50W

V =1.2V

CNTL

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Frequency(MHz)

110

Noise(nV/ )ÖHz

R =1kW

R =400W

R =200W

SR =50W

V =1.2V

CNTL

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

CurrentNoise(pA/ )ÖHz

Frequency(MHz)

R =

S400W

R =

S1kW

R =200W

V =1.2V

CNTL

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Frequency(MHz)

110

NoiseFigure(dB)

R =1kW

R =400W

R =200W

R =50W

PGA=30dB

V =1.2V

CNTL

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

OUTPUT-REFERRED NOISE vs VCNTL OUTPUT-REFERRED NOISE vs VCNTL

Figure 11. Figure 12.

OUTPUT-REFERRED NOISE vs FREQUENCY vs RSINPUT-REFERRED NOISE vs FREQUENCY vs RS

Figure 13. Figure 14.

CURRENT NOISE vs FREQUENCY OVER RSOURCE NOISE FIGURE vs FREQUENCY vs RS

Figure 15. Figure 16.

Product Folder Link(s): AFE5805

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

Frequency(Hz)

100k 20M

Noise(nV/ )ÖHz

10M1M

4000

3500

3000

2500

2000

1500

1000

500

Channel

Transconductance(mA/V)

14.0

17.0

14.2

14.6

15.0

15.6

16.0

16.4

16.8

16.6

16.2

15.8

15.4

15.2

14.8

14.4

-50

V (V)

CNTL

0.6 1.2

Distortion(dBFS)

0.80.7 0.9 1.0 1.1

PGA=20dB

Output= 6dBFS-

2MHz

5MHz

10MHz

V (V)

CNTL

0.6 1.2

Distortion(dBFS)

0.80.7 0.9 1.0 1.1

PGA=20dB

Output= 6dBFS-

2MHz

5MHz

10MHz

V (V)

CNTL

0.6 1.2

Distortion(dBFS)

0.80.7 0.9 1.0 1.1

PGA=30dB

Output= 1dBFS-

2MHz

5MHz

10MHz

V (V)

CNTL

0.6 1.2

Distortion(dBFS)

0.80.7 0.9 1.0 1.1

PGA=30dB

Output= 1dBFS-

2MHz

5MHz

10MHz

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

CW INPUT-REFERRED NOISE vs FREQUENCY CW ACCURACY

Figure 17. Figure 18.

2ND HARMONIC vs VCNTL vs FREQUENCY 3RD HARMONIC vs VCNTL vs FREQUENCY

Figure 19. Figure 20.

2ND HARMONIC vs VCNTL vs FREQUENCY 3RD HARMONIC vs VCNTL vs FREQUENCY

Figure 21. Figure 22.

Product Folder Link(s): AFE5805

OutputLevel(dBFS)

-40 0

Distortion(dBc)

-30 -20 -10

PGA=30dB

Frequency=5MHz

V =0.7V

CNTL

V =1V

CNTL

V =0.4V

CNTL

OutputLevel(dBFS)

-40 0

Distortion(dBc)

-30 -20 -10

PGA=30dB

Frequency=5MHz

V =1V

CNTL

V =0.7V

CNTL

V =0.4V

CNTL

-50

V (V)

CNTL

0.6 1.2

Crosstalk(dBc)

0.80.7 0.9 1.0 1.1

AdjacentChannels

PGA=20dB

1dBFS-

10MHz

5MHz

2MHz

-50

V (V)

CNTL

0.6 1.2

Crosstalk(dBc)

0.80.7 0.9 1.0 1.1

AdjacentChannels

PGA=25dB

1dBFS-

10MHz

5MHz

2MHz

-50

V (V)

CNTL

0.6 1.2

Crosstalk(dBc)

0.80.7 0.9 1.0 1.1

AdjacentChannels

PGA=27dB

1dBFS-

10MHz

5MHz

2MHz

-50

V (V)

CNTL

0.6 1.2

Crosstalk(dBc)

0.80.7 0.9 1.0 1.1

AdjacentChannels

PGA=30dB

1dBFS-

10MHz

5MHz

2MHz

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

2ND HARMONIC vs VCNTL vs OUTPUT LEVEL 3RD HARMONIC vs VCNTL vs OUTPUT LEVEL

Figure 23. Figure 24.

CROSSTALK vs VCNTL CROSSTALK vs VCNTL

Figure 25. Figure 26.

CROSSTALK vs VCNTL CROSSTALK vs VCNTL

Figure 27. Figure 28.

Product Folder Link(s): AFE5805

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

035

Magnitude(dB)

Frequency(MHz)

510 15 20 25 30

-2

-4

-6

-8

-10

-12

-14

-16

-18

-20

035

Magnitude(dB)

Frequency(MHz)

510 15 20 25 30

100

120

Frequency(MHz)

1.80 2.20

Magnitude(dBFS)

1.951.901.85 2.00

PGA=30dB

V =1.0V

IMD3=54.2dB

CNTL

2.05 2.10 2.15

-32

-6

-86.2

100

120

Frequency(MHz)

4.80 5.20

Magnitude(dBFS)

4.954.904.85 5.00

PGA=30dB

V =1.0V

IMD3=58.5dB

CNTL

5.05 5.10 5.15

-32

-6

-90.5

12k

10k

100M

Magnitude( )W

100

-100

Phase( )°

-80

-20

-40

-60

Frequency(Hz)

100k 1M 10M

Magnitude(Z )

IN Phase

1.0

0.5

1.0

SamplePoints

080

Output( Full-Scale)±

302010 40

V =1V (+12dBFS)

PGA=20dB

V =0.54V

IN PP

CNTL

50 60 70 90 100 110 120

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

10MHz LOW-PASS FILTER RESPONSE 15MHz LOW-PASS FILTER RESPONSE

Figure 29. Figure 30.

INTERMODULATION DISTORTION INTERMODULATION DISTORTION

(1.99MHz and 2.01MHz) (4.99MHz and 5.01MHz)

Figure 31. Figure 32.

INPUT IMPEDANCE vs FREQUENCY LNA OVERLOAD

Figure 33. Figure 34.

Product Folder Link(s): AFE5805

1.0

0.5

1.0

SamplePoints

080

Output( Full-Scale)±

302010 40

V =0.5V (+6dBFS)

PGA=30dB

V =1.0V

IN PP

CNTL

50 60 70 90 100 110 120

1.0

0.5

1.0

Time( s)m

015

Output( Full-Scale)±

5 10

PGA=30dB

V =1.0V

V =250mV ,0.25mV

CNTL

IN PP PP

1.0

0.5

1.0

Time( s)m

010

Output( Full-Scale)±

PGA=30dB

V =0Vto1.2V

CNTL

VCNTL

1.0

0.5

1.0

Time( s)m

020

Output( Full-Scale)±

PGA=30dB

V =0.4V

CNTL

305 15 25

170

150

130

110

ClockFrequency(MSPS)

555352515 45

ILVDD

IAVDD1

ZeroInputonAllChannels

I ,I (mA)

AVDD1 LVDD

995

990

985

980

975

970

965

960

955

950

945

Temperature( C)°

-40 85

TotalPower(mW)

0 25

TGCMode

50 70

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

TYPICAL CHARACTERISTICS (continued)

AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,

VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,

ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA= +25°C, unless otherwise noted.

FULL CHANNEL OVERLOAD OVERLOAD RECOVERY

Figure 35. Figure 36.

VCNTL RESPONSE TIME POWER-UP/POWER-DOWN RESPONSE TIME

Figure 37. Figure 38.

AVDD1 AND LVDD POWER-SUPPLY CURRENTS

vs CLOCK FREQUENCY POWER DISSIPATION vs TEMPERATURE

Figure 39. Figure 40.

Product Folder Link(s): AFE5805

(connectexternally)

VCA_CS RST

[H4]

[H9]

VCA_SCLK

VCA_SDATA

ADS_CS

ADS_SCLK

ADS_SDATA

ADS_RESET

[H8]SDATA

[H7]CS

[H6]SCLK

[L9]

EN_SM

Tieto:

+3.3V(AVDD1)

[H5]

AFE5805

SPIInterfaceandRegister

AFE5805

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SERIAL INTERFACE

The AFE5805 has a set of internal registers that can be accessed through the serial interface formed by pins CS

(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the

following actions occur:

• Serial shift of bits into the device is enabled

• SDATA (serial data) is latched at every rising edge of SCLK

• SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds

(a few hertz) and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be

done in one of two ways:

1. Through a hardware reset, by applying a low-going pulse on the ADS_RESET pin; or

2. Through a software reset; using the serial interface, set the S_RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the bit low. In this case, the

ADS_RESET pin stays high (inactive).

It is recommended to program the following registers after the initialization stage. The power-supply ripple and

clock jitter effects can be minimized.

ADDRESS DATA

01 0010

D1 0140

DA 0001

E1 0020

02 0080

01 0000

Serial Port Interface (SPI) Information

Figure 41. Typical Connection Diagram for the SPI Control Lines

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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

SCLK

SDATA

DatalatchedonrisingedgeofSCLK

StartSequence EndSequence

D0 D39

VCA_SDATA

VCA_SCLK

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SERIAL INTERFACE TIMING

AFE5805

PARAMETER DESCRIPTION MIN TYP MAX UNIT

t1SCLK period 50 ns

t2SCLK high time 20 ns

t3SCLK low time 20 ns

t4Data setup time 5 ns

t5Data hold time 5 ns

t6CS fall to SCLK rise 8 ns

t7Time between last SCLK rising edge to CS rising edge 8 ns

Internally-Generated VCA Control Signals

VCA_SCLK and VCA_SDATA signals are generated if:

• Registers with address 16, 17, or 18 (Hex) are written into, and

• EN_SM pin is HIGH

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SERIAL REGISTER MAP

Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4)

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT

00 X S_RST Self-clearing software RESET. Inactive

RES_

03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VCA

VCA_SDATA D5 = 1

16 X X X X X X X X X X X X X X 1 1 See Table 4 information

<0:15> (TGC mode)

VCA_SDATA

17 X X X X X X X X X X X X X X X X See Table 4 information

<16:31>

VCA_DATA

18 X X X X X X X X See Table 4 information

<32:39>

Channel-specific ADC

X X X X PDN_CH<1:4> Inactive

power-down mode.

Channel-specific ADC

xX X X X PDN_CH<8:5> Inactive

power-down mode.

Partial power-down mode (fast

0F X PDN_PARTIAL Inactive

recovery from power-down).

0 X PDN_COMPLETE Inactive

power-down (slower recovery).

Configures the PD pin for Complete

X 0 PDN_PIN_CFG partial power-down mode. power-down

LVDS current drive

X X X ILVDS_LCLK<2:0> programmability for LCLKM 3.5mA drive

and LCLKP pins.

LVDS current drive

ILVDS_FRAME

11 X X X programmability for FCLKM 3.5mA drive

<2:0> and FCLKP pins.

LVDS current drive

X X X ILVDS_DAT<2:0> programmability for OUTM and 3.5mA drive

OUTP pins.

Enables internal termination Termination

X EN_LVDS_TERM for LVDS buffers. disabled

Programmable termination for Termination

1 X X X TERM_LCLK<2:0> LCLKM and LCLKP buffers. disabled

12 TERM_FRAME Programmable termination for Termination

1 X X X <2:0> FCLKM and FCLKP buffers. disabled

Programmable termination for Termination

1 X X X TERM_DAT<2:0> OUTM and OUTP buffers. disabled

Channel-specific,

X X X X LFNS_CH<1:4> low-frequency noise Inactive

suppression mode enable.

14 Channel-specific,

xX X X X LFNS_CH<8:5> low-frequency noise Inactive

suppression mode enable.

Enables a repeating full-scale

X 0 0 EN_RAMP Inactive

ramp pattern on the outputs.

Enables the mode wherein the

DUALCUSTOM_

0 X 0 output toggles between two Inactive

PAT defined codes.

Enables the mode wherein the

SINGLE_CUSTOM

0 0 X output is a constant specified Inactive

25 _PAT code.

2MSBs for a single custom

BITS_CUSTOM1 pattern (and for the first code

X X Inactive

<11:10> of the dual custom pattern).

<11> is the MSB.

BITS_CUSTOM2 2MSBs for the second code of

X X Inactive

<11:10> the dual custom pattern.

10 lower bits for the single

BITS_CUSTOM1 custom pattern (and for the

26 X X X X X X X X X X Inactive

<9:0> first code of the dual custom

pattern). <0> is the LSB.

10 lower bits for the second

BITS_CUSTOM2

27 X X X X X X X X X X code of the dual custom Inactive

<9:0> pattern.

(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2) X = Register bit referenced by the corresponding name and description (default setting is listed above).

(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4) Multiple functions in a register should be programmed in a single write operation.

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Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) (3) (4) (continued)

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT

X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain

X X X X GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain

2A X X X X GAIN_CH2<3:0> Programmable gain channel 2. 0dB gain

X X X X GAIN_CH1<3:0> Programmable gain channel 1. 0dB gain

X X X X GAIN_CH5<3:0> Programmable gain channel 5. 0dB gain

X X X X GAIN_CH6<3:0> Programmable gain channel 6. 0dB gain

2B X X X X GAIN_CH7<3:0> Programmable gain channel 7. 0dB gain

X X X X GAIN_CH8<3:0> Programmable gain channel 8. 0dB gain

Single-

1 1 X DIFF_CLK Differential clock mode. ended clock

Enables the duty-cycle

1 1 X EN_DCC Disabled

correction circuit.

External

42 Drives the external reference reference

1 1 X EXT_REF_VCM mode through the VCM pin. drives REFT

and REFB

Controls the phase of LCLK

1 1 X X PHASE_DDR<1:0> 90 degrees

output relative to data.

0 X PAT_DESKEW Enables deskew pattern mode. Inactive

45 X 0 PAT_SYNC Enables sync pattern mode. Inactive

Binary two's complement Straight

1 1 X BTC_MODE format for ADC output. offset binary

Serialized ADC output comes LSB-first

1 1 X MSB_FIRST out MSB-first. output

Enables SDR output mode DDR output

1 1 X EN_SDR (LCLK becomes a 12x input

46 mode

clock).

Controls whether the LCLK Rising edge

rising or falling edge comes in of LCLK in

1 1 1 1 FALL_SDR the middle of the data window middle of

when operating in SDR output data window

mode.

SUMMARY OF FEATURES

POWER IMPACT (Relative to Default)

FEATURES DEFAULT SELECTION AT fS= 50MSPS

ANALOG FEATURES

Internal or external reference N/A Pin Internal reference mode takes approximately 20mW more power on AVDD1

(driven on the REFT and REFB pins)

External reference driven on the CM pin Off Register 42 Approximately 8mW less power on AVDD1

Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD1

With zero input to the ADC, low-frequency noise suppression causes digital switching

Low-frequency noise suppression Off Register 14 at fS/2, thereby increasing LVDD power by approximately 5.5mW/channel

Single-ended or differential clock Single-ended Register 42 Differential clock mode takes approximately 7mW more power on AVDD1

Power-down mode Off Pin and register 0F Refer to the Power-Down Modes section in the Electrical Characteristics table

DIGITAL FEATURES

Programmable digital gain (0dB to 12dB) 0dB Registers 2A and 2B No difference

Straight offset or BTC output Straight offset Register 46 No difference

LVDS OUTPUT PHYSICAL LAYER

LVDS internal termination Off Register 12 Approximately 7mW more power on AVDD1

LVDS current programmability 3.5mA Register 11 As per LVDS clock and data buffer current setting

LVDS OUTPUT TIMING

LSB- or MSB-first output LSB-first Register 46 No difference

DDR or SDR output DDR Register 46 SDR mode takes approximately 2mW more power on LVDD (at fS= 30MSPS)

LCLK phase relative to data output Refer to Figure 43 Register 42 No difference

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DESCRIPTION OF SERIAL REGISTERS

SOFTWARE RESET

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

00 X S_RST

Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears

to '0'.

Table 3. VCA Register Information

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

RES_V

03 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA 1(1) 1(1)

16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA

17 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16

VCA VCA VCA VCA VCA VCA VCA VCA

18 D39 D38 D37 D36 D35 D34 D33 D32

(1) Bits D0 and D1 of register 16 are forced to '1'.

space

• VCA_SCLK and VCA_SDATA become active only when one of the registers 16, 17, or 18 of the AFE5805

are written into.

• The contents of all three registers (total 40 bits) are written on VCA_SDATA even if only one of the above

registers is written into. This condition is only valid if the content of the register has changed because of the

most recent write. Writing contents that are the same as existing contents does not trigger activity on

VCA_SDATA.

• For example, if register 17 is written into after a RESET is applied, then the contents of register 17 as well as

the default values of the bits in registers 16 and 18 are written into VCA_SDATA.

• If register 16 is then written to, then the new contents of register 16, the previously written contents of register

17, and the default contents of register 18 are written into VCA_SDATA. Note that regardless of what is

written into D0 and D1 of register 16, the respective outputs on VCA_SDATA are always ‘1’.

• Alternatively, all three registers (16, 17 and 18) can also be written within one write cycle of the serial

interface. In that case, there would be 48 consecutive SCLK edges within the same CS active window.

• VCA_SCLK is generated using an oscillator (running at approximately 6MHz) inside the AFE5805, but the

oscillator is gated so that it is active only during the write operation of the 40 VCA bits.

• To ensure the SDATA transfer reliability, a ≥1ms gap is recommended between programming two VCA

registers consecutively.

VCA Reset

• VCA_CS should be permanently connected to the RST-input.

• When VCA_CS goes high (either because of an active low pulse on ADS_RESET for more than 10ns or as a

result or setting bit RES_VCA), the following functions are performed inside the AFE5805:

– Bits D0 and D1 of register 16 are forced to ‘1’

– All other bits in registers 16, 17 and 18 are RESET to the respective default values (‘0’ for all bits except

D5 of register 16 which is set to a default of ‘1’).

– No activity on signals VCA_SCLK and VCA_SDATA.

• If bit RES_VCA has been set to ‘1’, then the state machine is in the RESET state until RES_VCA is set to ‘0’.

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INPUT REGISTER BIT MAPS

Table 4. VCA Register Map

BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5

D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39

Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8

Table 5. Byte 1—Control Byte Register Map

BIT NUMBER BIT NAME DESCRIPTION

D0 (LSB) 1 Start bit; this bit is permanently set high = 1

D1 WR Write bit; this bit is permanently set high = 1

D2 PWR 1= Power-down mode enabled.

D3 BW Low-pass filter bandwidth setting (see Table 10)

D4 CL Clamp level setting (see Table 10)

D5 Mode 1 = TGC mode (default) , 0 = CW Doppler mode

D6 PG0 LSB of PGA gain control (see Table 11)

D7 (MSB) PG1 MSB of PGA gain control

Table 6. Byte 2—First Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D8 (LSB) DB1:1 Channel 1, LSB of matrix control

D9 DB1:2 Channel 1, matrix control

D10 DB1:3 Channel 1, matrix control

D11 DB1:4 Channel 1, MSB of matrix control

D12 DB2:1 Channel 2, LSB of matrix control

D13 DB2:2 Channel 2, matrix control

D14 DB2:3 Channel 2, matrix control

D15 (MSB) DB2:4 Channel 2, MSB of matrix control

Table 7. Byte 3—Second Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D16 (LSB) DB3:1 Channel 3, LSB of matrix control

D17 DB3:2 Channel 3, matrix control

D18 DB3:3 Channel 3, matrix control

D19 DB3:4 Channel 3, MSB of matrix control

D20 DB4:1 Channel 4, LSB of matrix control

D21 DB4:2 Channel 4, matrix control

D22 DB4:3 Channel 4, matrix control

D23 (MSB) DB4:4 Channel 4, MSB of matrix control

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Table 8. Byte 4—Third Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D24 (LSB) DB5:1 Channel 5, LSB of matrix control

D25 DB5:2 Channel 5, matrix control

D26 DB5:3 Channel 5, matrix control

D27 DB5:4 Channel 5, MSB of matrix control

D28 DB6:1 Channel 6, LSB of matrix control

D29 DB6:2 Channel 6, matrix control

D30 DB6:3 Channel 6, matrix control

D31 (MSB) DB6:4 Channel 6, MSB of matrix control

Table 9. Byte 5—Fourth Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D32 (LSB) DB7:1 Channel 7, LSB of matrix control

D33 DB7:2 Channel 7, matrix control

D34 DB7:3 Channel 7, matrix control

D35 DB7:4 Channel 7, MSB of matrix control

D36 DB8:1 Channel 8, LSB of matrix control

D37 DB8:2 Channel 8, matrix control

D38 DB8:3 Channel 8, matrix control

D39 (MSB) DB8:4 Channel 8, MSB of matrix control

Table 10. Clamp Level and LPF Bandwidth Setting

FUNCTION

BW D3 = 0 Bandwidth set to 15MHz (default)

BW D3 = 1 Bandwidth set to 10MHz

CL D4 = 0 Clamps the output signal at approximately –1.4dB below the full-scale of 2VPP.

CL D4 = 1 Clamp transparent (disabled)

Table 11. PGA Gain Setting

PG1 (D7) PG0 (D6) FUNCTION

0 0 Sets PGA gain to 20dB (default)

0 1 Sets PGA gain to 25dB

1 0 Sets PGA gain to 27dB

1 1 Sets PGA gain to 30dB

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Channel1

Input

V/I

Converter

VCA_SDATA

CW0

CW1

CW2

CW3

CW4

CW5

CW6

CW7

CW8

CW9

AVDD_5V

VCA_SCLK

Decode

Logic

(ToOtherChannels)

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Table 12. CW Switch Matrix Control for Each Channel

DBn:4 (MSB) DBn:3 DBn:2 DBn:1 (LSB) LNA INPUT CHANNEL n DIRECTED TO

0 0 0 0 Output CW0

0 0 0 1 Output CW1

0 0 1 0 Output CW2

0 0 1 1 Output CW3

0 1 0 0 Output CW4

0 1 0 1 Output CW5

0 1 1 0 Output CW6

0 1 1 1 Output CW7

1 0 0 0 Output CW8

1 0 0 1 Output CW9

1 0 1 0 Connected to AVDD_5V

1 0 1 1 Connected to AVDD_5V

1 1 0 0 Connected to AVDD_5V

1 1 0 1 Connected to AVDD_5V

1 1 1 0 Connected to AVDD_5V

1 1 1 1 Connected to AVDD_5V

Figure 42. Basic CW Cross-Point Switch Matrix Configuration

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POWER-DOWN MODES

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X X PDN_CH<1:4>

X X X X PDN_CH<8:5>

0F X PDN_PARTIAL

0 X PDN_COMPLETE

X 0 PDN_PIN_CFG

Each of the eight ADC channels within the AFE5805 can be individually powered down. PDN_CH<N> controls

the power-down mode for the ADC channel <N>.

In addition to channel-specific power-down, the AFE5805 also has two global power-down modes: partial

power-down mode and complete power-down mode.

In addition to programming the device for either of these two power-down modes (through either the

PDN_PARTIAL or PDN_COMPLETE bits, respectively), the ADS_PD pin itself can be configured as either a

partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when

the ADS_PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when

the ADS_PD pin is high, the device enters partial power-down mode.

The partial power-down mode function allows the AFE5805 to be rapidly placed in a low-power state. In this

mode, most amplifiers in the signal path are powered down, while the internal references remain active. This

configuration ensures that the external bypass capacitors retain the respective charges, minimizing the wake-up

response time. The wake-up response is typically less than 50ms, provided that the clock has been running for at

least 50ms before normal operating mode resumes. The power-down time is instantaneous (less than 1.0ms).

In partial power-down mode, the part typically dissipates only 233mW, representing a 76% power reduction

compared to the normal operating mode. This function is controlled through the ADS_PD and VCA_PD pins,

which are designed to interface with 3.3V low-voltage logic. If separate control of the two PD pins is not desired,

then both can be tied together. In this case, the ADS_PD pin should be configured to operate as a partial

power-down mode pin [see further information (PDN_PIN_CFG) above].

For normal operation the PD pins should be tied to a logic low (0); a high (1) places the AFE5805 into partial

power-down mode.

To achieve the lowest power dissipation of only 64mW, the AFE5805 can be placed in complete power-down

mode. This mode is controlled through the serial interface by setting Register 16 (bit D2) and Register 0F (bit

D9:D10). In complete power-down mode, all circuits (including references) within the AFE5805 are

powered-down, and the bypass capacitors then discharge. Consequently, the wake-up time from complete

power-down mode depends largely on the time needed to recharge the bypass capacitors. Another factor that

affects the wake-up time is the elapsed time that the AFE5805 spends in shutdown mode.

LVDS DRIVE PROGRAMMABILITY

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X ILVDS_LCLK<2:0>

11 X X X ILVDS_FRAME<2:0>

X X X ILVDS_DAT<2:0>

The LVDS drive strength of the bit clock (LCLKP or LCLKM) and the frame clock (FCLKP or FCLKM) can be

individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTM can also be

programmed to the same value.

All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 13

details an example of how the drive strength of the bit clock is programmed (the method is similar for the frame

clock and data drive strengths).

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Table 13. Bit Clock Drive Strength(1)

ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM

0 0 0 3.5mA (default)

0 0 1 2.5mA

0 1 0 1.5mA

0 1 1 0.5mA

1 0 0 7.5mA

1 0 1 6.5mA

1 1 0 5.5mA

1 1 1 4.5mA

(1) Current settings lower than 1.5mA are not recommended.

LVDS INTERNAL TERMINATION PROGRAMMING

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X EN_LVDS_TERM

1 X X X TERM_LCLK<2:0>

12 1 X X X TERM_FRAME<2:0>

1 X X X TERM_DAT<2:0>

The LVDS buffers have high-impedance current sources that drive the outputs. When driving traces with

characteristic impedances that are not perfectly matched with the termination impedance on the receiver side,

there may be reflections back to the LVDS output pins of the AFE5805 that cause degraded signal integrity. By

enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal

integrity can be significantly improved in such scenarios. To set the internal termination mode, the

EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock,

frame clock, and data buffers can be independently programmed using sets of three bits. Table 14 shows an

example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is

similar for the frame clock and data drive strengths). These termination values are only typical values and can

vary by several percent across temperature and from device to device.

Table 14. Bit Clock Internal Termination

INTERNAL TERMINATION BETWEEN

TERM_LCLK<2> TERM_LCLK<1> TERM_LCLK<0> LCLKP AND LCLKM IN Ω

0 0 0 None

0 0 1 260

0 1 0 150

0 1 1 94

1 0 0 125

1 0 1 80

1 1 0 66

1 1 1 55

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LOW-FREQUENCY NOISE SUPPRESSION MODE

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X X LFNS_CH<1:4>

14 X X X X LFNS_CH<8:5>

The low-frequency noise suppression mode is especially useful in applications where good noise performance is

desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of

the AFE5805 to approximately fS/2, thereby moving the noise floor around dc to a much lower value.

LFNS_CH<8:1> enables this mode individually for each channel.

LVDS TEST PATTERNS

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X 0 0 EN_RAMP

0 X 0 DUALCUSTOM_PAT

25 0 0 X SINGLE_CUSTOM_PAT

X X BITS_CUSTOM1<11:10>

X X BITS_CUSTOM2<11:10>

26 X X X X X X X X X X BITS_CUSTOM1<9:0>

27 X X X X X X X X X X BITS_CUSTOM2<9:0>

0 X PAT_DESKEW

45 X 0 PAT_SYNC

The AFE5805 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal

ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.

The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the

full-scale code, it returns back to zero code and ramps again.

The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and

programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM<11:0> take the place of

the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as

normal ADC data are.

The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT

to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>.

In addition to custom patterns, the device may also be made to output two preset patterns:

1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the

010101010101 word.

2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word.

Note that only one of the above patterns can be active at any given instant.

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PROGRAMMABLE GAIN

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X X GAIN_CH4<3:0>

X X X X GAIN_CH3<3:0>

2A X X X X GAIN_CH2<3:0>

X X X X GAIN_CH1<3:0>

X X X X GAIN_CH5<3:0>

X X X X GAIN_CH6<3:0>

2B X X X X GAIN_CH7<3:0>

X X X X GAIN_CH8<3:0>

The AFE5805, through its registers, allows for a digital gain to be programmed for each channel. This

programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The

programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by

using quantization information from some extra internal bits. The programmable gain for each channel can be

individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in

binary from 0dB to 12dB, as shown in Table 15.

Table 15. Gain Setting for Channel 1

GAIN_CH1<3> GAIN_CH1<2> GAIN_CH1<1> GAIN_CH1<0> CHANNEL 1 GAIN SETTING

0 0 0 0 0dB

0 0 0 1 1dB

0 0 1 0 2dB

0 0 1 1 3dB

0 1 0 0 4dB

0 1 0 1 5dB

0 1 1 0 6dB

0 1 1 1 7dB

1 0 0 0 8dB

1 0 0 1 9dB

1 0 1 0 10dB

1 0 1 1 11dB

1 1 0 0 12dB

1 1 0 1 Do not use

1 1 1 0 Do not use

1 1 1 1 Do not use

Product Folder Link(s): AFE5805

VREFT=1.5V+ VCM

1.5V

VREFB=1.5V -

VCM

1.5V

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

CLOCK, REFERENCE, AND DATA OUTPUT MODES

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

1 1 X DIFF_CLK

1 1 X EN_DCC

42 1 1 X EXT_REF_VCM

1 1 X X PHASE_DDR<1:0>

1 1 X BTC_MODE

1 1 X MSB_FIRST

46 1 1 X EN_SDR

1 1 1 1 FALL_SDR

INPUT CLOCK

The AFE5805 is configured by default to operate with a single-ended input clock; CLKP is driven by a CMOS

clock and CLKM is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a

differential input clock on CLKP and CLKM. Operating with a low-jitter differential clock generally leads to

improved SNR performance.

In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable

an internal duty cycle correction circuit. Enable this circuit by setting the EN_DCC bit to '1'.

EXTERNAL REFERENCE

The AFE5805 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,

the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have

enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The

advantage of using the external reference mode is that multiple AFE5805 units can be made to operate with the

same external reference, thereby improving parameters such as gain matching across devices. However, in

applications that do not have an available high drive, differential external reference, the AFE5805 can still be

driven with a single external reference voltage on the CM pin. When EXT_REF_VCM is set as '1' (and the

INT/EXT pin is set to '0'), the CM pin is configured as an input pin, and the voltages on REFT and REFB are

generated as shown in Equation 1 and Equation 2.

(1)

(2)

Product Folder Link(s): AFE5805

FCLKP

LCLKP

OUTP

PHASE_DDR<1:0>='00'

PHASE_DDR<1:0>='01'

PHASE_DDR<1:0>='10'

PHASE_DDR<1:0>='11'

FCLKP

LCLKP

OUTP

FCLKP

LCLKP

OUTP

FCLKP

LCLKP

OUTP

FCLKP

LCLKP

OUTP

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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BIT CLOCK PROGRAMMABILITY

The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge

transitions in the middle of alternate data windows. Figure 43 shows this default phase.

Figure 43. LCLK Default Phase

The phase of LCLK can be programmed relative to the output frame clock and data using bits

PHASE_DDR<1:0>. Figure 44 shows the LCLK phase modes.

Figure 44. LCLK Phase Programmability Modes

Product Folder Link(s): AFE5805

EN_SDR='1',FALL_SDR='0'

FCLKP

LCLKP

OUTP

EN_SDR='1',FALL_SDR='1'

FCLKP

LCLKP

OUTP

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR

mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12 times the input clock, or

twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two

manners shown in Figure 45.AsFigure 45 illustrates, only the LCLK rising (or falling) edge is used to capture the

output data in SDR mode.

Figure 45. SDR Interface Modes

The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.

DATA OUTPUT FORMAT MODES

The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the

MSB, and the output becomes binary two's complement mode.

Also by default, the first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output.

Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit

following the FCLKP rising edge.

Product Folder Link(s): AFE5805

High-Level RESET

(1.4Vto3.6V)

High-Level CS

(1.4Vto3.6V)

DeviceReadyfor

SerialRegisterWrite

DeviceReadyfor

DataConversion

StartofClock

AVDD1

AVDD2

DVDD

AVDD 5V-

LVDD

ADS_RESET

FCLK

t4t7

(3.3V,5.0V)

(1.8V)

VCA_PD,ADC_PD(2)

DeviceFully

PowersDown

DeviceFully

PowersUp

1 smt(1)

WAKE

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING

10ms < t1< 50ms, 10ms < t2< 50ms, –10ms < t3< 10ms, t4> 10ms, t5> 100ns, t6> 100ns, t7> 10ms, and t8> 100ms.

The AVDDx and LVDD power-on sequence does not matter as long as –10ms < t3< 10ms. Similar considerations apply while shutting down

the device.

POWER-DOWN TIMING

Power-up time shown is based on 1mF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up

completely from power-down mode. The AFE5805 has two power-down modes: complete power-down mode and partial power-down mode.

(1) tWAKE ≤50ms for complete power-down mode. tWAKE ≤2ms for partial power-down mode (provided the clock is not shut off during

power-down).

(2) The ADS_PD pins can be configured for partial power-down mode through a register setting.

Product Folder Link(s): AFE5805

CIN

LNA

V/I CWSwitchMatrix

Attenuator

(VCA) PGA Clamp

LPF

CW/IOUT

OUT

T/R

Switch

VCNTL

AFE5805

LVDS

Serializer

12-Bit

ADC

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

THEORY OF OPERATION

of 0V to 1.2V. While the LNA is designed to be driven

The AFE5805 is an 8-channel, fully integrated analog from a single-ended source, the internal TGC signal

front-end device controlling the LNA, attenuator, path is designed to be fully differential to maximize

PGA, LPF, and ADC, that implements a number of dynamic range while also optimizing for low,

proprietary circuit design techniques to specifically even-order harmonic distortion.

address the performance demands of medical

ultrasound systems. It offers unparalleled low-noise CW doppler signal processing is facilitated by routing

and low-power performance at a high level of the differential LNA outputs to V/I amplifier stages.

integration. For the TGC signal path, each channel The resulting signal currents of each channel then

consists of a 20dB fixed-gain low-noise amplifier connect to an 8×10 switch matrix that is controlled

(LNA), a linear-in-dB voltage-controlled attenuator through the serial interface and a corresponding

(VCA), and a programmable gain amplifier (PGA), as register. The CW outputs are typically routed to a

well as a clamping and low-pass filter stage. Digitally passive delay line that allows coherent summing

controlled through the logic interface, the PGA gain (beam forming) of the active channels and additional

can be set to four different settings: 20dB, 25dB, off-chip signal processing, as shown in Figure 46.

27dB, and 30dB. At its highest setting, the total Applications that do not utilize the CW path can

available gain of the AFE5805 is therefore 50dB. To simply operate the AFE5805 in TGC mode. In this

facilitate the logarithmic time-gain compensation mode, the CW blocks (V/I amplifiers and switch

required for ultrasound systems, the VCA is designed matrix) remain powered down, and the CW outputs

to provide a 46dB attenuation range. Here, all can be left unconnected.

channels are simultaneously controlled by an

externally-applied control voltage (VCNTL) in the range

Figure 46. Functional Block Diagram

Product Folder Link(s): AFE5805

Attenuator

Input

Attenuator

Output

A1-A8AttenuatorStages

Control

Input

Q2Q3

C -C ClippingAmplifiers

1 8

Q5Q6Q7Q8

A1 A2 A3 A4 A5 A6 A7 A8

VCNTL

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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LOW-NOISE AMPLIFIER (LNA) The attenuator is essentially a variable voltage divider

that consists of the series input resistor (RS) and

As with many high-gain systems, the front-end eight identical shunt FETs placed in parallel and

amplifier is critical to achieve a certain overall controlled by sequentially activated clipping amplifiers

performance level. Using a new proprietary (A1 through A8). Each clipping amplifier can be

architecture, the LNA of the AFE5805 delivers understood as a specialized voltage comparator with

exceptional low-noise performance, while operating a soft transfer characteristic and well-controlled

on a very low quiescent current compared to output limit voltage. Reference voltages V1 through

CMOS-based architectures with similar noise V8 are equally spaced over the 0V to 1.2V control

performances. voltage range. As the control voltage rises through

the input range of each clipping amplifier, the

The LNA performs a single-ended input to differential amplifier output rises from 0V (FET completely ON) to

output voltage conversion and is configured for a VCM – VT(FET nearly OFF), where VCM is the

fixed gain of 20dB (10V/V). The ultralow common source voltage and VTis the threshold

input-referred noise of only 0.7nV/√Hz, along with the voltage of the FET. As each FET approaches its off

linear input range of 250mVPP, results in a wide state and the control voltage continues to rise, the

dynamic range that supports the high demands of next clipping amplifier/FET combination takes over for

PW and CW ultrasound imaging modes. Larger input the next portion of the piecewise-linear attenuation

signals can be accepted by the LNA, but distortion characteristic.

performance degrades as input signal levels

increase. The LNA input is internally biased to Thus, low control voltages have most of the FETs

approximately +2.4V; the signal source should be turned on, producing maximum signal attenuation.

ac-coupled to the LNA input by an adequately-sized Similarly, high control voltages turn the FETs off,

capacitor. Internally, the LNA directly drives the VCA, leading to minimal signal attenuation. Therefore, each

avoiding the typical drawbacks of ac-coupled FET acts to decrease the shunt resistance of the

architectures, such as slow overload recovery. voltage divider formed by RSand the parallel FET

network.

VOLTAGE-CONTROLLED ATTENUATOR

(VCA)

The VCA is designed to have a linear-in-dB

attenuation characteristic; that is, the average gain

loss in dB is constant for each equal increment of the

control voltage (VCNTL). Figure 47 shows the

simplified schematic of this VCA stage.

Figure 47. Voltage-Controlled Attenuator Simplified Schematic

Product Folder Link(s): AFE5805

Clamp

Gain

Control

Bits

From

Attenuator

Clamp

Control

Bit

Low-Pass

Filter

PGA

VCM

(+1.65V)

ToADC

Inputs

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

PROGRAMMABLE POST-GAIN AMPLIFIER

(PGA) PROGRAMMABLE CLAMPING

Following the VCA is a programmable post-gain

amplifier (PGA). Figure 48 shows a simplified To further optimize the overload recovery behavior of

schematic of the PGA, including the clamping stage. a complete TGC channel, the AFE5805 integrates a

The gain of this PGA can be configured to four programmable clamping stage, as shown in

different gain settings: 20dB, 25dB, 27dB, and 30dB, Figure 49. This clamping stage precedes the

programmable through the serial port; see Table 10.low-pass filter in order to prevent the filter circuit from

being driven into overload, the result of which would

The PGA structure consists of a differential, be an extended recovery time. Programmable

programmable-gain voltage-to-current converter through the serial interface, the clamping level can be

stage followed by transimpedance amplifiers to buffer either set to clamp the signal level to approximately

each side of the differential output. Low input noise is 1.7VPP differential, or be disabled. Disabling the

also a requirement for the PGA design as a result of clamp function increases the current consumption on

the large amount of signal attenuation that can be the 3.3V analog supply (AVDD2) by about 3mA for

applied in the preceding VCA stage. At minimum the full device. Note that with the clamp function

VCA attenuation (used for small input signals), the enabled, the third-harmonic distortion increases.

LNA noise dominates; at maximum VCA attenuation

(large input signals), the attenuator and PGA noise LOW-PASS FILTER

dominate. The AFE5805 integrates an anti-aliasing filter in the

form of a programmable low-pass filter (LPF) for each

channel. The LPF is designed as a differential, active,

second-order filter that approximates a Bessel

characteristic, with typically 12dB per octave roll-off.

Figure 49 shows the simplified schematic of half the

differential active low-pass filter. Programmable

through the serial interface, the –3dB frequency

corner can be set to either 10MHz or 15MHz. The

filter bandwidth is set for all channels simultaneously.

Figure 48. Post-Gain Amplifier

(Simplified Schematic)

Figure 49. Clamping Stage and Low-Pass Filter (Simplified Schematic)

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AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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ANALOG-TO-DIGITAL CONVERSION devices without having to externally drive and route

reference lines. The nominal values of REFT and

The analog-to-digital converter (ADC) of the AFE5805 REFB are 2.5V and 0.5V, respectively. The

employs a pipelined converter architecture that references are internally scaled down differentially by

consists of a combination of multi-bit and single-bit a factor of 2. VCM (the common-mode voltage of

internal stages. Each stage feeds its data into the REFT and REFB) is also made available externally

digital error correction logic, ensuring excellent through a pin, and is nominally 1.5V.

differential linearity and no missing codes at the

12-bit level. The ADC output goes to a serializer that operates

from a 12x clock generated by the PLL. The 12 data

The 12 bits given out by each channel are serialized bits from each channel are serialized and sent LSB

and sent out on a single pair of pins in LVDS format. first. In addition to serializing the data, the serializer

All eight channels of the AFE5805 operate from a also generates a 1x clock and a 6x clock. These

common input clock (CLKP/M). The sampling clocks clocks are generated in the same way the serialized

for each of the eight channels are generated from the data are generated, so these clocks maintain perfect

input clock using a carefully matched clock buffer synchronization with the data. The data and clock

tree. The 12x clock required for the serializer is outputs of the serializer are buffered externally using

generated internally from CLKP/M using a LVDS buffers. Using LVDS buffers to transmit data

phase-locked loop (PLL). A 6x and a 1x clock are externally has multiple advantages, such as a

also output in LVDS format, along with the data, to reduced number of output pins (saving routing space

enable easy data capture. The AFE5805 operates on the board), reduced power consumption, and

from internally-generated reference voltages that are reduced effects of digital noise coupling to the analog

trimmed to improve the gain matching across circuit inside the AFE5805.

devices, and provide the option to operate the

Product Folder Link(s): AFE5805

Attenuator

8kW

7pF0.1mF

CIN

³ m0.1 F

(+2.4V)

VBL

T/R

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

APPLICATION INFORMATION

The LNA closed-loop architecture is internally

ANALOG INPUT AND LNA compensated for maximum stability without the need

of external compensation components (inductors or

While the LNA is designed as a fully differential capacitors). At the same time, the total input

amplifier, it is optimized to perform a single-ended capacitance is kept to a minimum with only 16pF.

input to differential output conversion. A simplified This architecture minimizes any loading of the signal

schematic of an LNA channel is shown in Figure 50.source that may otherwise lead to a

A bias voltage (VB) of +2.4V is internally applied to frequency-dependent voltage divider. Moreover, the

the LNA inputs through 8kΩresistors. In addition, the closed-loop design yields very low offsets and offset

dedicated signal input (IN pin) includes a pair of drift; this consideration is important because the LNA

back-to-back diodes that provide a coarse input directly drives the subsequent voltage-controlled

clamping function in case the input signal rises to attenuator.

very large levels, exceeding 0.7VPP. This

configuration prevents the LNA from being driven into The LNA of the AFE5805 uses the benefits of a

a severe overload state, which may otherwise cause bipolar process technology to achieve an

an extended overload recovery time. The integrated exceptionally low-noise voltage of 0.7nV/√Hz, and a

diodes are designed to handle a dc current of up to low current noise of only 3pA/√Hz. With these

approximately 5mA. Depending on the application input-referred noise specifications, the AFE5805

requirements, the system overload characteristics achieves very low noise figure numbers over a wide

may be improved by adding external Schottky diodes range of source resistances and frequencies (see

at the LNA input, as shown in Figure 50.Figure 16,Noise Figure vs Frequency vs RSin the

Typical Characteristics). The optimal noise power

As Figure 50 also shows, the complementary LNA matching is achieved for source impedances of

input (VBL pin) is internally decoupled by a small around 200Ω. Further details of the AFE5805 input

capacitor. Furthermore, for each input channel, a noise performance are shown in the Typical

separate VBL pin is brought out for external Characteristic graphs.

bypassing. This bypassing should be done with a

small, 0.1mF (typical) ceramic capacitor placed in Table 16. Noise Figure versus Source Resistance

close proximity to each VBL pin. Attention should be (RS) at 2MHz

given to provide a low-noise analog ground for this

bypass capacitor. A noisy ground potential may RS(Ω) NOISE FIGURE (dB)

cause noise to be picked up and injected into the 50 2.6

signal path, leading to higher noise levels. 200 1.0

400 1.1

1000 2.3

Figure 50. LNA Channel (Simplified Schematic)

Product Folder Link(s): AFE5805

LNA

Cable

Probe

Transducer

From

Pulser -5V

+5V

AFE5805

3kW

C2³ m0.1 F

3kW

BAS40

0.1 Fm

VBL

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

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OVERLOAD RECOVERY ±0.3V can significantly reduce the overall overload

recovery performance. The T/R switch characteristics

The AFE5805 is designed in particular for ultrasound are largely determined by the biasing current of the

applications where the front-end device is required to diodes, which can be set by adjusting the 3kΩ

recover very quickly from an overload condition. Such resistor values; for example, setting a higher current

an overload can either be the result of a transmit level may lead to an improved switching characteristic

pulse feed-through or a strong echo, which can cause and reduced noise contribution. A typical front-end

overload of the LNA, PGA, and ADC. As discussed protection circuitry may add in the order of 2nV/√Hz

earlier, the LNA inputs are internally protected by a of noise to the signal path. The increase in noise also

pair of back-to-back diodes to prevent severe depends on the value of the termination resistor (RT).

overload of the LNA. Figure 51 illustrates an

ultrasound receive channel front-end that includes As Figure 51 shows, the front-end circuitry should be

typical external overload protection elements. Here, capacitively coupled to the LNA signal input (IN). This

four high-voltage switching diodes are configured in a coupling ensures that the LNA input bias voltage of

bridge configuration and form the transmit/receive +2.4V is maintained and decoupled from any other

(T/R) switch. During the transmit period, high voltage biasing voltage before the LNA.

pulses from the pulser are applied to the transducer Within the AFE5805, overload can occur in either the

elements and the T/R switch isolates the sensitive LNA or the PGA. LNA overload can occur as the

LNA input from being damaged by the high voltage result of T/R switch feed-through; and the PGA can

signal. However, it is common that fast transients up be driven into an overload condition by a strong echo

to several volts leak through the T/R switch and in the near-field while the signal gain is high. In any

potentially overload the receiver. Therefore, an case, the AFE5805 is optimized for very short

additional pair of clamping diodes is placed between recovery times, as shown in Figure 51.

the T/R switch and the LNA input. In order to clamp

the over-voltage to small levels, Schottky diodes

(such as the BAS40 series by Infineon®) are

commonly used. For example, clamping to levels of

Figure 51. Typical Input Overload Protection Circuit of an Ultrasound System

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LNA

PGA

Attenuator

VCNTL

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

VCA—GAIN CONTROL When the AFE5805 operates in CW mode, the

attenuator stage remains connected to the LNA

The attenuator (VCA) for each of the eight channels outputs. Therefore, it is recommended to set the

of the AFE5805 is controlled by a single-ended VCNTL voltage to +1.2V in order to minimize the

control signal input, the VCNTL pin. The control voltage internal loading of the LNA outputs. Small

range spans from 0V to 1.2V, referenced to ground. improvements in reduced power dissipation and

This control voltage varies the attenuation of the VCA improved distortion performance may also be

based on its linear-in-dB characteristic with its realized.

maximum attenuation (minimum gain) at VCNTL = 0V,

and minimum attenuation (maximum gain) at VCNTL =

1.2V. Table 17 shows the nominal gains for each of

the four PGA gain settings. The total gain range is

typically 46dB and remains constant, independent of

the PGA selected; the Max Gain column reflects the

absolute gain of the full signal path comprised of the

fixed LNA gain of 20dB and the programmable PGA

gain.

Table 17. Nominal Gain Control Ranges for Each

of the Four PGA Gain Settings

MIN GAIN AT MAX GAIN AT

PGA GAIN VCNTL = 0V VCNTL = 1.2V

20dB –4.5dB 41.5dB

25dB –0.5dB 45.5dB

27dB 1.5dB 47.5dB

30dB 3.5dB 49.5dB

As previously discussed, the VCA architecture uses

eight attenuator segments that are equally spaced in Figure 52. External Filtering of the VCNTL Input

order to approximate the linear-in-dB gain-control

slope. This approximation results in a monotonic

slope; gain ripple is typically less than ±0.5dB. CW DOPPLER PROCESSING

The AFE5805 gain-control input has a –3dB The AFE5805 integrates many of the elements

bandwidth of approximately 1.5MHz. This wide necessary to allow for the implementation of a CW

bandwidth, although useful in many applications, can doppler processing circuit, such as a V/I converter for

allow high-frequency noise to modulate the gain each channel and a cross-point switch matrix with an

control input. In practice, this modulation can easily 8-input into 10-output (8×10) configuration.

be avoided by additional external filtering (RFand CF)

of the control input, as Figure 52 shows. Stepping the In order to switch the AFE5805 from the default TGC

control voltage from 0V to 1.2V, the gain control mode operation into CW mode, bit D5 of the VCA

response time is typically less than 500ns to settle control register must be updated to low ('0'); see

within 10% of the final signal level of 1VPP (–6dBFS) Table 5. This setting also enables access to all other

output. registers that determine the switch matrix

configuration (see the Input Register Bit Map tables).

The control voltage input (VCNTL pin) represents a In order to process CW signals, the LNA internally

high-impedance input. Multiple AFE5805 devices can feeds into a differential V/I amplifier stage. The

be connected in parallel with no significant loading transconductance of the V/I amplifier is typically

effects using the VCNTL pin of each device. Note that 15.6mA/V with a 100mVPP input signal. For proper

when the VCNTL pin is left unconnected, it floats up to operation, the CW outputs must be connected to an

a potential of about +3.7V. For any voltage level external bias voltage of +2.5V. Each CW output is

above 1.2V and up to 5.0V, the VCA continues to designed to sink a small dc current of 0.9mA, and

operate at its minimum attenuation level; however, it can deliver a signal current of up to 2.9mAPP.

is recommended to limit the voltage to approximately

1.5V or less.

Product Folder Link(s): AFE5805

ADC

VCM0

(+2.5V)

Amplifier

IandQ

Channel

ADC

AFE5805

CWOut

8InBy10Out

CW0

CW1

CW2

CW3

CW4

CW5

CW6

CW7

CW8

CW9

AFE5805

CWOut

8InBy10Out

CW0

CW1

CW2

CW3

CW4

CW5

CW6

CW7

CW8

CW9

Passive

Delay

Line

Clock

L=220 Hm

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

The resulting signal current then passes through the After summing, the CW signal path further consists of

8×10 switch matrix. Depending on the programmed a high dynamic range mixer for down-conversion to

configuration of the switch matrix, any V/I amplifier I/Q base-band signals. The I/Q signals are then

current output can be connected to any of 10 CW band-limited (that is, low-frequency contents are

outputs. This design is a simple current-summing removed) in a filter stage that precedes a pair of

circuit such that each CW output can represent the high-resolution, low sample rate ADCs.

sum of any or all of the channel currents. The CW

outputs are typically routed to a passive LC delay

line, allowing coherent summing of the signals.

Figure 53. Conceptual CW Doppler Signal Path Using Current Summing and a Passive Delay Line for

Beamforming

Product Folder Link(s): AFE5805

5kW5kW

CLKP

CLKM

VCM

CLKP

CLKM

DifferentialSine-Wave,

PECL,orLVDSClockInput

0.1 Fm

CLKP

CLKM

CMOSSingle-Ended

Clock

CLKP

CLKM

CMOSClockInput

0.1 Fm

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

CLOCK INPUT

The eight channels on the device operate from a

single clock input. To ensure that the aperture delay

and jitter are the same for all channels, the AFE5805

uses a clock tree network to generate individual

sampling clocks to each channel. The clock paths for

all the channels are matched from the source point to

the sampling circuit. This architecture ensures that

the performance and timing for all channels are

identical. The use of the clock tree for matching

introduces an aperture delay that is defined as the

delay between the rising edge of FCLK and the actual

instant of sampling. The aperture delays for all the

channels are matched to the best possible extent. A

mismatch of ±20ps (±3s) could exist between the

aperture instants of the eight ADCs within the same Figure 55. Internal Clock Buffer

chip. However, the aperture delays of ADCs across

two different chips can be several hundred

picoseconds apart.

The AFE5805 can operate either in CMOS

single-ended clock mode (default is DIFF_CLK = 0)

or differential clock mode (SINE, LVPECL, or LVDS).

In the single-ended clock mode, CLKM must be

forced to 0VDC, and the single-ended CMOS applied

on the CLKP pin. Figure 54 shows this operation.

Figure 56. Differential Clock Driving Circuit

(DIFF_CLK = 1)

Figure 54. Single-Ended Clock Driving Circuit

(DIFF_CLK = 0)

When configured for the differential clock mode

(register bit DIFF_CLK = 1) the AFE5805 clock inputs Figure 57. Single-Ended Clock Driving Circuit

can be driven differentially (SINE, LVPECL, or LVDS) When DIFF_CLK = 1

with little or no difference in performance between

them, or with a single-ended (LVCMOS). The For best performance, the clock inputs must be

common-mode voltage of the clock inputs is set to driven differentially, reducing susceptibility to

VCM using internal 5kΩresistors, as shown in common-mode noise. For high input frequency

Figure 55. This method allows using sampling, it is recommended to use a clock source

transformer-coupled drive circuits for a sine wave with very low jitter. Bandpass filtering of the clock

clock or ac-coupling for LVPECL and LVDS clock source can help reduce the effect of jitter. If the duty

sources, as shown in Figure 56 and Figure 57. When cycle deviates from 50% by more than 2% or 3%, it is

operating in the differential clock mode, the recommended to enable the DCC through register bit

single-ended CMOS clock can be ac-coupled to the EN_DCC.

CLKP input, with CLKM connected to ground with a

0.1mF capacitor, as Figure 57 shows.

Product Folder Link(s): AFE5805

VREFT=1.5V+ VCM

1.5V

VREFB=1.5V -

VCM

1.5V

REFT REFB

ISET

0.1 Fm2.2 Fm

56.2kW

2.2 Fm0.1 Fm

AFE5805

+ +

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

REFERENCE CIRCUIT The device also supports the use of external

reference voltages. There are two methods to force

The digital beam-forming algorithm in an ultrasound the references externally. The first method involves

system relies on gain matching across all receiver pulling INT/EXT low and forcing externally REFT and

channels. A typical system would have about 12 octal REFB to 2.5V and 0.5V nominally, respectively. In

AFEs on the board. In such a case, it is critical to this mode, the internal reference buffer goes to a

ensure that the gain is matched, essentially requiring 3-state output. The external reference driving circuit

the reference voltages seen by all the AFEs to be the should be designed to provide the required switching

same. Matching references within the eight channels current for the eight ADCs inside the AFE5805. It

of a chip is done by using a single internal reference should be noted that in this mode, CM and ISET

voltage buffer. Trimming the reference voltages on continue to be generated from the internal bandgap

each chip during production ensures that the voltage, as in the internal reference mode. It is

reference voltages are well-matched across different therefore important to ensure that the common-mode

chips. voltage of the externally-forced reference voltages

matches to within 50mV of VCM.

All bias currents required for the internal operation of

the device are set using an external resistor to The second method of forcing the reference voltages

ground at the ISET pin. Using a 56kΩresistor on externally can be accessed by pulling INT/EXT low,

ISET generates an internal reference current of 20mA. and programming the serial interface to drive the

This current is mirrored internally to generate the bias external reference mode through the CM pin (register

current for the internal blocks. Using a larger external bit called EXT_REF_VCM). In this mode, CM

resistor at ISET reduces the reference bias current becomes configured as an input pin that can be

and thereby scales down the device operating power. driven from external circuitry. The internal reference

However, it is recommended that the external resistor buffers driving REFT and REFB are active in this

be within 10% of the specified value of 56kΩso that mode. Forcing 1.5V on the CM pin in the mode

the internal bias margins for the various blocks are results in REFT and REFB coming to 2.5V and 0.5V,

proper. respectively. In general, the voltages on REFT and

REFB in this mode are given by Equation 3 and

Buffering the internal bandgap voltage also generates Equation 4:

the common-mode voltage VCM, which is set to the

midlevel of REFT and REFB. It is meant as a

reference voltage to derive the input common-mode if (3)

the input is directly coupled. It can also be used to

derive the reference common-mode voltage in the

external reference mode. Figure 58 shows the (4)

suggested decoupling for the reference pins. The state of the reference voltage internal buffers

during various combinations of the ADS_PD,

INT/EXT, and EXT_REF_VCM register bits is

described in Table 18.

Figure 58. Suggested Decoupling on the Reference Pins

Product Folder Link(s): AFE5805

AFE5805

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SBOS421D –MARCH 2008–REVISED MARCH 2010

Table 18. State of Reference Voltages for Various Combinations of ADS_PD and INT/EXT

PIN, REGISTER BIT INTERNAL BUFFER STATE

ADS_PD pin 0 0 1 1 0 0 1 1

INT/EXT pin 0 1 0 1 0 1 0 1

EXT_REF_VCM 0 0 0 0 1 1 1 1

REFT buffer 3-state 2.5V 3-state 2.5V(1) 1.5V + VCM/1.5V Do not use 2.5V(1) Do not use

REFB buffer 3-state 0.5V 3-state 0.5V(1) 1.5V – VCM/1.5V Do not use 0.5V(1) Do not use

CM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use

(1) Weakly forced with reduced strength. Poor RMS jitter (> 100ps), combined with inadequate

power-supply design (for example, supply voltage

POWER SUPPLIES drops and ripple increases), can affect LVDS timing.

The AFE5805 operates on three supply rails: a digital As a result, occasional glitches might be observed on

1.8V supply, and the 3.3V and 5V analog supplies. At the AFE5805 outputs. If this phenomenon is

initial power-up, the part is operational in TGC mode, observed, or if clock jitter and LVDD noise are

with the registers in the respective default concerns in the overall system, the registers

configurations (see Table 2). described in Table 19 can be written as part of the

initialization sequence in order to stabilize LVDS

In TGC mode, only the VCA (attenuator) draws a low clock timing and SNR performance.

current (typically 8mA) from the 5V supply. Switching

into the CW mode, the internal V/I-amplifiers are then Table 19. Address and Data in Hexadecimal

powered from the 5V rails as well, raising the

operating current on the 5V rail. At the same time, the ADDRESS DATA

post-gain amplifiers (PGA) are being powered down, 01 0010h

thereby reducing the current consumption on the 3.3V D1 0140h

rail (refer to the Electrical Characteristics table for DA 0001h

details on TGC mode and CW mode current

consumption). E1 0020h

02 0080h

All analog supply rails for the AFE5805 should be low 01 0000h

noise, including the 3.3V digital supply DVDD that

connects to the internal logic blocks of the VCA within Writing to these registers has the following additional

the AFE5805. It is recommended to tie the DVDD effects:

pins to the same 3.3V analog supply as the AVDD1/2

pins, rather than a different 3.3V rail that may also a. Total chip power increases by approximately

provide power to other logic device in the system. 8mW—this includes a current increase of about

Transients and noise generated by those devices can 1.9mA on AVDD1 and about 1.1mA on LVDD.

couple into the AFE5805 and degrade overall device b. With reference to the LVDS Timing Diagram and

performance. the Definition of Setup and Hold Times,

LCLKP/LCLKM shift by about 100ps to the left

CLOCK JITTER, POWER NOISE, SNR, AND relative to CLK and OUTP/OUTM. This shift

LVDS TIMING causes the data setup time to reduce by 100ps

and the data hold time to increase by 100ps.

As explained in application note SLYT075, ADC clock c. The clock propagation delay (tPROP) is reduced by

jitter can degrade ADC performance. Therefore, it is approximately 2ns. The typical and minimum

always preferred to use a low jitter clock to drive the values for this specification are reduced by 2ns,

AFE5805. To ensure the performance of the and the maximum value is reduced by 1.5ns.

AFE5805, a clock with a jitter of 1ps RMS or better is

expected. However, it might not be always possible to Power-supply noise usually can be minimized if

use this clock configuration for practical reasons. With grounding, bypassing, and printed circuit board (PCB)

a higher clock jitter, the SNR of the AFE5805 may be layout are well managed. Some guidelines can be

degraded as well as the LVDS timing stability. In found in the Grounding and Bypassing and Board

addition, clean and stable power supplies are always Layout sections.

preferred to maximize device SNR performance and

ensure LVDS timing stability.

Product Folder Link(s): AFE5805

AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010

www.ti.com

GROUNDING AND BYPASSING High-speed mixed signal devices are sensitive to

various types of noise coupling. One primary source

The AFE5805 distinguishes between three different of noise is the switching noise from the serializer and

grounds: AVSS1 and AVSS2 (analog grounds), and the output buffer/drivers. For the AFE5805, care has

LVSS (digital ground). In most cases, it should be been taken to ensure that the interaction between the

adequate to lay out the printed circuit board (PCB) to analog and digital supplies within the device is kept to

use a single ground plane for the AFE5805. Care a minimal amount. The extent of noise coupled and

should be taken that this ground plane is properly transmitted from the digital and analog sections

partitioned between various sections within the depends on the effective inductances of each of the

system to minimize interactions between analog and supply and ground connections. Smaller effective

digital circuitry. Alternatively, the digital (LVDS) inductance of the supply and ground pins leads to

supply set consisting of the LVDD and LVSS pins can improved noise suppression. For this reason, multiple

be placed on separate power and ground planes. For pins are used to connect each supply and ground

this configuration, the AVSS and LVSS grounds sets. It is important to maintain low inductance

should be tied together at the power connector in a properties throughout the design of the PCB layout by

star layout. use of proper planes and layer thickness.

All bypassing and power supplies for the AFE5805

should be referenced to this analog ground plane. All BOARD LAYOUT

supply pins should be bypassed with 0.1mF ceramic Proper grounding and bypassing, short lead length,

chip capacitors (size 0603 or smaller). In order to and the use of ground and power-supply planes are

minimize the lead and trace inductance, the particularly important for high-frequency designs.

capacitors should be located as close to the supply Achieving optimum performance with a

pins as possible. Where double-sided component high-performance device such as the AFE5805

mounting is allowed, these capacitors are best placed requires careful attention to the PCB layout to

directly under the package. In addition, larger bipolar minimize the effects of board parasitics and optimize

decoupling capacitors (2.2mF to 10mF, effective at component placement. A multilayer PCB usually

lower frequencies) may also be used on the main ensures best results and allows convenient

supply pins. These components can be placed on the component placement.

PCB in proximity (< 0.5in or 12.7mm) to the AFE5805

itself. In order to maintain proper LVDS timing, all LVDS

traces should follow a controlled impedance design

The AFE5805 internally generates a number of (for example, 100Ωdifferential). In addition, all LVDS

reference voltages, such as the bias voltages (VB1 trace lengths should be equal and symmetrical; it is

through VB6). Note that in order to achieve optimal recommended to keep trace length variations less

low-noise performance, the VB1 pin must be than 150mil (0.150in or 3.81mm).

bypassed with a capacitor value of at least 1mF; the

recommended value for this bypass capacitor is Additional details on PCB layout techniques can be

2.2mF. All other designed reference pins can be found in the Texas Instruments Application Report

bypassed with smaller capacitor values, typically MicroStar BGA Packaging Reference Guide

0.1mF. For best results choose low-inductance (SSYZ015B), which can be downloaded from the TI

ceramic chip capacitors (size 402) and place them as web site (www.ti.com).

close as possible to the device pins as possible.

Product Folder Link(s): AFE5805

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (October, 2008) to Revision D Page

• Changed Output transconductance specification notation from V/I to IOUT/VIN ..................................................................... 4

• Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............ 13

• Corrected PD polarity and notation in Figure 38 ................................................................................................................ 20

• Changed CS input line connection to SPI interface and register block in Figure 41 .......................................................... 21

• Changed footnote 2 for Table 2 .......................................................................................................................................... 23

• Changed ADC_RESET to ADS_RESET in VCA Reset section ......................................................................................... 25

• Changed hyperlink pointer in paragraph five of Power-Down Modes section .................................................................... 29

• Changed last sentence of second paragraph in CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING ............... 47

• Added 02, 0080h to Table 19 ............................................................................................................................................. 47

• Changed note a; updated values of current increase from 4mW to 8mW and 0.6mA to 1.9mA ....................................... 47

Changes from Revision B (July, 2008) to Revision C Page

• Corrected VCM subscript for common-mode voltage (internal) and VCM output current ........................................................ 4

• Changed AVDD2 to AVDD1 in description of pin L9 .......................................................................................................... 10

• Added statement about register initialization to Register Initialization section ................................................................... 21

• Changed bit D7 for address 42; added values of '1' for all four functions .......................................................................... 24

• Changed VCM pin to CM pin .............................................................................................................................................. 24

• Revised External Reference section, Equation 1 and Equation 2 to reflect CM pin instead of VCM pin ........................... 33

• Corrected second paragraph of Analog-to-Digital Conversion section to change VCM to CM .......................................... 40

• Changed total input capacitance description from 30pF to 16pF ....................................................................................... 41

• Changed VCM to CM .......................................................................................................................................................... 45

• Changed common-mode voltage VCM to VCM and related references to CM pin, including Equation 3 and

Equation 4 ........................................................................................................................................................................... 46

• Changed VCM to VCM ......................................................................................................................................................... 47

• Added CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING,Clock Jitter, Power Noise, SNR, and LVDS

Timing ................................................................................................................................................................................. 47

Product Folder Link(s): AFE5805

PACKAGE OPTION ADDENDUM

www.ti.com 15-Jan-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

AFE5805ZCF ACTIVE NFBGA ZCF 135 160 Green (RoHS

& no Sb/Br) SNAGCU Level-3-260C-168 HR Contact TI Distributor

or Sales Office

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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