1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
HI-RELIABILITY PRODUCT
WF4M16-XDTX5
November 1999 Rev.3
2x2Mx16 5V FLASH MODULE
ADVANCED*
■Data Polling and Toggle Bit feature for detection of program
or erase cycle completion.
■Supports reading or programming data to a sector not being
erased.
■Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
■RESET pin resets internal state machine to the read mode.
■Ready/Busy (RY/BY) output for direction of program or erase
cycle completion.
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
Note: For programming information refer to Flash Programming 16M5
Application Note.
FEATURES
■Access Time of 90, 120, 150ns
■Packaging:
• 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213).
Fits standard 56 SSOP footprint.
■Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8 chip
• Any combination of sectors can be erased. Also supports
full chip erase.
■Minimum 100,000 Write/Erase Cycles Minimum
■Organized as two banks of 2Mx16; User Configurable as
4 x 2Mx8
■Commercial, Industrial, and Military Temperature Ranges
■5 Volt Read and Write. 5V ± 10% Supply.
■Low Power CMOS
FIG. 1 PIN CONFIGURATION FOR WF4M16-XDTX5
BLOCK DIAGRAM
TOP VIEW
56 CSOP PIN DESCRIPTION
I/O0-15 Data Inputs/Outputs
A0-20 Address Inputs
WE Write Enable
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
RY/BY Ready/Busy
RESET Reset
I/O
0-7
CS
1
I/O
8-15
CS
2
C S
3
C S
4
A
0-20
OE
WE
RY/BY
RESET
2M x 8 2M x 8 2M x 8 2M x 8
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1
and CS3 both active. CS2 and CS4 control the same data bus. Reads
cannot be done with CS2 and CS4 both active.
3. Address compatible with Intel 2M8 56 SSOP.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS1
A12
A13
A14
A15
NC
CS2
NC
A20
A19
A18
A17
A16
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
NC
RESET
A11
A10
A9
A1
A2
A3
A4
A5
A6
A7
GND
A8
V
CC
I/O9
I/O1
I/O8
I/O0
A0
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to VSS VT-2.0 to +7.0 V
Power Dissipation PT8W
Storage Temperature Tstg -65 to +125 °C
Short Circuit Output Current IOS 100 mA
Endurance - Write/Erase Cycles 100,000 min cycles
(Mil Temp)
Data Retention (Mil Temp) 20 years
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage V CC 4.5 5.5 V
Ground VSS 00V
Input High Voltage VIH 2.0 VCC + 0.5 V
Input Low Voltage V IL -0.5 +0.8 V
Operating Temperature (Mil.) TA -55 +125 °C
Operating Temperature (Ind.) TA -40 +85 °C
DC CHARACTERISTICS - CMOS COMPATIBLE
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE at VIH.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
Parameter Symbol Conditions Min Max Unit
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 µA
Output Leakage Current ILOx32 VCC = 5.5, VIN = GND to VCC 10 µA
VCC Active Current for Read (1) ICC1 CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5 82 mA
VCC Active Current for Program or Erase (2) ICC2 CS = VIL, OE = VIH, VCC = 5.5 1 22 m A
VCC Standby Current ICC3 VCC = 5.5, CS = VIH, f = 5MHz 8.0 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85xVcc V
Low VCC Lock-Out Voltage VLKO 3.2 4.2 V
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
V
IN
= 0 V, f = 1.0 MHz
45 pF
WE capacitance CWE
V
IN
= 0 V, f = 1.0 MHz
45 pF
CS capacitance CCS
V
IN
= 0 V, f = 1.0 MHz
15 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
25 pF
Address input capacitance CAD
V
IN
= 0 V, f = 1.0 MHz
45 pF
This parameter is guaranteed by design but not tested.
3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L000µs
VCC Setup Time tVCS 50 50 50 µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
NOTES:
1. Typical value for t WHWH1 is 7µs.
2. Typical value for t WHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling. AC CHARACTERISTICS – READ-ONLY OPERATIONS
(VCC = 5.0V, TA = -55°C to +125°C)
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 90 120 150 ns
Address Access Time tAVQV tACC 90 120 150 ns
Chip Select Access Time tELQV tCE 90 120 150 ns
Output Enable to Output Valid tGLQV tOE 40 50 55 ns
Chip Select High to Output High Z (1) tEHQZ tDF 20 30 35 ns
Output Enable High to Output High Z (1) t GHQZ tDF 20 30 35 ns
Output Hold from Addresses, CS or OE Change, tAXQX tOH 000ns
whichever is First
1. Guaranteed by design, not tested.
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
FIG. 2
AC TEST CIRCUIT AC TEST CONDITIONS
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
I
Current Source
D.U.T.
C = 50 pf
eff
I
OL
V
≈
1.5V
(Bipolar Supply)
Z
Current Source
OH
Parameter Symbol -90 -120 -150 Unit
Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 90 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time t AVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 µs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000µs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) t OEH 10 10 10 ns
NOTES:
1. Typical value for t WHWH1 is 7µs.
2. Typical value for t WHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
Addresses
CS
OE
WE
Outputs High Z
Addresses Stable
t
OE
t
RC
Output Valid
t
CE
t
ACC
t
OH
High Z
t
DF
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIG. 4
WRITE/ERASE/PROGRAM
OPERATION, WE CONTROLLED
Addresses
CS
OE
WE
Data
5.0 V
5555H PA PA
tWC
tCS
PD D7DOUT
tAH
tWPH
tDH
tDS
Data Polling
tAS tRC
tWP
A0H
tOE tDF
tOH
tCE
tGHWL
tWHWH1
7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
FIG. 5
AC WAVEFORMS CHIP/SECTOR
ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
Addresses
CS
OE
WE
Data
V
CC
5555H 2AAAH 2AAAH SA5555H 5555H
t
WP
t
CS
t
VCS
10H/30H55H80H55H AAHAAH
t
AH
t
GHWL
t
WPH
t
DH
t
DS
t
AS
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
FIG. 6
AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS
Addresses
CS
OE
WE
Data
V
CC
5555H 2AAAH 2AAAH SA5555H 5555H
t
WP
t
CS
t
VCS
10H/30H55H80H55H AAHAAH
t
AH
t
GHWL
t
WPH
t
DH
t
DS
t
AS
9White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
Addresses
WE
OE
CS
Data
5.0 V
5555H PA PA
t
WC
t
WS
PD D
7
D
OUT
t
AH
t
CPH
t
CP
t
DH
t
DS
Data Polling
t
AS
t
GHEL
A0H
t
WHWH1
FIG. 7
ALTERNATE CS CONTROLLED
PROGRAMMING OPERATION TIMINGS
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
23.63 (0.930) ± 0.25 (0.010)
12.96 (0.510)
± 0.13 (0.005)
0.51
(0.020) TYP
0.51 (0.020)
± 0.13 (0.005)
0.18 (0.007)
± 0.03 (0.001)
21.59 (0.850) TYP
16.13 (0.635)
± 0.13 (0.005)
0.25 (0.010)
± 0.05 (0.002)
0.80 (0.031) TYP
10.93 (0.430)
± 0.13 (0.005)
4.57 (0.180)
MAX
PIN 1 IDENTIFIER 0° / -4°
1.58 (0.062) TYP
3.50 (0.138)
± 0.83 (0.032)
0.51 (0.020) TYP
+
DETAIL "A"
SEE DETAIL "A" R 0.18
(0.007)
PACKAGE 213: 56 LEAD, DUAL CAVITY CERAMIC SOP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
FIG. 8 ALTERNATE PIN CONFIGURATION FOR WF4M16W-XDTX5
BLOCK DIAGRAM
TOP VIEW
56 CSOP PIN DESCRIPTION
I/O0-15 Data Inputs/Outputs
A0-20 Address Inputs
WE Write Enable
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
RY/BY Ready/Busy
RESET Reset
I/O
0-7
CS
1
I/O
8-15
CS
2
C S
3
C S
4
A
0-20
OE
WE
RY/BY
RESET
2M x 8 2M x 8 2M x 8 2M x 8
NOTE:
1. RY/BY is an open drain output and should be pulled-up to Vcc with an
external resistor.
2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1
and CS3 both active. CS2 and CS4 control the same data bus. Reads
cannot be done with CS2 and CS4 both active.
3. Address compatible with Intel 1M16 56 SSOP, with the addition of
A20
at pin 8
. Also refer to Note 2.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS1
A11
A12
A13
A14
NC
CS2
A20
A19
A18
A17
A16
A15
V
CC
GND
I/O6
I/O14
I/O7
I/O15
RY/BY
OE
WE
NC
I/O13
I/O5
I/O12
I/O4
V
CC
NC
RESET
A10
A9
A8
A0
A1
A2
A3
A4
A5
A6
GND
A7
V
CC
I/O9
I/O1
I/O8
I/O0
NC
NC
CS3
CS4
I/O2
I/O10
I/O3
I/O11
GND
11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WF4M16-XDTX5
ORDERING INFORMATION
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5 V
DEVICE GRADE:
M = Military, 883 Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
DT = 56 Lead Dual Cavity CSOP (Package 213)
fits standard 56 SSOP footprint
ACCESS TIME (ns)
ORGANIZATION, 2M x 16
User configurable as 4 x 2M x 8
Flash
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