MOSEL VITELIC
1
V4DJX132BLT/V4DJ132BLT
1M X 32 HIGH PERFORMANCE
EDO/FPM MEMORY MODULE
PRELIMINARY
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
Features
■
1M x 32-bit organization
■
V4DJX132BLT EDO
■
V4DJ132BLT FPM
■
Utilizes High Performance 1M x 8 CMOS
DRAMs
■
Fast access times: 50, 60 ns
■
Low power dissipation
■
CAS before RAS refresh, RAS only refresh, and
Hidden refresh capability
■
Standard 72-lead single-in-line module
■
Single 5 V
±
10% Power Supply
■
TTL Interface
Description
The V4DJX132BLT/V4DJ132BLT memory
Module is organized as 1,097,152 x 32 bits in a 72-
lead single-in-line module. The 1M x 32 memory
module uses 4 Mosel-Vitelic 1M x 8 DRAMs. The
x32 modules are ideal for use in high performance
computer systems where increased memory
density and fast access times are required.
Device Usage Chart
Operating
Temperature
Range
Organization Module Type Access Time (ns) Power
1M x 32 SIMM 50 60 Std
0
°
C to 70
°
C• ••• •
V4DJX132BLT/V4DJ132BLT Pin Configuration
1363772
1 VSS
2 I/O1
3 I/O17
4 I/O2
5 I/O18
6 I/O3
7 I/O19
8 I/O4
9 I/O20
10 VCC
11 NC
12 A0
13 A1
14 A2
15 A3
16 A4
17 A5
18 A6
19 NC
20 I/O5
21 I/O21
22 I/O6
23 I/O22
24 I/O7
25 I/O23
26 I/O8
27 I/O24
28 A7
29 NC
30 VCC
31 A8
32 A9
33 NC
34 RAS2
35 NC
36 NC
37 NC
38 NC
39 VSS
40 CAS0
41 CAS2
42 CAS3
43 CAS1
44 RAS0
45 NC
46 NC
47 WE
48 NC
49 I/O9
50 I/O25
51 I/O10
52 I/O26
53 I/O11
54 I/O27
55 I/O12
56 I/O28
57 I/O13
58 I/O29
59 VCC
60 I/O30
61 I/O14
62 I/O31
63 I/O15
64 I/O32
65 I/O16
66 NC
67 PD1*
68 PD2*
69 PD3*
70 PD4*
71 NC
72 VSS
* Default Presence Detect is NC, Optional configurations are available.
Pin Names
Name Description
A0–A9 Addresses
I/O1–I/O32 Data Inputs/Outputs
RAS0, RAS2 Row Address Strobes
CAS0–CAS3 Column Address Strobes
WE Write Enable
PD1–PD4 Presence Detect
V
CC
Power Supply (5V)
V
SS
Ground
NC No Connection
2
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
Absolute Maximum Ratings*
Ambient Temperature
Under Bias................................ –10
°
C to +80
°
C
Storage Temperature (plastic)..... –55
°
C to +125
°
C
Voltage on any Pin Except V
CC
Relative to V
SS
.........................–1.0 V to +7.0 V
Voltage on V
CC
Relative to V
SS
.....–1.0 V to +7.0 V
Data Out Current..........................................50 mA
Power Dissipation
V4DJX132BLT.............................................3.5 W
V4DJ132BLT...............................................4.5 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
°
C, f = 1.0MHz, V
CC
= 5 V
±
10%, V
SS
= 0 V
*Note:
Capacitance is samples and not 100% tested.
Symbol Parameter Min. Max. Unit
C
IN
Input Capacitance,
Address Inputs 48 pF
C
IN
Input Capacitance, W 64 pF
C
(I/O)
Input/Output Capacitance,
I/O1–I/O32 10 pF
C
IN(RAS)
Input Capacitance,
RAS0, RAS2 16 pF
C
IN(CAS)
Input Capacitance,
CAS0–CAS3 16 pF
Part Number Information
MOSEL VITELIC
MANUFACTURED
4
NUMBER OF
COMPONENTS MEM.
FAMILY
PWR.
V 4 DJ 1 32 B LT
SPEED
50 ns
60 ns
LT = 1-SIDED SIMM (TIN LEAD, LOW PROFILE)
1K REFRESH
4
DEPTH
BLANK = 5V
DRAM SOJ
MEM.
TYPE
X
X = EDO PAGE MODE
BLANK = FPM
32
WIDTH PACKAGE
CODE
DEVICE
FEATURES
Edge Connector
Pin Names
1 VSS 2 I/O1
3 I/O17 4 I/O2
5 I/O18 6 I/O3
7 I/O19 8 I/O4
9 I/O20 10 VCC
11 NC 12 A0
13 A1 14 A2
15 A3 16 A4
17 A5 18 A6
19 NC 20 I/O5
21 I/O21 22 I/O6
23 I/O22 24 I/O7
25 I/O23 26 I/O8
27 I/O24 28 A7
29 NC 30 VCC
31 A8 32 A9
33 NC 34 RAS2
35 NC 36 NC
37 NC 38 NC
39 VSS 40 CAS0
41 CAS2 42 CAS3
43 CAS1 44 RAS0
45 NC 46 NC
47 WE 48 NC
49 I/O9 50 I/O25
51 I/O10 52 I/O26
53 I/O11 54 I/O27
55 I/O12 56 I/O28
57 I/O13 58 I/O29
59 VCC 60 I/O30
61 I/O14 62 I/O31
63 I/O15 64 I/O32
65 I/O16 66 NC
67 PD1 68 PD2
69 PD3 70 PD4
71 NC 72 VSS
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
3
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
V4DJX132BLT/V4DJ132BLT Functional Diagram
RAS
CAS I/O1
I/O2
I/O3
I/O4
WE
OE
V53C808H
V53C808H
V53C808H
V53C808H
CX
RAS0
CAS0
A0–A9
VCC
GND
WE
RAS
CAS I/O1
I/O2
I/O3
I/O4
WE
OE
A0–A9
A0–A9
CAS1
RAS
CAS I/O1
I/O2
I/O3
I/O4
WE
OE
A0–A9
CAS2
RAS2
RAS
CAS I/O1
I/O2
I/O3
I/O4
WE
OE
A0–A9
CAS3
DQ4
DQ7
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
VCC
GND
4
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
DC and Operating Characteristics
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, unless otherwise specified.
Symbol Parameter Access
Time
V4DJX132BLT
Unit Test Conditions NotesMin. Typ. Max.
I
LI
Input Leakage Current
(any input pin) –40 40
µ
A V
SS
≤
V
IN
≤
V
CC
I
LO
Output Leakage Current
(for High-Z State) –40 40
µ
A V
SS
≤
V
OUT
≤
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating 50 580 mA t
RC
= t
RC
(min.) 1, 2
60 540
I
CC2
V
CC
Supply Current,
TTL Standby 2 mA RAS, CAS at V
IH
other inputs
≥
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh 50 580 mA t
RC
= t
RC
(min.) 2
60 540
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
50 340 mA Minimum cycle 1, 2
60 320
I
CC5
V
CC
Supply Current,
Standby, Output Enabled 8 mA RAS = V
IH
, CAS = V
IL
other inputs
≥
V
SS
1
I
CC6
V
CC
Supply Current,
CMOS Standby 8 mA RAS
≥
V
CC
– 0.2 V,
CAS
≥
V
CC
– 0.2 V,
All other inputs
≥
V
SS
I
CC7
Self Refresh Current 1.6 mA CBR Cycle with t
RAS
≥
t
RASS
(Min.) and CAS = V
IL
;
WE = V
CC
–0.2V; A0–A8 and
D
IN
= V
CC
–0.2V
V
CC
Supply Voltage 4.5 5.0 5.5 V
V
IL
Input Low Voltage –1 0.8 V 3
V
IH
Input High Voltage 2.4 V
CC
+ 1 V 3
V
OL
Output Low Voltage 0.4 V I
OL
= 2 mA
V
OH
Output High Voltage 2.4 V I
OH
= –2 mA
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
5
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
DC and Operating Characteristics
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol Parameter Access
Time
V4DJ132BLT
Unit Test Conditions NotesMin. Typ. Max.
ILI Input Leakage Current
(any input pin) –40 40 µA VSS ≤ VIN ≤ VCC
ILO Output Leakage Current
(for High-Z State) –40 40 µA VSS ≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1 VCC Supply Current,
Operating 50 840 mA tRC = tRC (min.) 1, 2
60 800
ICC2 VCC Supply Current,
TTL Standby 16 mA RAS, CAS at VIH
other inputs ≥ VSS
ICC3 VCC Supply Current,
RAS-Only Refresh 50 840 mA tRC = tRC (min.) 2
60 800
ICC4 VCC Supply Current,
Fast Page Mode
Operation
50 400 mA Minimum cycle 1, 2
60 360
ICC5 VCC Supply Current,
Standby, Output Enabled 8 mA RAS = VIH, CAS = VIL
other inputs ≥ VSS
1
ICC6 VCC Supply Current,
CMOS Standby 8 mA RAS ≥ VCC – 0.2 V,
CAS ≥ VCC– 0.2 V,
All other inputs ≥ VSS
VCC Supply Voltage 4.5 5.0 5.5 V
VIL Input Low Voltage –1 0.8 V 3
VIH Input High Voltage 2.4 VCC + 1 V 3
VOL Output Low Voltage 0.4 V IOL = 4.2 mA
VOH Output High Voltage 2.4 V IOH = –5 mA
6
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
V4DJX132BLT
Unit Notes
50 60
Min. Max. Min. Max.
1 tRAS RAS Pulse Width 50 75K 60 75K ns
2 tRC Read or Write Cycle Time 90 110 ns
3 tRP RAS Precharge Time 30 40 ns
4 tCSH CAS Hold Time 50 60 ns
5 tCAS CAS Pulse Width 9 15 ns
6 tRCD RAS to CAS Delay 19 36 20 45 ns
7 tRCS Read Command Setup Time 0 0 ns 4
8 tASR Row Address Setup Time 0 0 ns
9 tRAH Row Address Hold Time 9 10 ns
10 tASC Column Address Setup Time 0 0 ns
11 tCAH Column Address Hold Time 7 10 ns
12 tRSH (R) RAS Hold Time (Read Cycle) 15 15 ns
13 tCRP CAS to RAS Precharge Time 5 5 ns
14 tRCH Read Command Hold Time Referenced to CAS 0 0 ns 5
15 tRRH Read Command Hold Time Referenced to RAS 0 0 ns 5
16 tCAC Access Time from CAS (EDO) 14 15 ns 6, 7, 14
17 tRAC Access Time from RAS 50 60 ns 6, 8, 9
18 tCAA Access Time from Column Address 24 30 ns 6, 7, 10
19 tLZ CAS to Low-Z Output 0 0 ns 16
20 tHZ CAS to High-Z Output 0 8 0 10 ns 16
21 tAR Column Address Hold Time from RAS 40 50 ns
22 tRAD RAS to Column Address Delay Time 14 26 15 30 ns 11
23 tRSH (W) RAS or CAS Hold Time in Write Cycle 14 15 ns
24 tCWL Write Command to CAS Lead Time 14 15 ns
25 tWCS Write Command Setup Time 0 0 ns 12, 13
26 tWCH Write Command Hold Time 7 10 ns
27 tWP Write Pulse Width 7 10 ns
28 tWCR Write Command Hold Time from RAS 40 50 ns
29 tRWL Write Command to RAS Lead Time 14 15 ns
30 tDS Data in Setup Time 0 0 ns 14
31 tDH Data in Hold Time 7 10 ns 14
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
7
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
32 tRWC
(RMW) Read-Modify-Write Cycle Time 130 170 ns
33 tRRW
(RMW) Read-Modify-Write Cycle RAS Pulse Width 87 105 ns
34 tCWD CAS to WE Delay 34 40 ns 12
35 tRWD RAS to WE Delay in Read-Modify-Write Cycle 68 85 ns 12
36 tCRW CAS Pulse Width (RMW) 52 65 ns
37 tAWD Col. Address to WE Delay 42 58 ns 12
38 tPC EDO Page Mode Read or Write Cycle Time 19 27 ns
39 tCP CAS Precharge Time 7 10 ns
40 tCAR Column Address to RAS Setup Time 24 30 ns
41 tCAP Access Time from Column Precharge 27 34 ns 7
42 tDHR Data in Hold Time Referenced to RAS 40 50 ns
43 tCSR CAS Setup Time CAS-before-RAS Refresh 10 10 ns
44 tRPC RAS to CAS Precharge Time 0 0 ns
45 tCHR CAS Hold Time CAS-before-RAS Refresh 12 15 ns
46 tPCM EDO Page Mode Read-Modify-Write Cycle Time 70 85 ns
47 tCOH Output Hold After CAS Low 5 5 ns
48 tTTransition Time (Rise and Fall) 3 50 3 50 ns 15
49 tREF Refresh Interval (1024 Cycles) 16 16 ms 17
# Symbol Parameter
V4DJX132BLT
Unit Notes
50 60
Min. Max. Min. Max.
AC Characteristics (cont.)
8
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
# Symbol Parameter
V4DJ132BLT
Unit Notes
50 60
Min. Max. Min. Max.
1 tRAS RAS Pulse Width 50 75K 60 75K ns
2 tRC Read or Write Cycle Time 90 110 ns
3 tRP RAS Precharge Time 30 40 ns
4 tCSH CAS Hold Time 50 60 ns
5 tCAS CAS Pulse Width 14 15 ns
6 tRCD RAS to CAS Delay 19 36 20 43 ns
7 tRCS Read Command Setup Time 0 0 ns 4
8 tASR Row Address Setup Time 0 0 ns
9 tRAH Row Address Hold Time 9 10 ns
10 tASC Column Address Setup Time 0 0 ns
11 tCAH Column Address Hold Time 7 10 ns
12 tRSH (R) RAS Hold Time (Read Cycle) 14 15 ns
13 tCRP CAS to RAS Precharge Time 5 5 ns
14 tRCH Read Command Hold Time Referenced to CAS 0 0 ns 5
15 tRRH Read Command Hold Time Referenced to RAS 0 0 ns 5
16 tROH RAS Hold Time Referenced to OE 10 10 ns
17 tOAC Access Time from OE 14 17 ns
18 tCAC Access Time from CAS 14 17 ns 6, 7
19 tRAC Access Time from RAS 50 60 ns 6, 8, 9
20 tCAA Access Time from Column Address 24 30 ns 6, 7, 10
21 tLZ CAS to Low-Z Output 0 0 ns 16
22 tHZ Output buffer turn-off delay time 0 8 0 10 ns 16
23 tAR Column Address Hold Time
from RAS 40 45 ns
24 tRAD RAS to Column Address 14 26 15 30 ns 11
Delay Time
25 tRSH (W) RAS or CAS Hold Time in Write Cycle 14 15 ns
26 tCWL Write Command to CAS Lead Time 14 15 ns
27 tWCS Write Command Setup Time 0 0 ns 12, 13
28 tWCH Write Command Hold Time 7 10 ns
29 tWP Write Pulse Width 7 10 ns
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
9
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
30 tWCR Write Command Hold Time
from RAS 40 45 ns
31 tRWL Write Command to RAS Lead Time 14 15 ns
32 tDS Data in Setup Time 0 0 ns 14
33 tDH Data in Hold Time 7 10 ns 14
34 tWOH Write to OE Hold Time 8 10 ns 14
35 tOED OE to Data Delay Time 8 10 ns 14
36 tRWC Read-Modify-Write Cycle Time 130 170 ns
37 tRRW Read-Modify-Write Cycle RAS Pulse Width 87 105 ns
38 tCWD CAS to WE Delay 34 40 ns 12
39 tRWD RAS to WE Delay in Read-Modify-Write Cycle 68 85 ns 12
40 tCRW CAS Pulse Width (RMW) 52 65 ns
41 tAWD Col. Address to WE Delay 42 58 ns 12
42 tPC Fast Page Mode
Read or Write Cycle Time 28 40 ns
43 tCP CAS Precharge Time 7 8 ns
44 tCAR Column Address to RAS Setup
Time 24 30 ns
45 tCAP Access Time from Column Precharge 27 34 ns 7
46 tDHR Data in Hold Time Referenced
to RAS 40 50 ns
47 tCSR CAS Setup Time CAS-before-RAS Refresh 10 10 ns
48 tRPC RAS to CAS Precharge Time 0 0 ns
49 tCHR CAS Hold Time CAS-before-RAS Refresh 12 15 ns
50 tPCM Fast Page Mode Read-Modify-Write Cycle Time 70 85 ns
51 tTTransition Time (Rise and Fall) 3 50 3 50 ns 15
52 tREF Refresh Interval (1024 Cycles) 16 16 ms
# Symbol Parameter
V4DJ132BLT
Unit Notes
50 60
Min. Max. Min. Max.
AC Characteristics (cont.)
10
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in EDO Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to –1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to one TTL inputs and 100 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRCD will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. t RAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
MOSEL VITELIC
V4DJX132BLT/V4DJ132BLT
11
V4DJX132BLT/V4DJ132BLT Rev. 0.3 May 1999
Package Dimensions
.86 [21.76]
4.25 [107.95]
4.25 [107.95]
1 36 37 72
3.98 [101.19]
1.75 [44.45] .25 [6.35]1.75 [44.45]
.25 [6.35]
.05 [1.27]
.06 [1.57]
Unit in inches [mm]
A
Detail A
.40 [10.16]
R = .06 [1.57]
.13 [3.38]
D = .12 [3.175]
.08 [2.03]
.04 [1]
.251 [6.375]
.1 [2.54]
.010 [0.25]
0.195
0.050
Tolerances: ±0.005 [0.13]
MOSEL VITELIC
WORLDWIDE OFFICES V4DJX132BLT/V4DJ132BLT
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
© Copyright 1999, MOSEL VITELIC Inc. 5/99
Printed in U.S.A.
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