ISSI®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
IS71VPCF16KS04
IS71VPCF16QS04
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. 00A
09/05/02
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip
Package (MCP) — 16 Mbit Simultaneous Operation Flash
Memory and 4 Mbit Static RAM
MCP FEATURES
•Power supply voltage 2.7V to 3.3V
•High performance:
Flash: 70ns maximum access time
SRAM: 85ns maximum access time
•Package: 56-ball BGA
•Operating Temperature: -25C to +85C
FLASH FEATURES
•Power Dissipation:
Read Current at 1 Mhz: 7 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5 µA maximum
•Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
•Low-Power Mode:
A period of no activity causes flash to enter a low-
power state
•Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank.
•Sector Erase Architecture:
8 sectors of 4K words each and 31 sectors of 32K words
each (16 Mbit)
Any combination of sectors, or the entire flash can
be simultaneously erased
•Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
•Program Algorithms:
Automatically writes and verifies data at specified
address
•Hidden ROM Region:
64KB with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
•Data Polling and Toggle Bit:
Allow for detection of program or erase cycle
completion
•Ready-Busy output (RY/BY): Detection of program
or erase cycle completion
•Over 100,000 write/erase cycles
•Low supply voltage (Vccf ≤ 2.5V) inhibits writes
•WP/ACC input pin:
If VIL, allows protection of boot sectors
If VIH, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
•Boot sector: Top or Bottom
SRAM FEATURES (4 Mb density)
•Power Dissipation:
Operating: 40 mA maximum
Standby: 7 µA maximum
•Chip Selects: CE1s, CE2s
•Power down feature using CE1s, or CE2s
•Data retention supply voltage: 1.5 to 3.3 volt
•Byte data control: LBs (DQ0–DQ7), UBs
(DQ8–DQ15) — in x16 mode
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 16 Mbit Flash/4
Mbit SRAM having a data bus of either x8 or x16. The 16 Mbit
flash is composed of 1,048,576 words of 16 bits or 2,097,152
bytes of 8 bits. The 4Mb SRAM has 262,144 words of 16 bits
or 524,288 bytes of 8 bits. Data lines DQ0-DQ7 handle the
x8 format, while lines DQ0-DQ15 handle the x16 format.
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase opera-
tions. The flash can be programmed in system using this
3.0V supply, or can be programmed in a standard EPROM
programmer.
The 16 Mbit flash/4 Mbit SRAM is offered in a 69-ball BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 85ns and
the SRAM access time is 85ns.
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized perfor-
mance can be achieved by first initializing a program or erase
function in one bank, then immediately starting a read from
the other bank. Both operations would then be operating
simultaneously, with zero latency.
PRELIMINARY INFORMATION
SEPTEMBER 2002
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
LOGIC SYMBOL
MCP BLOCK DIAGRAM
A0-A19, A-1
SA
CEf
CE1s
CE2s
OE
WE
WP/ACC
RESET
UBs
LBs
I/Of
I/Os
DQ0-DQ15
21
16 or 8
RY/BY
GND
GND
V
CCf
RY/BY
4-MBIT
Static RAM
16-MBIT
Flash Memory
DQ0-DQ15/A-1
A0-A19
A0-A19
A-1
WP/ACC
RESET
CEf
I/Of
SA
LBs
UBs
WE
OE
CE1s
CE2s
I/Os
DQ0-DQ15
A0-A17
V
CCS
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
STATE CONTROL
&
COMMAND REGISTER
RESET
WE
CE
BYTE
WP/ACC
DQ0-DQ15
A0-A19
A0-A19
A0-A19
A0-A19
A0-A19
Lower Bank Address
Upper Bank Address
Y -Decoder
Latches and
Control Logic
Lower
Bank
Upper
Bank
X-Decoder
Y -Decoder
Latches and
Control Logic
X-Decoder
Status
Control
DQ0-DQ15
DQ0-DQ15
DQ0-DQ15
OE BYTE
OE BYTE
V
CC
GND
RY/BY
FLASH MEMORY BLOCK DIAGRAM
FLASH BANK ORGANIZATION
Note:
For device part number, see Part Number Logic Diagram or Ordering Information
Organization Type Bank 1 Size Bank 2 Size Boot Block
Type K 4Mb 12Mb Top
Type Q 8Mb 8Mb Bottom
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
4Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
PIN DESCRIPTIONS
A0-A17 Address Inputs, Common
A18-A19, A-1 Address Inputs, Flash
DQ0-DQ15/A-1 Data Inputs/Outputs
RESET Reset
CE1s, CE2s Chip Selects, SRAM
I/Of I/O Configuration, Flash
CEf Chip Enable Input, Flash
OE Output Enable Input
WE Write Enable Input
I/Os I/O Configuration, SRAM
LBsLower-byte Control(DQ0-DQ7), SRAM
UBsUpper-byte Control (DQ8-DQ15), SRAM
WP/ACC Write Protect/Acceleration Pin,
Flash
RY/BY Ready/Busy Output
SA High Order Address Pin, SRAM (x8)
NC No Connection
Vccf Power, Flash
Vccs Power, SRAM
GND Ground
PIN CONFIGURATION
A B C D E F G H
8
7
6
5
4
3
2
1
SRAM Onl
y
Flash Only
Shared
A15 NC NC A16 I/Of GND
A11 A12 A13 A14 SA
DQ15/A-1
DQ7 DQ14
A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5
WE CE2s NC DQ4 Vccs I/Os
WE/ACC RESET RY/BY
DQ3 Vccf DQ11
Land
Index
LBs UBs A18 A17 DQ1 DQ9 DQ10 DQ2
A7 A6 A5 A4 GND OE DQ0 DQ8
A3 A2 A1 A0 CEf CE1s
Note:
1. There is no solder ball. This land should be open electrically.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
OPERATION(1,3) CECE
CECE
CEfCECE
CECE
CE1s CE2s OEOE
OEOE
OE WEWE
WEWE
WE SA(6) LBLB
LBLB
LBsUBUB
UBUB
UBsDQ
0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WPWP
WPWP
WP/ACC(5)
Full Standby H H X X X X X X High-Z High-Z H X
H X L X X X X X High-Z High-Z H X
Output Disable H L H H H X X X High-Z High-Z H X
H L H X X X H H High-Z High-Z H X
L H X H H X X X High-Z High-Z H X
L X L H H X X X High-Z High-Z H X
Read from Flash(2) LHXLHXXXDOUT DOUT HX
LXLLHXXXDOUT DOUT HX
Write to Flash L H X H L X X X DIN DIN HX
LXLHLXXX DIN DIN HX
Read from SRAM H L H L H X L L DOUT DOUT HX
H L H L H X H L High-Z DOUT HX
HLHLHXLHDOUT High-Z H X
Write to SRAM H L H X L X L L DIN DIN HX
H L H X L X H L High-Z DIN HX
HLHXLXLH DIN High-Z H X
Temporary Sector XXXXXXXX X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X High-Z High-Z L X
Reset X X L X X X X X High-Z High-Z L X
Boot Block Sector XXXXXXXX X X X L
Write Protection
Notes:
1. Any operations not indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. SA: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM= Word Mode: I/Os = Vccs)
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
6Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
Notes:
1. Any operations not indicated this column are inhibited..
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. SA: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
OPERATION(1,3) CECE
CECE
CEfCE1CE1
CE1CE1
CE1sCE2s DQ15/A-1 OEOE
OEOE
OE WEWE
WEWE
WE SA(6) LBLB
LBLB
LBsUBUB
UBUB
UBsDQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WP/ACC(5)
Full Standby H H X X X X X X X High-Z High-Z H X
H X L X X X X X X High-Z High-Z H X
Output Disable H L H X H H X X X High-Z High-Z H X
H L H X X X X H H High-Z High-Z H X
L H X A-1 H H X X X High-Z High-Z H X
L X L A-1 H H X X X High-Z High-Z H X
Read from Flash(2) L H X A-1 L H X X X DOUT DOUT HX
L X L A-1 L H X X X DOUT DOUT HX
Write to Flash L H X A-1 H L X X X DIN DIN HX
L X L A-1 H L X X X DIN DIN HX
Read from SRAM H L H X L H X L L DOUT DOUT HX
H L H X L H X H L High-Z DOUT HX
HL H X LHXLHDOUT High-Z H X
Write to SRAM H L H X X L X L L DIN DIN HX
H L H X X L X H L High-Z DIN HX
HL H X XLXLH DIN High-Z H X
Temporary Sector X X X X X X X X X X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X X High-Z High-Z L X
Reset X X L X X X X X X High-Z High-Z L X
Boot Block Sector X X X X X X X X X X X X L
Write Protection
User Bus Operations (Flash=BYTE mode: I/Of = GND, SRAM= Word Mode: I/Os = Vccs)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
DEVICE BUS OPERATIONS
User Bus Operations (Flash=WORD mode: I/Of = Vccf, SRAM= Byte Mode: I/Os = GND
Notes:
1. Any operations not indicated this column are inhibited..
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. LBs, UBs: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
OPERATION(1,3) CECE
CECE
CEfCECE
CECE
CE1s CE2s OEOE
OEOE
OE WEWE
WEWE
WE SA LBLB
LBLB
LBs(6) UBUB
UBUB
UBs(6) DQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WPWP
WPWP
WP/ACC(5)
Full Standby H H X X X X X X High-Z High-Z H X
H X L X X X X X High-Z High-Z H X
Output Disable H L H H H X X X High-Z High-Z H X
H L H X X X H H High-Z High-Z H X
L H X H H X X X High-Z High-Z H X
L X L H H X X X High-Z High-Z H X
Read from Flash(2) LHXLHXXXDOUT DOUT HX
LXLLHXXXDOUT DOUT HX
Write to Flash L H X H L X X X DIN DIN HX
LXLHLXXX DIN DIN HX
Read from SRAM H L H L H SA X X DOUT High-Z H X
Write to SRAM H L H X L SA X X DIN High-Z H X
Temporary Sector XXXXXXXX X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X High-Z High-Z L X
Reset X X L X X X X X High-Z High-Z L X
Boot Block Sector XXXXXXXX X X X L
Write Protection
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
8Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
Notes:
1. Any operations not indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. LBs, UBs: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Byte mode: I/Of = GND, SRAM= Byte Mode: I/Os = GND)
OPERATION(1,3) CECE
CECE
CEfCE1CE1
CE1CE1
CE1sCE2s DQ15/A-1 OEOE
OEOE
OE WEWE
WEWE
WE SA LBLB
LBLB
LBs(6) UBUB
UBUB
UBs(6) DQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WP/ACC(5)
Full Standby H H X X X X X X X High-Z High-Z H X
H X L X X X X X X High-Z High-Z H X
Output Disable H L H X H H X X X High-Z High-Z H X
H L H X X X X H H High-Z High-Z H X
L H X A-1 H H X X X High-Z High-Z H X
L X L A-1 H H X X X High-Z High-Z H X
Read from Flash(2) L H X A-1 L H X X X DOUT DOUT HX
L X L A-1 L H X X X DOUT DOUT HX
Write to Flash L H X A-1 H L X X X DIN DIN HX
L X L A-1 H L X X X DIN DIN HX
Read from SRAM H L H X L H SA X X DOUT High-Z H X
Write to SRAM H L H X X L SA X X DIN High-Z H X
Temporary Sector X X X X X X X X X X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X X High-Z High-Z L X
Reset X X L X X X X X X High-Z High-Z L X
Boot Block Sector X X X X X X X X X X X X L
Write Protection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
FLASH - TOP BOOT SECTOR ADDRESS
Sector Sector
Type Sector Address Size (x8) (x16)
K A19-A12 KB/KW Address Range Address Range
Bank2 SA0 00000xxx 64/32 000000h–00FFFFh 000000h–007FFFh
Bank2 SA1 00001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh
Bank2 SA2 00010xxx 64/32 020000h–02FFFFh 010000h–017FFFh
Bank2 SA3 00011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
Bank2 SA4 00100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
Bank2 SA5 00101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
Bank2 SA6 00110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
Bank2 SA7 00111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
Bank2 SA8 01000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
Bank2 SA9 01001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
Bank2 SA10 01010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
Bank2 SA11 01011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
Bank2 SA12 01100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
Bank2 SA13 01101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
Bank2 SA14 01110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
Bank2 SA15 01111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
Bank2 SA16 10000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
Bank2 SA17 10001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
Bank2 SA18 10010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
Bank2 SA19 10011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
Bank2 SA20 10100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
Bank2 SA21 10101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
Bank2 SA22 10110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
Bank2 SA23 10111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
Bank1 SA24 11000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
Bank1 SA25 11001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
Bank1 SA26 11010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
Bank1 SA27 11011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
Bank1 SA28 11100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
Bank1 SA29 11101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
FLASH - TOP BOOT SECTOR ADDRESS (Continued)
Note:
The address range is A19:A-1 in byte mode (I/Of=VIL ) or A19:A0 in word mode (I/Of=VIH ). The bank address bits
are A19 and A18 for Type K.
Device Sector
Address Size (x8) (x16)
A19-A12 KB/KW Address Range Address Range
Type K 11111xxx 64/32 1F0000h-1FFFFFh F8000h-FFFFFh
FLASH - TOP BOOT SECURITY SECTOR ADDRESSES
(Hidden-ROM)
Sector Sector
Type Sector Address Size (x8) (x16)
K A19-A12 KB/KW Address Range Address Range
Bank1 SA30 11110xxx 64/32 1E0000h–1EFFFFh F0000h–F7FFFh
Bank1 SA31 11111000 8/4 1F0000h–1F1FFFh F8000h–F8FFFh
Bank1 SA32 11111001 8/4 1F2000h–1F3FFFh F9000h–F9FFFh
Bank1 SA33 11111010 8/4 1F4000h–1F6FFFh FA000h–FAFFFh
Bank1 SA34 11111011 8/4 1F6000h–1F7FFFh FB000h–FBFFFh
Bank1 SA35 11111100 8/4 1F8000h–1F9FFFh FC000h–FCFFFh
Bank1 SA36 11111101 8/4 1FA000h–1FBFFFh FD000h–FDFFFh
Bank1 SA37 11111110 8/4 1FC000h–1FDFFFh FE000h–FEFFFh
Bank1 SA38 11111111 8/4 1FE000h–1FFFFFh FF000h–FFFFFh
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
FLASH - BOTTOM BOOT SECTOR ADDRESS
Sector Sector
Type Sector Address Size (x8) (x16)
Q A19-A12 KB/KW Address Range Address Range
Bank1 SA0 00000000 8/4 000000h–001FFFh 000000h–000FFFh
Bank1 SA1 00000001 8/4 002000h–003FFFh 001000h–001FFFh
Bank1 SA2 00000010 8/4 004000h–005FFFh 002000h–002FFFh
Bank1 SA3 00000011 8/4 006000h–007FFFh 003000h–003FFFh
Bank1 SA4 00000100 8/4 008000h–009FFFh 004000h–004FFFh
Bank1 SA5 00000101 8/4 00A000h–00BFFFh 005000h–005FFFh
Bank1 SA6 00000110 8/4 00C000h–00DFFFh 006000h–006FFFh
Bank1 SA7 00000111 8/4 00E000h–00FFFFh 007000h–007FFFh
Bank1 SA8 00001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh
Bank1 SA9 00010xxx 64/32 020000h–02FFFFh 010000h–017FFFh
Bank1 SA10 00011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
Bank1 SA11 00100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
Bank1 SA12 00101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
Bank1 SA13 00110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
Bank1 SA14 00111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
Bank1 SA15 01000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
Bank1 SA16 01001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
Bank1 SA17 01010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
Bank1 SA18 01011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
Bank1 SA19 01100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
Bank1 SA20 01101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
Bank1 SA21 01110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
Bank1 SA22 01111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
Bank2 SA23 10000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
Bank2 SA24 10001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
Bank2 SA25 10010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
Bank2 SA26 10011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
Bank2 SA27 10100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
Bank2 SA28 10101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
Bank2 SA29 10110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
FLASH - BOTTOM BOOT SECTOR ADDRESS (Continued)
FLASH - BOTTOM BOOT SECURITY SECTOR ADDRESSES
(Hidden-ROM)
Sector Sector
Type Sector Address Size (x8) (x16)
Q A19-A12 KB/KW Address Range Address Range
Bank2 SA30 10111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
Bank2 SA31 11000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
Bank2 SA32 11001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
Bank2 SA33 11010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
Bank2 SA34 11011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
Bank2 SA35 11100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
Bank2 SA36 11101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
Bank2 SA37 11110xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
Bank2 SA38 11111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
Note:
The address range is A19:A-1 in byte mode (I/Of=VIL ) or A19:A0 in word mode (I/Of=VIH ). The bank address bit is
A19 for Type Q.
Device Sector
Address Size (x8) (x16)
A19-A12 KB/KW Address Range Address Range
Type Q 00000xxx 64/32 000000h-00FFFFh 00000h-07FFFh
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 00000XXX SA0
01
SGA1 00010XXX SA1 to SA3
11
SGA2 001XXXXX SA4 to SA7
SGA3 010XXXXX SA8 to SA11
SGA4 011XXXXX SA12 to SA15
SGA5 100XXXXX SA16 to SA19
SGA6 101XXXXX SA20 to SA23
SGA7 110XXXXX SA24 to SA27
00
SGA8 11101XXX SA28 to SA30
10
SGA9 11111000 SA31
SGA10 11111001 SA32
SGA11 11111010 SA33
SGA12 11111011 SA34
SGA13 11111100 SA35
SGA14 11111101 SA36
SGA15 11111110 SA37
SGA16 11111111 SA38
SECTOR GROUP ADDRESS (TYPE K)
(Top Boot Block)
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 00000000 SA0
SGA1 00000001 SA1
SGA2 00000010 SA2
SGA3 00000011 SA3
SGA4 00000100 SA4
SGA5 00000101 SA5
SGA6 00000110 SA6
SGA7 00000111 SA7
01
SGA8 00010XXX SA8 to SA10
11
SGA9 001X XXXX SA11 to SA14
SGA10 010XXXXX SA15 to SA18
SGA11 011XXXXX SA19 to SA22
SGA12 100XXXXX SA23 to SA26
SGA13 101XXXXX SA27 to SA30
SGA14 110XXXXX SA31 to SA34
00
SGA15 11101XXX SA35 to SA37
10
SGA16 11111XXX SA38
SECTOR GROUP ADDRESS (TYPE Q)
(Bottom Boot Block)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
Type A12 to A19 A6A1A0A–1(1) Code (HEX)
Manufacturer’s Code X VIL VIL VIL VIL 04h
TYPE K Device ID Byte X VIL VIL VIH VIL 28h
Word X VIL VIL VIH X 2228h
TYPE Q Device ID Byte X VIL VIL VIH VIL 35h
Word X VIL VIL VIH X 2235h
Sector Group Protect Sector VIL VIH VIL VIL 01h(2)
Group
Address
FLASH MEMORY AUTOSELECT CODES
Note:
1. A–1 is only used for Byte mode.
2. Output 01h at protected sector address and output 00h at unprotected sector address.
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
FLASH MEMORY COMMAND DEFINITIONS
Note:
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A0 to A6.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Command Sequence
Bus
6
1
1
3
2
2
4
1
3
4
6
4
Bus
Write
Cycle
Req'd
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Cycle Write Cycle Write Cycle Read/Write Cycle Cycle
—
PA
Data
Read / Reset * 1
Hidden-Rom Exit
* 5
Extended Sector
Group Protection
* 3
Set to Fast Mode
Fast Program * 2
Data
Data
2AAH
555H
—
Addr. Addr.
XXXH
BA
BA
555H
AAH
—
Addr. Addr.
Data
—
Addr.
Data
—
Addr.
——
—
Data
Read / Reset —
PA
SPA
XXXH
—
60H
F0H*6
—
SPA
—
—
PA
—
—
SPA
—
—
—
—
—
—
RA
—
—
—
—
—
—
—
—
—
—
55H
—
—
—
—
—
—
—
—
—
—
—
—
HRA
555H
AAAH
SA
—
—
—
—
—
—
—
—
—
30H
10H
—
—
—
30H
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55H
55H
55H
55H
55H
—
—
55H
PD
F0H
AAH
AAH
AAH
AAH
F0H —
—
RD
—
AAH
PD
AAH
—
—
—
—
—
SD
—
—
PD
AAH
00H
A0H
80H
80H
—
—
20H
—
—
40H
—
88H
A0H
80H
90H
AAH
B0H
30H
—
555H
AAAH
—
—
XXXH
BA
XXXH
AAH
A0H
90H
60H
98h
AAh
AAH
AAH
AAH
55H
55H
55H
55H
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
55H
AAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
555H
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
(HRBA)
2AAH
555H
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
AAAH
XXXH
Reset from Fast
Mode * 2
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
Autoselect
Program
Chip Erase
Sector Erase
Sector Erase
Suspend
Sector Erase
Resume
Query * 4
Hidden-ROM
Entry
Hidden-ROM
Program
* 5
Hidden-ROM
Erase
* 5
90H
—
—
55H
55H
—
(BA)
AAAH
(HRBA)
AAAH
555H
AAAH
3
3
4
6
(BA)
1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
MCP ABSOLUTE MAXIMUM RATINGS(1,2,3)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –25 to +85 °C
TSTG Storage Temperature –55 to +125 °C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for Data, –0.3 to VCCf + 0.4 V
Address and Control Pins –0.3 to VCCs + 0.4 V
VIN RESET(5) -0.5 TO +13.0 V
VIN WP/ACC(6) -0.5 TO +10.5 V
VCCf/VCCs Voltage on Vcc Supply Relative to GND(4) –0.3 to 4.0 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
4. Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for
periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.3 V. During voltage transitions, input or
I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns.
5. Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS to –2.0 V for periods
of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input
voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
6. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for
periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0V for periods of up
to 20 ns, when VCCf is applied.
Type Q (Bottom Boot Type)
Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area
Type K (Top Boot Type) :
A15 = A16 = A17 = A18 = A19 = 1
Type Q (Bottom Boot Type) :
A15 = A16 = A17 = A18 = A19 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data.
Output 01h at protected sector addresses and output 00h at
unprotected sector addresses.
The system should generate the following address patterns;
Word mode : 555h or 2AAh to addresses A0 to A10
Byte mode : AAAh or 555h to addresses A–1 and A0 to A10
Address bits A12 to A19 = X = “H” or “L” for all address
commands except for Program Address (PA), Sector Address
(SA),and Bank Address (BA).
Bus operations are defined in “Device Bus Operations”.
RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased.
The combination of A19 , A18 , A17 , A16 , A15 , A14 , A13 ,
and A12 will uniquely select any sector.
BA = Bank address (A15 to A19 )
SPA = Sector group address to be protected.
Set sector group address (SGA) and (A6 , A1 , A0 ) = (0, 1, 0)
for protect; or SGA and (A6, A1, A0) = (1,1,0) for unprotect.
HRA= Address of the Hidden-ROM area
Type K (Top Boot Type)
Word mode: 0F8000h to 0FFFFFh
Byte mode: 1F0000h to 1FFFFFh
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
MCP OPERATING RANGE
Range Ambient Temperature VCCF,VCCS
Industrial –25°C to +85°C 2.7–3.3V
CAPACITANCE(1)
Symbol Parameter Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 11 14 pF
COUT Output Capacitance VOUT = 0V 12 16 pF
CIN2 Control Pin Capacitance VIN = 0V 14 16 pF
CIN3WP/ACC Pin Capacitance VIN = 0V 17 20 pF
Notes:
1. Test conditions: TA = 25°C, f = 1 MHz
STANDARD VOLTAGE RANGE VCC = 2.7-3.3 V
FLASH
MEMORY SRAM UNITS
Max Access Time 70 85 ns
CE Access 70 85 ns
OE Access 30 45 ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 19
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
Symbol Parameter Test Conditions Min. Max. Unit
ILI Input Leakage VIN=VSS to VCCf, VCCs -1.0 1.0 µA
ILO Output Leakage VOUT=VSS to VCCf, VCCs -1.0 1.0 µA
VIL Input Low Level -0.3 0.5 V
VIH Input High Level 2.4 VCC + 0.3(2) V
VID Voltage for Sector 11.5 12.5 V
Protection, and Temporary
Sector Unprotection (RESET)(1)
VACC Voltage for Program 8.5 9.5 V
Acceleration ( WP/ACC)(1)
VOL Output Low Level VCCf = V CCf min., VCCS=VCCS min. — 0.45 V
IOL = 1.0mA
VOH Output High Level VCCf = VCCf min., VCCS=VCCS min. 2.4 — V
IOH = -0.5mA
VLKO Flash Low Vccf 2.3 2.5 V
MCP DC CHARACTERISTICS
Notes:
1. Applicable f or only VCCf applying.
2. VCC indicates low er of VCCf or VCCs.
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
20 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
FLASH DC CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
ILIT RESET Inputs V CCf=VCCf max., VCCs=VCCs max. — 35 µA
Leakage Current RESET = 12.5V
ILIA ACC Inputs VCCf=VCCf max., VCCs=VCCs max. — 20 µA
Leakage Current WP/ACC = Vacc max.
ICC1f FLASH Vcc (1) CEf=VIL tCycle = 5Mhz Byte — 13 mA
Active Current (Read) OE=VIH tCycle = 5Mhz Word — 15
tCycle = 1Mhz Byte — 7
tCycle = 1Mhz Word — 7
ICC2f FLASH Vcc Active(2) CEf=VIL —35mA
Current(Program/Erase) OE=VIH
ICC3f FLASH Vcc Active(4) CEf=VIL Byte — 48 mA
Current OE=VIH Word 50
(Read-While-Program)
ICC4f FLASH Vcc Active(4) CEf=VIL Byte — 48 mA
Current OE=VIH Word 50
(Read-While-Erase)
ICC5f FLASH Vcc Active CEf=VIL —35mA
Current OE=VIH
(Erase-Suspend-Program)
ISB1f FLASH Vcc VCCf = Vcc max, CEf= VCCf = + 0.3V — 5 µA
Standby Current RESET, CEf, WP/ACC = VCCf = + 0.3V
ISB2f FLASH Vcc VCCf = Vcc max, RESET= VSS = + 0.3V — 5 µA
Standby Current WP/ACC = VCCf = + 0.3V
(RESET)
ISB3f FLASH Vcc(3) VCCf = Vcc max. CEf, = VSS = + 0.3V — 5 µA
Standby Current RESET, WP/ACC = VCCf = + 0.3V
(Auto Sleep Mode) VIN = VCCf + 0.3V OR VSS + 0.3V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns..
4. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 21
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
JEDEC Standard
Parameter Symbol Symbol Condition Min Unit
CE Recover Time — tCCR —0ns
AC CHARACTERISTICS - CECE
CECE
CE TIMING
TIMING DIAGRAM FOR ALTERNATING SRAM TO FLASH
CEf
CE1s
CE2s
tCCR tCCR
tCCR tCCR
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
22 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
09/05/02
FLASH READ ONLY SWITCHING CHARACTERISTICS
(Over Operating Range)
Symbol Parameter Min. Max. Min. Max. Unit
tRC Cycle Time 70 85 — ns
tACC Address to Output Delay — 70 — 85 ns
tCE Chip Enable to Output Delay — 70 — 85 ns
tOE Output Enable to Output Delay — 30 — 35 ns
tDF Chip Enable to Output High-Z — 25 — 30 ns
tDF Output Enable to Output High-Z — 25 — 30 ns
tOH Output Hold Time from Addresses, 0 — 0 — ns
CEf or OE, Whichever Occurs First
tREADY RESET Pin Low to Read Mode — 20 — 20 µs
FLASH AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 0.5 x VCCf
and Reference Level
Output Load 1 TTL gate and 30pF
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 23
Rev. 00A
09/05/02
IS71VPCF16KS04, IS71VPCF16QS04 ISSI
®
FLASH READ CYCLE
ADDRESS
DQ
CEf
OE
WE
Address Stable
Output valid High-Z
High-Z
t
OEH
t
RC
t
OE
t
DF
t
CE
t
ACC
t
OH