HT0324A (5.0V SPECIFICATION) 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD August. 2000 VER 0.0 TOMATO LSI Inc. HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD HT0324A Specification revision history Content Version 0.0 1. Operating voltage range : VDD = 2.4V ~ 5.5V TOMATO LSI Inc. 2 Ver 0.0 Date August. 2000 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 CONTENTS 1. INTRODUCTION ----------------------------------------------------------------------------------------------------------- 5 2. FEATURES --------------------------------------------------------------------------------------------------------------- 5 3. BLOCK DIAGRAM ----------------------------------------------------------------------------------------------------- 7 4. PAD CONFIGURATION -----------------------------------------------------------------------------------------------4-1. Pad center coordinates ------------------------------------------------------------------------------------------- 8 9 5. PIN DESCRIPTION ---------------------------------------------------------------------------------------------------- 12 6. FUNCTIONAL DESCRIPTION ----------------------------------------------------------------------------------6-1. Microprocessor interface ---------------------------------------------------------------------------------------a. Chip select input b. Interface c. Parallel interface (PS = "H") d. Serial interface (PS = "L") e. Busy flag f. Data accessing 6-2. Display data RAM (DDRAM) -------------------------------------------------------------------------------------a. Display data RAM b. Page address circuit c. Column address circuit d. Line address circuit e. Segment control circuit 6-3. LCD display circuit ---------------------------------------------------------------------------------------------------a. Oscillator b. Display timing generator circuit c. Common output control circuit 6-4. LCD driver circuit --------------------------------------------------------------------------------------------------6-5. Power supply circuits ------------------------------------------------------------------------------------------a. Voltage converter circuits b. Voltage regulator circuits c. Voltage follower circuits d. High power mode 6-6. Reference circuit examples -------------------------------------------------------------------------------------6-7. Reset circuit -------------------------------------------------------------------------------------------------------- 16 16 7. PROGRAM INSTRUCTION ---------------------------------------------------------------------------------------7-1. Read display data ------------------------------------------------------------------------------------------------7-2. Write display data -----------------------------------------------------------------------------------------------7-3. Read status ----------------------------------------------------------------- --------------------------------------7-4. Display ON / OFF ----------------------------------------------------------------------------------------------------7-5. Initial display line ------------------------------------------------------------------------------------------------7-6. Reference voltage select -------------------------------------------------------------------------------------7-7. Set page address -----------------------------------------------------------------------------------------------7-8. Set column address ----------------------------------------------------------------------------------------------7-9. ADC select --------------------------------------------------------------------------------------------------------7-10. Reverse display ON / OFF----------------------------------------------------------------------------------------7-11. Entire display ON / OFF-------------------------------------------------------------------------------------------7-12. Select LCD bias -------------------------------------------------------------------------------------------------7-13. Set modify-read --------------------------------------------------------------------------------------------------7-14. Reset modify-read ----------------------------------------------------------------------------------------------7-15. Reset ---------------------------------------------------------------------------------------------------------------7-16. SHL select ---------------------------------------------------------------------------------------------------------- 34 35 35 36 36 37 37 38 39 39 39 40 40 40 40 41 41 TOMATO LSI Inc. 3 19 22 23 24 31 32 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-17. Power control --------------------------------------------------------------------------------------------------------7-18. Regulator resistor select -----------------------------------------------------------------------------------------7-19. Set static indicator state ------------------------------------------------------------------------------------------7-20. NOP ----------------------------------------------------------------------------------------------------------------------7-21. Test instruction --------------------------------------------------------------------------------------------------------7-22. Power save (Compound instruction) --------------------------------------------------------------------------7-23. Referential instruction set flow----------------------------------------------------------------------------------8. SPECIFICATIONS -------------------------------------------------------------------------------------------------------8-1. Absolute maximum ratings --------------------------------------------------------------------------------------8-2. DC characteristics ---------------------------------------------------------------------------------------------------8-3. AC characteristics -------------------------------------------------------------------------------------------------a. Read / write characteristics (8080-series MPU) b. Read / write characteristics (6800-series MPU) c. Serial interface characteristics d. Reset input timing e. Display control output timing 42 42 43 43 43 44 45 49 49 49 50 9. REFERENCE APPLICATION --------------------------------------------------------------------------------------------- 56 9-1. MPU interface ------------------------------------------------------------------------------------------------------56 9-2. Connections between HT0324A and LCD panel -----------------------------------------------------------------57 9-3. TCP pin layout (sample) ----------------------------------------------------------------------------------------63 9-4. Application circuit for serial -------------------------------------------------------------------------------------64 TOMATO LSI Inc. 4 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 1. INTRODUCTION The HT0324A is a driver and controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65 common and 132 segment driver circuits. This chip is connected directly to a microprocessor (MPU), accepts serial or 8-bit parallel display data and stores in an on-chip Display Data RAM (DDRAM) of 65 x 132 bits. It provides a high-flexible display section due to one to one correspondences between on-chip DDRAM bits and LCD panel pixels. And it performs DDRAM read / write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. 2. FEATURES Driver output circuits -. 65 common outputs / 132 segment outputs On-chip display data RAM (DDRAM) -. Capacity: 65 x 132=8,580 bits -. RAM bit data "1": a dot of display is illuminated. -. RAM bit data "0": a dot of display is not illuminated. Multi-chip operation -. Master and slave mode available Applicable duty-ratios Duty ratio Applicable LCD bias Maximum display area 1/65 1/9 or 1/7 65 x 132 1/55 1/8 or 1/6 55 x 132 1/49 1/8 or 1/6 49 x 132 1/33 1/6 or 1/5 33 x 132 Microprocessor (MPU) interface -. High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series -. Serial inter-face (only write operation) available Various Function set -. Display ON/OFF, set initial display line, set page address, set column address, read status, write / read display data, select segment driver output, reverse display ON/OFF, entire display ON/OFF, select LCD bias, set/reset modify-read, select common driver output, control display power circuit, select internal regulator resistor ratio for V0 voltage regulation, electronic volume, set static indicator state. -. H/W and S/W reset available -. Static drive circuit equipped internally for indicators with 4 flashing modes Built-in analog circuits -. On-chip Oscillator circuit for display clock(external clock can also be used) -. High performance voltage converter (with booster ratios of x2, x3, x4 and x5, where the step-up reference voltage can be used externally) -. High accuracy voltage regulator(temperature coefficient: -0.05%/ or external input) -. Electronic contrast control function (64 steps) -. Vref = 2.1V 3% (V0 voltage adjustment voltage) -. High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity) TOMATO LSI Inc. 5 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Operating voltage range -. Supply voltage (VDD): 2.4 to 5.5V -. LCD driving voltage (VLCD = V0 -VSS): 4.5 to 15.0V Low power consumption -. Operating power : 40A Typ, (VDD = 3V, x4 boosting[VCI is VDD], V0=11V, internal power supply ON, display OFF and normal mode is selected) -. Standby power : 10A Max. (during power save[standby] mode) Operating Temperatures -. Wide range of operating temperatures : -40 to 85 CMOS Process Package type -. Gold bumped chip and TCP available TOMATO LSI Inc. 6 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VDD V0 V1 V2 V3 V4 VSS 33 COMMON DRIVER CIRCUITS COM63 COMS COM32 132 SEGMENT DRIVER CIRCUITS DISPLAY DATA CONTROL CIRCUIT /HPM SEG129 SEG130 SEG131 SEG0 SEG1 SEG2 COMS COM0 COM31 3. BLOCK DIAGRAM 33 COMMON DRIVER CIRCUITS COMMON OUTPUT CONTROL CIRCUIT MS VOLTAGE FOLLOWER CL V0 VR INTRS REF VEXT VOLTAGE REGULATOR I/O I/O BUFFER BUFFER DISPLAY DISPLAYDATA DATARAM RAM 65 65xx132 132==8,580 8,580BITS BITS PAGE PAGE ADDRESS ADDRESS CIRCUIT CIRCUIT COLUMN COLUMNADDRESS ADDRESS CIRCUIT CIRCUIT LINE LINE ADDRESS ADDRESS CIRCUIT CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT M FRS FR DISP DSEL0 DSEL1 VOUT C1C1+ C2C2+ C3+ C4+ VCI VOLTAGE CONVERTER STATUS REGISTER INSTRUCTION REGISTER BUS HOLDER INSTRUCTION DECODER Figure 3-1. block diagra TOMATO LSI Inc. 7 DB0 DB1 DB2 DB3 DB4 DB5 (SCLK)DB6 C68 (SID)DB7 /RESET PS RW_/WR RS E_/RD CS2 /CS1 MPU INTERFACE CIRCUIT(PARALLEL & SERIAL) OSCILLATOR CLS HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 4. PAD CONFIGURATION 292 145 293 144 (0,0) X SL09SL0211 F111 Y HT0324A TOP VIEW 320 117 1 116 Figure 4-1. Chip configuration Table 4-1. Pad dimensions ITEM Pad No. Chip size (Include scribe lane) - Pad pitch Y 9540 2310 70 118~143, 146~291, 294~319 60 1~2, 93~95, 115~116, 117~118 , 143~144, 145~146, 291~292, 293~294, 319~320 80 2~93, 95~115 50 102 118~143, 294~319 102 40 146~291 40 102 1, 94, 116, 145, 292 55 102 117, 144, 293, 320 102 55 Bumped pad height Unit m 18 3 (Typ.) All pad 108m 30m 30m 30m 30m 30m 30m 42m 108m (3960, -305) Figure 4-3. ILB align key 42m 108m 60m 8 (-3960, 415) 42m 108m 42m 30m 30m 30m 30m (3920, 425) Figure 4-2. COG align key TOMATO LSI Inc. X 2~93, 95~115 Bumped pad size (Bottom) (-3920, -305) Size HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 4-1. PAD CENTER COORDINATES Table 4-2. Pad center coordinates PAD No. PAD name X Y [Unit: um] PAD No. PAD name X 1 DUMMY -4045 -991 51 C4+ -535 2 FRS -3965 -991 52 C3+ -465 3 FR -3895 -991 53 C3+ -395 4 NC0 -3825 -991 54 C1-325 5 NC1 -3755 -991 55 C1-255 6 M -3685 -991 56 C1+ -185 7 CL -3615 -991 57 C1+ -115 8 DISP -3545 -991 58 C2+ -45 9 VSS -3475 -991 59 C2+ 25 10 VSS -3405 -991 60 C295 11 /CS1 -3335 -991 61 C2165 12 CS2 -3265 -991 62 VDD 235 13 VDD -3195 -991 63 VEXT 305 14 /RESET -3125 -991 64 VEXT 375 15 RS -3055 -991 65 REF 445 16 VSS -2985 -991 66 VSS 515 17 RW _/WR -2915 -991 67 V1 585 18 E_/RD -2845 -991 68 V1 655 19 VDD -2775 -991 69 V2 725 20 DB0 -2705 -991 70 V2 795 21 DB1 -2635 -991 71 V3 865 22 DB2 -2565 -991 72 V3 935 23 DB3 -2495 -991 73 V4 1005 24 DB4 -2425 -991 74 V4 1075 25 DB5 -2355 -991 75 V0 1145 26 DB6 -2285 -991 76 V0 1215 27 DB7 -2215 -991 77 V0 1285 28 VSS -2145 -991 78 VR 1355 29 VDD -2075 -991 79 VR 1425 30 DSEL0 -2005 -991 80 VR 1495 31 DSEL1 -1935 -991 81 VSS 1565 32 VSS -1865 -991 82 VSS 1635 33 VDD -1795 -991 83 VDD 1705 34 VDD -1725 -991 84 MS 1775 35 VDD -1655 -991 85 CLS 1845 36 VDD -1585 -991 86 VSS 1915 37 VDD -1515 -991 87 C68 1985 38 VCI -1445 -991 88 PS 2055 39 VCI -1375 -991 89 VDD 2125 40 VCI -1305 -991 90 /HPM 2195 41 VSS -1235 -991 91 VSS 2265 42 VSS -1165 -991 92 INTRS 2335 43 VSS -1095 -991 93 VDD 2405 44 VSS -1025 -991 94 DUMMY 2485 45 VSS -955 -991 95 TEST0 2565 46 VOUT -885 -991 96 TEST1 2635 47 VOUT -815 -991 97 TEST2 2705 48 VOUT -745 -991 98 TEST3 2775 49 VOUT -675 -991 99 TEST4 2845 50 C4+ -605 -991 100 TEST5 2915 * 1. NC0, NC1: No Connection 2. Main VSS pad (PAD No. 41,42,43,44 and 45) have to be connected TOMATO LSI Inc. 9 Y PAD No. PAD name -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 DUMMY DUMMY COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 DUMMY DUMMY COM5 COM4 COM3 COM2 COM1 X Y 2985 3055 3125 3195 3265 3335 3405 3475 3545 3615 3685 3755 3825 3895 3965 4045 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4606 4430 4350 4290 4230 4170 4110 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -991 -860 -780 -720 -660 -600 -540 -480 -420 -360 -300 -240 -180 -120 -60 0 60 120 180 240 300 360 420 480 540 600 660 720 800 991 991 991 991 991 991 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Table 4-2. Pad center coordinates (continued) PAD No. Pad name 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 COM0 COMS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 TOMATO LSI Inc. X Y PAD No. Pad name 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 10 Ver 0.0 [Unit: um] X Y PAD No. PAD name 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM32 COM33 COM34 COM35 COM36 COM37 COM38 DUMMY DUMMY COM39 COM40 COM41 COM42 COM43 COM44 COM45 X Y -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4430 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 991 800 720 660 600 540 480 420 360 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Table 4-2. Pad center coordinates (continued) PAD No. Pad name X Y 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS DUMMY -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 -4606 300 240 180 120 60 0 -60 -120 -180 -240 -300 -360 -420 -480 -540 -600 -660 -720 -780 -860 TOMATO LSI Inc. 11 PAD No. Pad name Ver 0.0 [Unit: um] X Y PAD No. PAD name X Y HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 5. PIN DESCRIPTION Table 5-1. Pin description Power supply Name I/O VDD Description Shared with the MPU power supply terminal VCC. Power supply VSS This is a 0V terminal connected to the system GND. Main VSS pad (PAD No. 41,42,43,44 and 45) have to be connected The voltage is determined by the LCD pixel impedance-converted for application by an operational amplifier. Voltage have the following relationship: V0 >V1>V2>V3>V4>VSS(GND) When the on-chip power circuit is active, these voltages are generated according to the state of LCD bias, as shown in the table below. V0 V1 V2 V3 V4 I/O LCD Bias V1 V2 V3 V4 1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 LCD driver power supply Name I/O Description C1+ Capacitor1+ positive connection pin for the voltage converter C1- Capacitor1- negative connection pin for voltage converter C2+ Capacitor2+ positive connect ion pin for voltage converter O C2- Capacitor2- negative connection pin for voltage converter C3+ Capacitor3+ positive connection pin for voltage converter C4+ Capacitor4+ positive connection pin for voltage converter Voltage converter input / output pin Connect this pin to VSS through capacitor. VOUT I/O VR I V0 voltage adjustment pin. It is valid only when using external resistors.(INTRS="L") VCI I This is the reference voltage for the voltage converter circuit for the LCD drive. Whether internal voltage converter use or not use, this pin should be fixed. The voltage should have the following range: 2.4V VCI 5.5V VEXT I This is the externally input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used (REF = "L"). When using internal VREF, this pin is Open REF I Select the external VREF voltage via VEXT pin -REF = "L": using the external VREF -REF = "H": using the internal VREF TOMATO LSI Inc. 12 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) System control Name I/O Description Master/slave mode select input. Master makes some signals for display, and slave receives them. This for display synchronization. MS ="H": Master mode MS ="L": Slave mode MS MS I CLS OSC Circuit Power Supply CL M FRS, FR DISP H Enable Enable Output Output Output Output L Disable Enable Input Output Output Output - Disable Disable Input Input Output Input H L Built-in oscillator circuit enables / disable select pin. CLS = "H": Enable CLS = "L": Disable (external display clock input to CL pin) CLS I CL I/O Display clock input / output pin. When HT0324A is used in master/slave mode(multi-chip), the CL pin must be connected to each other. M I/O LCD AC signal input / output pin. When HT0324A is used in master/slave mode(multi-chip), the M pin must be connected to each other. MS = "H": Output MS = "L": Input FRS O Static driver segment output. This pin is used together with the FR pin. FR O Static driver common output. This pin is used together with the FRS pin. I/O LCD display blanking control input/output. When HT0324A is used in master/slave mode (multi-chip), the DISP pin must be connected to each other. MS = "H": Output MS = "L": Input I Internal resistor selects pin. This pin selects the resistor for adjusting V0 voltage level and is available only in master mode. INTRS = "H": using built-in resistors. INTRS = "L": not using built-in resistors. V0 voltage is controlled by VR pin with external resistive divider. I Power control pin of the power supply circuits for LCD driver - /HPM = "H": normal mode - /HPM = "L": high power mode This pin is valid only in master operation. DISP INTRS /HPM The LCD driver duty ratio depends on the following table. DSEL1 DSEL0 TOMATO LSI Inc. I 13 DSEL1 DSEL0 DUTY RATIO L L 1/33 L H 1/49 H L 1/55 H H 1/65 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) MPU interface Name I/O /RESET I Description Hardware reset input pin. When /RESET is "L", initialization is executed. Parallel/Serial select input pin. PS I PS Operating mode Chip select Data/ Instruction Data I/O Read/ Write Serial H Parallel /CS1, CS2 RS DB7 to DB0 E_/RD, RW_/WR - L Serial /CS1, CS2 RS DB7 (SID) Write only DB6 (SCLK) When PS= "L", DB5 to DB0 are high impedance. E_/RD and RW_/WR are fixed to either "H" or "L". With serial data input, RAM display data reading is not supported. C68 I This pin is the MPU interface switch terminal. C68 = "H": 6800 series MPU interface C68 = "L": 8080 series MPU interface /CS1 CS2 I Chip select input pin. Data input/output is enables only when /CS1 is low and CS2 is high. When chip select is non-active, DB7 to DB0 will be high impedance. RS I Register select input pin. RS = "H": The data on DB7 to DB0 is used the display data. RS = "L": The data on DB7 to DB0 is used the control data. I When interfacing to a 6800-series MPU, read/write is enabled at; RW_/WR = "H": read RW_/WR = "L": write When interfacing to an 8080-series MPU, RW_/WR is enabled at low. The signals on the data bus are latched at the rising edge of the RW_/WR signal. I When interfacing to a 6800-series MPU: Active High. This pin is used as an enable clock input pin of the 6800-series MPU. When interfacing to a 8080-series MPU: Active Low. This pin is connected to the RD signal of the 8080-series MPU. While this signal is Low, HT0324A data bus output is enabled. RW_/WR E_/RD DB7 to DB0 I/O 8-bit bi-directional data bus. It is connected to the standard 8-bit microprocessor data bus. In case of serial interface,(PS = "L") DB7: Serial input data(SID) DB6: Serial input clock(SCLK) DB5 to DB0 : High impedance When chip select is not active, DB7 to DB0 will be high impedance. NC1 NC0 I/O These are set to Open. TEST20 to TEST0 I/O These are pins for IC chip testing. These are set to Open. TOMATO LSI Inc. 14 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Table 5-1. Pin description (continued) LCD driver output Name I/O Description LCD driver output for segment. The display data and the FR signal control the output voltage of segment driver. Segment output voltage Display data SEG0 to SEG131 O FR Normal display Reverse display H H V0 V2 H L VSS V3 L H V2 V0 L L V3 VSS Power save mode VSS LCD driver output for common. The internal scanning data and M signal control the output voltage of common driver. COM0 to COM63 O Scan data FR Common output voltage H H VSS H L V0 L H V1 L L V4 Power save mode COMS O Common signal output for the icons. The output signals of two pins are the same. When this signal is not used, should be left open. In multi-chip(master/slave) mode, all COMS pin on both master and slave units are the same signal. Note: -. DUMMY, TEST0 ~ TEST20, NC0, NC1: The pins should be opened(floated). TOMATO LSI Inc. VSS 15 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6. FUNCTIONAL DESCRIPTION 6-1. MICROPROCESSOR INTERFACE a. Chip select input There are /CS1 and CS2 pins for chip selection. The HT0324A can interface with an MPU only when /CS1 is "L" and CS2 is "H". When these pins are set to any other combination, RS, E_/RD, and RW_/WR inputs are disabled and DB7 to DB0 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. b. Interface HT0324A has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 6-1. Table 6-1. Parallel / Serial interface mode PS Type /CS1 CS2 H Parallel /CS1 CS2 L Serial /CS1 CS2 C68 Interface mode H 6800-series MPU mode L 8080-series MPU mode X* Serial MPU mode X : Don't care c. Parallel interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as shown in table 6-2. The type of data transfer is determined by signals at RS, E_/RD, and RW_/WR as shown in table 6-3. Table 6-2. Microprocessor selection for parallel interface C68 /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 MPU H /CS1 CS2 RS E RW DB7 to DB0 6800-series L /CS1 CS2 RS /RD /WR DB7 to DB0 8080-series Table 6-3. Parallel data transfer Common 6800-series 8080-series Description RS E_/RD (E) RW_/WR (RW) E_/RD (/RD) RW_/WR (/WR) H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register(instruction) TOMATO LSI Inc. 16 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 d. Serial interface (PS = "L") When the HT0324A is active and serial interface has been selected, the serial data (DB7) and the serial clock (DB6) inputs are enabled. And HT0324A is not active, the internal 8-bit shift register and the 3-bit counter are reset. The serial data can be read on the rising edge of the serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. The serial data input is display data when RS is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. /CS1 CS2 SID (DB7) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCLK (DB6) RS Figure 6-1. Serial interface timing e. Busy flag The busy flag indicates whether the HT0324A is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the MPU needs not to check this flag before each instruction, which improves the MPU performance. TOMATO LSI Inc. 17 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 f. Data accessing The HT0324A uses bus holder and internal data bus for data read and data write with the MPU. When writing data from the MPU to on-chip RAM, the data is automatically transferred from the bus holder to the on-chip RAM as shown in figure 6-2. When the MPU reads data from on-chip RAM, the first data read cycle stores the data in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6-3. This means the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. Therefore, a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Internal signals MPU signals RS /WR DB7 to DB0 N D(N) D(N+1) D(N+2) D(N+3) D(N+4) N D(N) D(N+1) D(N+2) D(N+3) D(N+4) /WR Bus Holder Column Address N N+1 N+2 N+3 N+4 Figure 6-2. Write timing MPU signals RS /WR /RD DB7 to DB0 N Dummy D(N) D(N+1) D(N+2) D(N+3) Internal signals /WR /RD Bus Holder N Column Address D(N) N N+1 D(N+1) N+2 Figure 6-3. Read timing TOMATO LSI Inc. 18 D(N+2) D(N+3) D(N+4) N+3 N+4 N+5 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-2. DISPLAY DATA RAM (DDRAM) a. DDRAM The DDRAM stores pixel data for the LCD. It has 65-row (8 page x 8 bit + 1) by 132-column addressable array. Each pixel can be selected by specifying the page and the column address. The 65 rows are divided into 8 pages of 8 lines and the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB7 to DB0. The display data of DB0 to DB7 from the MPU correspond to the LCD common direction as shown in Figure 6-4. The MPU can read from and write to DDRAM through the I/O buffer, which is independent operation from signal reading for the LCD driver. This independent operation makes it possible that the MPU writes the data into the DDRAM at the same time as data is being displayed without causing the LCD flicker. DB0 0 1 1 ...... 0 COM0 ...... DB1 1 0 0 ...... 1 COM1 ...... DB2 1 1 1 ...... 0 COM2 ...... DB3 0 0 1 ...... 1 COM3 ...... DB4 1 1 0 ...... 0 COM4 ...... Display data RAM LCD display Figure 6-4. RAM-to-LCD data transfer b. Page address circuit This circuit is for providing a page address to DDRAM shown in figure 6-6. The 4-bit page address register changed by only the "Set page" instruction. Page address 8 (DB3, DB2, DB1, DB0 = 1, 0, 0, 0) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. c. Column address circuit Column address circuit has a 8-bit preset counter that provides column address to the DDRAM as shown in figure 6-6. When the "Set column address MSB / LSB" instruction is issued, 8-bit [Y7:Y0] is updated. And this address is increased by +1 each display data Read/Write instruction. This allows that the MPU display data can be accessed continuously. The increment of the column address stops with 83H. And the counter is not increased and locked if the address is specified over 84H. It is unlocked if a column address is set again by "Set column address MSB / LSB" instruction. The column address counter is independent of the page address register. The ADC select instruction makes it possible to convert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing the ADC select instruction. Refer to the figure 6-5. TOMATO LSI Inc. 19 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD SEG OUTPUT SEG0 SEG1 SEG2 SEG4 ......... SEG128 Column address[Y7:Y0] 00H 01H 02H 04H ......... 80H Display data 1 0 1 1 0 Ver 0.0 SEG129 SEG130 SEG131 81H 82H 83H 1 0 1 LCD panel display (ADC = 0) LCD panel display (ADC = 1) Figure 6-5. The relationship between the column address and the segment outputs d. Line address circuit This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Using the display start line address set command, what is normally the top line of the display can be specified. By setting the line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of DDRAM as shown in figure 6-6. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by +1 and the line address is generated for transferring the 132-bit RAM data to the display data latch circuit. However, the display data of icons is not scrolled because the MPU can not access the line address of icons. e. Segment control circuit This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire display ON /OFF instructions without changing the data in the DDRAM. TOMATO LSI Inc. 20 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Column address ADC = 0 ADC = 1 LCD output Page 4 Page 5 Page 6 Page 7 Page 8 00 01 02 03 04 05 06 .............. 7B 7C 7D 7E 7F 80 81 83 83 82 81 80 7F 7E 7D ............. 08 07 06 05 03 02 01 00 .............. Figure 6-6. Display data RAM map TOMATO LSI Inc. 21 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS 1/49 DUTY 1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH START 0 Page 3 COM output 1/33 DUTY 1 SEG131 1 SEG130 0 SEG129 0 Page 2 SEG128 0 SEG127 1 SEG126 0 SEG125 0 Page 1 SEG124 1 SEG6 0 SEG5 0 SEG4 0 Page 0 SEG3 0 SEG2 0 SEG1 0 SEG0 0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 Line address 1/65 DUTY Page address data DB3 DB2 DB1 DB0 Ver 0.0 1/55 DUTY HT0324A When the initial display line address is 1CH HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-3. LCD DISPLAY CIRCUITS a. Oscillator HT0324A implement complete on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. The oscillator circuit is enabled when MS="H" and CLS="H". When the external clock is used, set CLS="L" and imply clock signal to CL pin. b. Display timing generator circuit This circuit generates timing signals to be used for displaying LCD. The display clock (CL) is generated by oscillation clock and CL generates the clock for the line counter and the signal for the display data latch. The line address of DDRAM is generated in synchronization with CL. The 132-bit display data is latched in the display data latch circuit synchronized with CL. Reading to the display data liquid crystal driver circuit is completely independent of access to the DDRAM by the MPU. The display timing generator circuit generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and internal timing signal are shown in figure 6-7. When HT0324A is used multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 6-4 shows the M, CL, and DISP status. Table 6-4. Master and slave timing signal status Operation mode Clock M FRS, FR MS CLS CL Internal H H Output Output Output Output External H L Output Input Output Output Internal L H Input Input Output Input External L L Input Input Output Input DISP Master mode Slave mode 64 65 1 2 3 4 5 6 7 8 9 10 ............... 57 58 59 60 61 62 63 64 65 1 2 3 4 CL FR V0 V1 V2 V3 V4 VSS COM0 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS SEGn Figure 6-7. 2-frame AC driving waveform (Duty ratio = 1/65) TOMATO LSI Inc. 22 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Common output control circuit This circuit controls the relationship between the number of common output and specified duty ratio. SHL select instruction specifies the scanning direction of the common output pins. Table 6-5. The relationship between duty ratio and common output Common output pins Duty SHL COM [0:15] COM [16:23] COM [24:26] COM [27:36] COM [37:39] COM [40:47] COM [48:63] 0 COM[0:15] *NC COM[16:31] 1 COM[31:16] *NC COM[15:0] COMS 1/33 COMS 0 COM[0:23] *NC COM[24:47] 1 COM[47:24] *NC COM[23:0] 1/49 COMS 0 COM[0:26] *NC COM[27:53] 1 COM[53:27] *NC COM[26:0] 1/55 COMS 0 COM[0:63] 1 COM[63:0] 1/65 COMS *NC : No Connection 6-4. LCD DRIVER CIRCUIT This driver circuit is configured by 66-channel common drivers (including 2COMS channels) and 132channel segment drivers. This LCD panel driver voltage depends on the combination of display data and FR signal. VDD FR VSS COM0 COM1 COM0 COM2 COM3 COM4 COM1 COM5 COM6 COM7 COM2 COM8 COM9 SEG0 COM10 COM11 COM12 SEG1 COM13 COM14 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 SEG2 Figure 6-8. Segment and common timing TOMATO LSI Inc. 23 V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-5. POWER SUPPLY CIRCUITS The power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction description". Table 6-6 shows the referenced combinations in using power supply circuits. Table 6-6. Recommended power supply combinations VC,VR,VF Voltage converter Voltage regulator Voltage follower VOUT V0 V1 to V4 All Internal power supply 1, 1, 1 ON ON ON Open Open Open Voltage regulator and voltage follower 0, 1, 1 OFF ON ON External input Open Open Voltage follower 0 , 0, 1 OFF OFF ON Open External input Open All external power supply 0, 0, 0 OFF OFF OFF Open External input External input Mode Settings TOMATO LSI Inc. 24 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 a. Voltage converter circuits These circuits boost up the electric potential between VCI and VSS to 2, 3, 4 or 5 times toward positive side and boosted voltage is outputted from VOUT pin. [C1 = 1.0 to 4.7F] VDD VDD VCI VCI VDD HT0324A VDD VCI VCI VOUT VOUT C4+ C4+ C3+ C3+ C1- HT0324A C1 C1+ C1VOUT = 3 x VCI C1 C1+ VOUT = 2 x VCI C2+ C2+ C2- C1 VCI VSS VCI C2VSS C1 GND C1 VSS GND GND Figure 6-9. Two times boosting circuit VSS GND Figure 6-10. Three times boosting circuit VDD VDD VCI VCI VDD VDD VCI VCI VOUT VOUT C4+ C4+ C3+ C3+ VOUT = 5 x VCI C1 HT0324A C1 VOUT = 4 x VCI C1- HT0324A C1 C1C1 C1+ C1+ C2+ C2+ C1 C1 C1 C2- C2- VCI VCI VSS VSS C1 C1 VSS GND GND Figure 6-11. Four times boosting circuit VSS GND GND Figure 6-12. Five times boosting circuit *. The VCI voltage range must be set so that the VOUT voltage does not exceed the absolute maximum rated value. TOMATO LSI Inc. 25 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b. Voltage regulator circuits The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by the adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits as shown in figure 6-13, it is necessary to be applied internally or externally. For the equation 1, we determine V0 by Ra, Rb and VEV. Ra and Rb are connected internally or externally by INTRS pin. The voltage of electronic volume, VEV, is determined by equation 2, where the reference voltage parameter is the value selected by instruction, "Set reference voltage register", within the range 0 to 63. Refer to table 6-8. VREF voltage at Ta =25C is show in table 6-7. Rb V0 = ( 1 + ) x VEV [V] ------ (Equation 1) Ra ( 63- ) ) x VREF [V] ------ (Equation 2) VEV = ( 1 162 Table 6-7. VREF voltage at Ta =25C REF Temp. coefficient H -0.05% / C L External input VREF[V] 2.1 VEXT Table 6-8. Electronic contrast control register (Reference Voltage Parameter : , 64step) Reference Voltage V0 Contrast SV5 SV4 SV3 SV2 SV1 SV0 Parameter ( ) Low Minimum 0 0 0 0 0 0 0 : : : : 0 0 0 0 0 1 1 : : : : : : : : : : : : : : : : : : : : : : 1 0 0 0 0 0 32 (default) : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 0 62 : : : : 1 1 1 1 1 1 63 High Maximum TOMATO LSI Inc. 26 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VOUT + V0 - VEV Rb VR Ra VSS GND Figure 6-13. Internal voltage regulator circuit TOMATO LSI Inc. 27 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b-1. In case of using internal resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator resistor select" and "Set reference voltage". Table 6-9. Internal Rb / Ra ratio depending on 3-bit Data (R2, R1, R0) 3-bit data settings(R2 R1 R0: gain) 1+(Rb/Ra) 000 001 010 011 100 101 110 111 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C. 16 14 gain 111 gain 110 12 gain 101 gain 100 10 gain 011 gain 010 V0[V]8 gain 001 gain 000 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 55 Electronic volum e level Figure 6-13. Electronic volume level TOMATO LSI Inc. 28 60 63 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b-2. In case of using external resistors, Ra and Rb. (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = ( 1, 0, 0, 0, 0, 0 : = 32) 3. Maximum current flowing Ra, Rb = 1[A] From equation 1 Rb 10 = ( 1 + + Ra ) x VEV [V] ------ (Equation 3) From equation 2 (63-32) ) x 2.1 1.698 [V] ------ (Equation 4) VEV = ( 1 - 162 From equation 3 10 = 1[A] ------ (Equation 5) ( Ra + Rb ) From equation 3, 4 and 5 Ra = 1.69[M] Rb = 8.31[M] The following table shows the range of V0 depending on the above requirements. Table 6-10. V0 depending on electronic volume level Electric Volume Level V0 TOMATO LSI Inc. 0 ------ 32 ------- 63 7.57 ------ 10.00 ------- 12.43 29 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Voltage follower circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are converted by the voltage follower for increasing drive capability. The following table shows the relationship between V1 to V4 level and each duty ratio. Table 6-11. The relationship between V1 to V4 level and duty ratio Duty Ratio DSEL1 DSEL0 1/33 L L 1/49 1/55 1/65 L LCD Bias V1 V2 V3 V4 1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0 1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0 1/7 (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0 1/9 (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0 H H L H H d. High power mode The power supply circuit equipped in the HT0324A for LCD drive has very low power consumption (in normal mode : /HPM = "H"). If use for LCD panels with large loads, this low-power supply may cause display quality to degrade. When this occurs, setting the /HPM pin to "L"(high power mode) can improve the quality of the display. Moreover, if the quality of display is inadequate even after High Power mode has been set, then it is necessary to add a liquid crystal drive power supply externally (VOUT or V0 or V1 V2 V3 V4). TOMATO LSI Inc. 30 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-6. REFERECE CIRCUIT EXAMPLS When using internal regulator resistors. When not using internal regulator resistors. VD D IN TR S VD D VDD VCI VO U T C 4+ C 3+ C 1C 1+ C 2+ C 2- H T0324A INTRS MS VSS GND VCI * C1 C1 C1 C1 HT0324A * * C1 Ra V0 V1 V2 V3 V4 VSS GND C1 C1 Rb C2 C2 C1 VR C2 C2 C2 GND MS VOUT C4+ C3+ C1C1+ C2+ C2- * VR V0 V1 V2 V3 V4 VDD C2 C2 C2 C2 C2 GND GND Figure 6-15. When using all LCD power circuits (VCI = VDD, 4-time, V/C: ON, V/R: ON, V/F: ON) When using internal regulator resistors. When not using internal regulator resistors. VD D IN TR S VD D VDD VC I MS VO U T C 4+ C 3+ C 1C 1+ C 2+ C 2- H T0324A VSS INTRS External pow er supply GND HT0324A MS External power supply Ra VR Rb C2 C2 C2 C2 C2 GND VCI VOUT C4+ C3+ C1C1+ C2+ C2- VR V0 V1 V2 V3 V4 VDD VSS GND GND V0 V1 V2 V3 V4 C2 C2 C2 C2 C2 GND Figure 6-16. When using some LCD power circuits (VCI = VDD, V/C: OFF, V/R: ON, V/F: ON) TOMATO LSI Inc. 31 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 VDD INTRS VDD VCI MS VOUT C4+ C3+ C1C1+ C2+ C2- HT0324A VR V0 V1 V2 V3 V4 VSS GND External power supply C2 C2 C2 C2 C2 GND Figure 6-17. When using some LCD power circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: ON) Value of external capacitance VDD INTRS VDD VCI Item C1 C2 MS Value 1.0 ~ 4.7 0.47 ~ 1.0 VOUT C4+ C3+ C1C1+ C2+ C2- HT0324A VSS GND VR V0 V1 V2 V3 V4 External power supply GND Figure 6-18. When not using any LCD power supply circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: OFF) *. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. TOMATO LSI Inc. 32 Unit F HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 6-7. RESET CIRCUIT Setting /RESET to "L" or reset instruction can initialize internal function. When /RESET becomes "L", following procedure is occurred. Display ON / OFF: OFF (DON = 0). Entire display ON / OFF: OFF (normal = 0). ADC select: OFF (normal = 0) Reverse display ON / OFF: OFF (normal = 0). Power control register (VC, VR, VF) = (0, 0, 0) Serial interface internal register data clear LCD power supply bias ratio: bias bit 0 (Refer to LCD bias select of instruction table and duty ratio by DSEL1, DSEL0 pin setting) Duty ratio DSEL1 DSEL0 1/33 1/49 1/55 1/65 0 0 1 1 0 1 0 1 Liquid crystal bias Bias = 0 1/6 1/8 1/8 1/9 Bias = 1 1/5 1/6 1/6 1/7 On-chip oscillator OFF (while /RESET is "L") Power save release Set modify-read: OFF SHL select: OFF (normal = 0). Static indicator mode: OFF. Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0. Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, following procedure is occurred. Set modify-read: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: OFF (normal = 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (1, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release While /RESET is "L", or Reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. /RESET must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by /RESET is essential before used. TOMATO LSI Inc. 33 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7. PROGRAM INSTRUCTION DESCRIPTION Table 7-1. Instruction table X: Don't' care Instruction RS RW DB7 DB6 DB5 DB4 DB3 Read display data DB2 DB1 DB0 Description 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ADC ON / OFF /RESET 0 0 0 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 DON Turn ON / OFF LCD panel When DON = 0: display OFF When DON=1 : display ON Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM0 Set reference voltage mode 0 0 1 0 0 0 0 0 0 1 Set reference voltage mode Set reference voltage register 0 0 X X SV5 SV4 SV3 SV2 SV1 SV0 Set reference voltage register Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB Select SEG output direction. When ADC = 0 : normal direction ADC select 0 0 1 0 1 0 0 0 0 ADC (SEG0 SEG131) When ADC = 1 ; reverse direction (SEG131 SEG 0) Select normal / reverse display When REV = 0 : normal display When REV = 1 : reverse display Select normal / entire display ON When EON = 0 : normal display When EON = 1 : entire display ON Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 Release modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal function Select COM output direction When SHL = 0 : normal direction SHL select 0 0 1 1 0 0 SHL X X X (COM0 COM63) When SHL = 1 : reverse direction (COM63 COM0) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode Set static indicator register 0 0 X X X X X X S1 S0 Set static indicator register Power save - - - - - - - - - - Compound instruction of display OFF and entire display ON NOP 0 0 1 1 1 0 0 0 1 1 Non-Operation command 0 0 1 1 1 1 X X X X Don't use this instruction 0 0 1 0 0 1 X X X X Don't use this instruction Test Instruction_1 Test Instruction_2 TOMATO LSI Inc. 34 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-1. Read display data The 8-bit data from DDRAM specified by the column address and the page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the MPU can continuously read the data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS RW 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data 7-2. Write display data 8-bit data of display data from the MPU can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the MPU can continuously write data to the addressed page. RS RW 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write data Set page address Set page address Set column address Set column address Dummy data read Data write Column = Column + 1 Data read Column = Column + 1 YES Column = Column + 1 Data write continue? Data read continue? YES NO NO Optional status Figure 7-1. Sequence for writing display data TOMATO LSI Inc. 35 Optional status Figure 7-2. Sequence for reading display data HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-3. Read status Indicates the internal status of the HT0324A. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON/OFF /RESET 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG131 ->SEG0), 1: normal direction (SEG0 ->SEG131) -> -> ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF /RESET Indicate the /RESET. 0: chip is active, 1: chip is being reset 7-4. Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 DON DON = 1: display ON DON = 0: display OFF TOMATO LSI Inc. 36 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-5. Initial Display Line Sets the line address of DDRAM to determine the initial display line. The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 7-6. Reference voltage select Consists of 2-byte instruction the first instruction sets reference voltage mode, the second one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. The first instruction: Set reference voltage select mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The second instruction: Set reference voltages select mode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 X X SV5 SV4 SV3 SV2 SV1 SV0 SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage parameter ( ) V0 Contrast 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 0 0 0 0 0 32 (default) : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Min : : : : : : : : : : Max Low : : : : : : : : : : High TOMATO LSI Inc. 37 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Setting reference voltage start First instruction for mode setting Second instruction for register setting Setting reference voltage end Figure 7-3. Sequence for setting the reference voltage 7-7. Set page address Sets the page address of DDRAM from the MPU into the page address register. Any RAM data bit can be accessed when its page address and column address are specified. Along with the column address, the page address defines the address of the DDRAM to write or read display data. Changing the page address doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 TOMATO LSI Inc. 38 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-8. Set column address Sets the column address of DDRAM from the MPU into the column address register. Along with the column address, the column address defines the address of the DDRAM to write or read display data. When the MPU reads or writes display data to or from DDRAM, column addresses are automatically increased. Set column address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131 : 7-9. ADC select Changes the relationship between DDRAM column address and segment driver. The direction of segment driver output pin can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG0 SEG131) ADC = 1: reverse direction (SEG131 SEG0) 7-10. Reverse display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the DDRAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = "1" RAM bit data = "0" 0(Normal) Liquid crystal pixel is illuminated Liquid crystal pixel is not illuminated 1(Reversed) Liquid crystal pixel is not illuminated Liquid crystal pixel is illuminated TOMATO LSI Inc. 39 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-11. Entire display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the DDRAM. At this time, the contents of the DDRAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal display EON = 1: entire display ON 7-12. Select LCD bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias Liquid crystal bias Duty ratio DSEL1 DSEL0 Bias = 0 Bias = 1 1/33 0 0 1/6 1/5 1/49 0 1 1/8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/9 1/7 7-13. Set modify-read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of the MPU when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset modify-read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 7-14. Reset modify-read This instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify-read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 TOMATO LSI Inc. 40 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Set page address Set colum n address(N) Set m odify-read D um m y read D ata read D ata process D ata write NO C hange com plete ? YES R eset m odify-read R eturn colum n address(N) Figure 7-4. Sequence for cursor display 7-15. Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affects the contents of DDRAM. This instruction can not initialize the LCD power supply which is initialized by the /RESET pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 7-16. SHL select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL X X X TOMATO LSI Inc. 41 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 SHL = 0: normal direction (COM0 COM63) SHL = 1: reverse direction (COM63 COM0) X : Don't care 7-17. Power control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Internal power supply circuits status Voltage converter circuit is OFF Voltage converter circuit is ON 0 1 Voltage regulator circuit is OFF Voltage regulator circuit is ON 0 1 Voltage follower circuit is OFF Voltage Follower circuit is ON 0 1 7-18. Regulator resistor select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 6-9. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 (default) 1 0 1 5.5 1 1 0 6.0 1 1 1 6.4 TOMATO LSI Inc. 42 (1 + Rb / Ra ) ratio HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 7-19. Set static indicator state Consists of two bytes instruction. The first byte instruction (set static indicator mode) enables the second byte instruction (set static indicator register) to be valid. The first byte sets the static indicator ON / OFF. When it is ON, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. The first instruction: Set static indicator mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The second instruction: Set static indicator register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 X X X X X X S1 S0 S1 S0 Static indicator output status 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking) 1 1 ON ( always ON) 7-20. NOP Non Operation Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 1 7-21. Test Instruction (Test Instruction_1 & Test Instruction_2) These are the instruction for IC chip testing. Please do not use it. If the Test Instruction is used by accident, it can be cleared by applying "0" signal to the /RESET input pin or the reset instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 X X X X TOMATO LSI Inc. 43 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD 0 0 1 0 0 1 X Ver 0.0 X X X 7-22. Power save (Compound instruction). If the entire display ON / OFF instruction is issued during the display OFF state, HT0324A enters the power save status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one of two modes (sleep and standby mode). When static indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power save mode is released by the display OFF instruction. S tatic in dicator O F F S tatic in dicator O N P o w er sa ve(C om pound instructio n) [D ispla y O F F ] [E ntire d ispla y O N ] SSleep leep m mooddee [O scillator circuit: O F F ] [O scillator circuit: [LC D ply circusup it:Oply FF] O p o w erp sup [LC D o w er [A ll C O M /S E G : V S S ] [A ll C O M /S E G : onsumption ption curren t:< A> [C[C onsum curren t:2 A ] P o w er sa ve O F F (C om pound instruction) [E ntire d ispla y O F F ] [S tatic indica tor O N ] 2 B ytes C om m and RRelea ode elease se sleep m sleep d SStan tanddbbyy dd [O ON] [Oscillator scillator circuit: circuit: [LCDD it:Oply FF] O p o w er [LC p osup w erply circu sup [A MO /SME/S G E: G V S S ]: [Allll C OC [C t: <10A A [Consum onsumption ption curren curren t: > ] P o w er sa ve O F F [E ntire d ispla y O F F ] RRelea y md ob d ye elease se stan d bstan d Figure 7-5. Power save routine -Sleep Mode This stops all operations in the LCD display system, and as long as there are no access from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: a. The oscillator circuit and the LCD power supply circuit are halted. b. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level. -Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. b. The duty drive system liquid crystal drive circuits are halted and the segment and common drive outputs TOMATO LSI Inc. 44 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 a VSS level. When a reset command is performed while in standby mode, the system enters sleep mode. 7-23. Referential instruction setup flow (1) U s e r s y s te m s e tu p b y e x te rn a l p in s SSta tarrtt ooff in initia itializ lizaatio tionn P o w e r O N (V D D -V S S )k e e p in g th e /R E S E T P in = "L " W a itin g fo r s ta b iliz in g th e p o w e r /R E S E T P in = "H " U s e r a p p lic a tio n s e tu p b y in te rn a l in s tr u c tio n s [A D C s e le c t] [S H L s e le c t] [L C D b ia s s e le c t] U s e r L C D p o w e r s e tu p b y in te rn a l in s tru c tio n s [V o lta g e c o n v e rte r O N ] W a itin g fo r > 1 m s U s e r L C D p o w e r s e tu p b y in te rn a l in s tru c tio n s [V o lta g e re g u la to r O N ] W a itin g fo r > 1 m s U s e r L C D p o w e r s e tu p b y in te rn a l in s tru c tio n s [V o lta g e fo llo w e r O N ] U s e r L C D p o w e r s e tu p b y in te rn a l in s tru c tio n s [R e g u la to r re s is to r s e le c t] [R e fe re n c e v o lta g e re g is te r s e t] W a itin g fo r s ta b iliz in g th e L C D p o w e r le v e ls EEnndd ooff in initia itializ lizaattio ionn Figure 7-6. Initializing with the built-in power supply circuits TOMATO LSI Inc. 45 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Referential instruction setup flow (2) U s er sy stem setup by external p ins SStart tart ooff in initializ itializatio ationn P ow er O n(V D D -V S S ) keeping the /R E S E T P in = "L" W aiting for s ta bilizing th e po w er /R E S E T P in = "H " S et pow er save U s er applic atio n setu p by in ternal in struction s [A D C s elect] [S H L s elect] [L C D b ia s s e lec t] U s er LC D pow er se tup by intern al instructions [R egulator re sistor select] [R eference voltage reg ister set] R ele ase pow er save W aiting for s ta bilizing th e LC D pow er levels EEnndd ooff in initializ itializatio ationn Figure 7-7. Initializing without the built -in power supply circuits TOMATO LSI Inc. 46 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Referential Instruction Setup Flow (3) End End of of initialization initialization DDRAM address by instruction [initial display line] [Set page address] [Set column address] Write display ON/OFF by instruction [Display ON/OFF] Turn display ON/OFF by instruction [Display ON/OFF] End End of of data datadisplay display Figure 7-8. Data display TOMATO LSI Inc. 47 Ver 0.0 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Referential instruction setup flow (4) Optional Optional status status Turn display ON/OFF by instruction [Display OFF] User LCD power setup by internal instructions [Voltage regulator OFF] W aiting for > 50ms User LCD power setup by internal instructions [Voltage follower OFF] W aiting for > 1ms User LCD power setup by internal instructions [Voltage converter OFF] W aiting for > 1ms Power Power OFF(VDD OFF(VDD -- VSS) VSS) Figure 7-9. Power off. TOMATO LSI Inc. 48 Ver 0.0 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 8. SPECIFICATIONS 8-1. Absolute maximum ratings Table 8-1. Absolute maximum ratings Parameter Symbol Rating Unit VDD -0.3 to +7.0 VLCD -0.3 to +17.0 Input voltage range VIN -0.3 to VDD +0.3 Operating temperature range TOPR -40 to +85 Supply voltage range V o Storage temperature range TSTR C -55 to +125 Notes: 1. VDD and VLCD are based on VSS = 0V. 2. Voltages V0 >V1>V2>V3>V4>VSS(GND) must always be satisfied.(VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. 8-2. DC Characteristics o Table 8-2. DC characteristics ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Item Symbol Operating voltage(1) Typ Max VDD 2.4 - 5.5 VDD *1 Operating voltage(2) V0 4.5 - 15.0 V0 *2 High VIH 0.8VDD - VDD Low VIL VSS - 0.2VDD High VOH IOH=-0.5mA 0.8VDD - VDD Low VOL IOL=0.5mA VSS - 0.2VDD -1.0 - +1.0 -3.0 - +3.0 - 2.0 3.0 32.7 43.6 54.5 4.09 5.45 6.81 Output voltage V IIL Output leakage current IOZ LCD driver ON resistance RON TOMATO LSI Inc. *3 *4 Input leakage current Oscillator frequency Unit Pin Used Min Input voltage Condition VIN=VDD or VSS VIN=VDD or VSS A *6 k SEGn COMn *7 kHz CL*8 o Internal fOSC External fCL 49 Ta = 25 C V0 = 8V o Ta = 25 C Duty ratio = 1/65 *5 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 o Table 8-2. DC characteristics (continued) ) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Item Symbol Voltage converter input voltage Condition Min. Typ. Max. x2 2.4 - 5.5 x3 2.4 5.3 x4 2.4 4.0 x5 2.4 3.2 95 99 - VCI Voltage converter output voltage VOUT x2/x3/x4/ x5 voltage conversion (no-load) Voltage regulator operating voltage VOUT - 6.0 - 16.0 Voltage follower operating voltage V0 - 4.5 - 15.0 Reference voltage VREF Ta = 25 C o -0.05%/ C 2.04 2.1 2.16 Unit Pin used V VCI % VOUT VOUT V V0*9 o *10 o Table 8-2. DC Characteristics (Continued) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85 C) Dynamic current consumption (1): Built-in circuit OFF (At operating mode) Dynamic current consumption (1) IDD1 VDD = 3.0V, V0 - VSS= 11.0V, 1/65 duty ratio, display pattern OFF - 15 23 A *11 Dynamic Current Consumption (2): Built-in circuit ON (At operating mode) Dynamic current consumption (2) IDD2 VDD = 3.0V, (VCI=VDD,4times boosting) V0 - VSS= 11.0V, 1/65 duty ratio, display pattern OFF, normal power mode VDD = 3.0V, (VCI=VDD, 4 times boosting) V0 - VSS= 11.0V, 1/65 duty ratio, display pattern check, normal power mode - 40 60 A *12 - 150 200 A *12 - - 2.0 A Current consumption during power save mode Sleep mode current TOMATO LSI Inc. IDDS1 50 During sleep HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Standby mode current IDDS2 During standby Ver 0.0 10.0 A Table 8-3. The relationship between oscillation frequency and frame frequency Item fCL fFR On-chip oscillator circuit is used fOSC / 8 fOSC / ( 2 x 8 x 65) External clock is used External Input(fCL) fCL / ( 2 x 65) On-chip oscillator circuit is used Fosc / 9 Fosc / (2 x 9 x 55) External clock is used External input (fCL) fCL / (2 x 55) On-chip oscillator circuit is used fOSC / 10 fOSC / ( 2 x 10 x 49) External clock is used External Input (fCL) fCL / ( 2 x 49) On-chip oscillator circuit is used fOSC / 15 fOSC / (2 x 15 x 33) External clock is used External Input (fCL) fCL / ( 2 x 33) Duty ratio 1/65 1/55 1/49 1/33 *(fOSC: oscillation frequency, fCL: display clock frequency, fFR: LCD AC signal frequency) <* Remark solves> *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU *2. In case of external power supply is applied. *3. /CS1, CS2, RS, DB7 to DB0, E_/RD, RW_/RW, /RESET, MS, C68, PS, INTRS, /HPM, CLS, CL, M, DISP pins. *4. DB0 to DB7, M, FR, FRS, DISP, CL pin. *5. /CS1, CS2, RS, DB7 to DB0, E_/RD, RW_/WR, /RESET, MS, C68, PS, INTRS, /HPM, CLS, CL, M, DISP pins. *6. Applies when then DB7 to DB0, M, FR, FRS, DISP, and CL, pins are in high impedance. *7. Resistance value when 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON = V / 0.1[k] (V :Voltage change when 0.1[mA]is applied in the on status) *8. See table 8-3 for the relationship between oscillation frequency and frame frequency. *9. The Voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *10. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11, 12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built -in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD penal capacity, wiring capacity, etc. TOMATO LSI Inc. 51 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 8-3. AC CHARACTERISTICS a. Read / write characteristics (8080-series MPU) RS tAS80 tAH80 /CS1 (CS2=1) tCY80 tPW80(R), tPW80(W) /RD, /WR 0.9VDD 0.1VDD tDS80 tDH80 DB7 ~ DB0 (Write) tACC80 tOD80 DB7 ~ DB0 (Read) Figure 8-4. Read / write timing chart (8080-series MPU) o Item Signal Address setup time Address hold time RS System cycle time RS Pulse width(/WR) Symbol tAS80 tAH80 (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 0 0 - - ns tCY80 300 - - ns RW-/WR tPW80 ( W ) 60 - - ns Pulse width(/RD) E-/RD 60 - - ns Data setup time Data hold time Read access time Output disable time DB7 to DB0 tPW80 ( R ) tDS80 tDH80 tACC80 tOD80 - - ns - 140 100 ns 40 15 10 CL = 100pF o Item Signal Address setup time Address hold time RS System cycle time RS Pulse width(/WR) Pulse width(/RD) Data setup time Data hold time TOMATO LSI Inc. Symbol tAS80 tAH80 (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 0 0 - - ns tCY80 166 - - ns RW-/WR tPW80 ( W ) 30 - - ns E-/RD DB7 to DB0 tPW80 ( R ) tDS80 tDH80 30 - - ns 30 10 - - ns 52 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD tACC80 tOD80 Read access time Output disable time 5 Ver 0.0 70 50 - ns CL = 100pF b. Read / write characteristics (6800-series MPU) RS tAS68 tAH68 /CS1 (CS2=1) tCY68 tPW68(R), tPW680(W) E 0.9VDD 0.1VDD tDS68 tDH68 DB7 ~ DB0 (Write) tACC68 tOD68 DB7 ~ DB0 (Read) Figure 8-5. Read / write timing chart (6800-series MPU) o Item Signal Address setup time Address hold time RS System cycle time RS Enable pulse width Read Write Data setup time Data hold time Access time Output disable time E-/RD DB7 to DB0 Symbol tAS68 tAH68 (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit 0 0 - - ns tAH68 300 - - ns tPW68 ( R ) tPW68 ( W ) tDS68 tDH68 TACC68 tOD68 120 60 - - - - - ns - 140 100 ns 40 15 10 Remark CL = 100pF o Item Signal Address setup time Address hold time RS System cycle time RS Enable pulse width Read Write Data setup time Data hold time Access time Output disable time TOMATO LSI Inc. E-/RD DB7 to DB0 53 Symbol tAS68 tAH68 (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit 0 0 - - ns tAH68 166 - - ns tPW68 ( R ) tPW68 ( W ) tDS68 tDH68 TACC68 tOD68 70 30 - - - - - ns - 70 50 ns 30 10 10 Remark CL = 100pF HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Serial interface characteristics tCSS tCHS /CS1 (CS2=1) tASS tAHS RS tCYS DB6 (SCLK) 0.9 VDD 0.1VDD tW LS tW HS tDSS tDHS DB7 (SID) Figure 8-6. Serial interface characteristics o Item Signal Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) Address setup time Address hold time Data setup time Data hold time /CS1 set up time /CS1 hold time RS DB7 (SID) /CS1 Symbol tCYC tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 250 100 100 150 150 100 100 150 150 - - ns - - ns - - ns - - ns o Item Signal Serial clock cycle SCLK high pulse width SCLK low pulse width DB6 (SCLK) Address setup time Address hold time Data setup time Data hold time /CS1 set up time /CS1 hold time TOMATO LSI Inc. RS DB7 (SID) /CS1 54 Symbol tCYC tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 200 75 75 50 100 50 50 100 100 - - ns - - ns - - ns - - ns HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 d. Reset input timing tR W /R E S E T tR In te r n a l s ta tu s D u rin g r e s e t R e s e t c o m p le te Figure 8-7. Reset input timing o (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark Item Signal Symbol Reset low pulse width /RESET tRW 1.0 - - s Reset time - tR - - 1.0 s o Item Signal Reset low pulse width /RESET Symbol tRW Reset time - tR (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark 0.5 - - s - - 0.5 s e. Display control output timing tD FR CL (O U T ) FR Figure 8-8. Display control output timing o Item Signal Symbol FR delay time FR tDFR (VDD = 2.4 to 3.6V, Ta = -40 to +85 C) Min. Typ. Max. Unit Remark - 20 80 ns CL = 50 pF o (VDD = 3.6 to 5.5V, Ta = -40 to +85 C) TOMATO LSI Inc. 55 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Item Signal Symbol Min. Typ. Max. Unit Remark FR delay time FR tDFR - 10 40 ns CL = 50 pF 9. REFERENCE APPLICATION 9-1. Microprocessor interface HT0324A Microprocessor /CS1 CS2 RS SID SCLK /RESET Open VDD or VSS VSS /CS1 CS2 RS DB7(SID) DB6(SCLK) /RESET DB5 to DB0 C68 PS Figure 9-1. Serial Interface (PS = "L", C68 = " H or L", E_/RD = "H or L", RW_/WR = "H or L") HT0324A 6800-series Microprocessor /CS1 CS2 RS E RW DB7 to DB0 /RESET VDD VDD /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 /RESET C68 PS Figure 9-2. 6800-series MPU Interface (PS = "H", C68 = " H") HT0324A 8080-series Microprocessor TOMATO LSI Inc. 56 /CS1 CS2 RS /RD /WR DB7 to DB0 /RESET VSS VDD /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 /RESET C68 PS HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 9-3. 8080-series MPU Interface (PS = "H", C68 = " L") 9-2. CONNECTIONS BETWEEN HT0324A AND LCD PANEL a. Single chip configuration (1/65 duty configurations) [ !"#$ @ 64 x 132 PIXELS [ 64 x 132 PIXELS SEG0 ....................SEG131 COMS COM0 SEG131 .....................SEG0 COM32 (Bottom View) HT0324A COM63 COMS Figure 9-4. SHL = 1, ADC = 0 COM31 HT0324A COMS COM63 (Top View) COM0 COMS COM32 SEG0 ......................SEG131 !"#$ @ 64 x 132 PIXELS Figure 9-6. SHL = 0, ADC = 0 TOMATO LSI Inc. COM32 HT0324A COM31 [ !"#$ @ 57 COM63 COMS COMS COM0 (Top View) COM31 Figure 9-5. SHL = 1, ADC = 1 COMS COM63 COM31 HT0324A (Bottom View) COM0 COM32 COMS SEG131 ......................SEG0 [ !"#$ @ 64 x 132 PIXELS Figure 9-7. SHL = 0, ADC = 1 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 b. Single chip configuration (1/55 duty configurations) [ !"#$ @ 54 x 132 PIXELS [ 54 x 132 PIXELS SEG0 ....................SEG131 COMS COM0 SEG131 .....................SEG0 COM37 (Bottom View) HT0324A COM63 COMS Figure 9-8. SHL = 1, ADC = 0 COM26 HT0324A COMS COM63 (Top View) COM0 COMS COM37 SEG0 ......................SEG131 !"#$ @ 54 x 132 PIXELS Figure 9-10. SHL = 0, ADC = 0 TOMATO LSI Inc. COM37 HT0324A COM26 [ !"#$ @ 58 COM63 COMS COMS COM0 (Top View) COM26 Figure 9-9. SHL = 1, ADC = 1 COMS COM63 COM26 HT0324A (Bottom View) COM0 COM37 COMS SEG131 ......................SEG0 [ !"#$ @ 54 x 132 PIXELS Figure 9-11. SHL = 0, ADC = 1 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 c. Single chip configuration (1/49 duty configurations) [ !"#$ @ 48 x 132 PIXELS [ 48 x 132 PIXELS SEG0 ....................SEG131 COMS COM0 SEG131 .....................SEG0 COM40 (Bottom View) HT0324A COM63 COMS Figure 9-12. SHL = 1, ADC = 0 COM23 HT0324A COMS COM63 (Top View) COM0 COMS COM40 SEG0 ......................SEG131 !"#$ @ 48 x 132 PIXELS Figure 9-14. SHL = 0, ADC = 0 TOMATO LSI Inc. COM40 HT0324A COM23 [ !"#$ @ 59 COM63 COMS COMS COM0 (Top View) COM23 Figure 9-13. SHL = 1, ADC = 1 COMS COM63 COM23 HT0324A (Bottom View) COM0 COM40 COMS SEG131 ......................SEG0 [ !"#$ @ 48 x 132 PIXELS Figure 9-15. SHL = 0, ADC = 1 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 d. Single chip configuration (1/33 duty configurations) [ !"#$ @ 32 x 132 PIXELS [ 32 x 132 PIXELS SEG131 .....................SEG0 SEG0 ....................SEG131 COMS COM0 COM48 (Bottom View) HT0324A COM63 COMS Figure 9-16. SHL = 1, ADC = 0 COM15 HT0324A COMS COM63 (Top View) COM0 COMS COM48 SEG0 ......................SEG131 !"#$ @ 32 x 132 PIXELS Figure 9-18. SHL = 0, ADC = 0 TOMATO LSI Inc. COM48 HT0324A COM15 [ !"#$ @ 60 COM63 COMS COMS COM0 (Top View) COM15 Figure 9-17. SHL = 1, ADC = 1 COMS COM63 COM15 HT0324A (Bottom View) COM0 COM48 COMS SEG131 ......................SEG0 [ !"#$ @ 32 x 132 PIXELS Figure 9-19. SHL = 0, ADC = 1 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 e. Multiple chip configuration - 65COM (64COM + 1COMS) x 264SEG (132SEG x 2) [ ! " # $ @ 6 4 x 2 6 4 P IX E L S ! " # % & S E G 131 ... ... ... ... ... S E G 0 C O M 32 C O M 63 COMS S E G 131 ... ... ... ... ... S E G 0 COMS COM0 H T0324A ( T o p V ie w ) (M a s te r) ' C O M 32 C O M 63 COMS C O M 31 H T0324A COMS COM0 ( T o p V ie w ) ( S la v e ) C O M 31 Figure 9-20. SHL = 1, ADC = 1 Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 C O M 31 H T0324A COMS C O M 63 C O M 31 ( T o p V ie w ) ( S la v e ) ( T o p V ie w ) (M a s te r) COM0 C O M 32 COMS SEG 0 ... ... ... ... ... SEG 131 [ H T0324A COM0 C O M 32 COMS SEG 0 ... ... ... ... ... SEG 131 ! " # $ @ 6 4 x 2 6 4 P IX E L S ! " # % & ' Figure 9-21. SHL = 0, ADC = 0 TOMATO LSI Inc. 61 COMS C O M 63 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 - 130COM (128COM + 2COMS) x 132SEG C O M 31 COM0 COMS H T0324A COMS C O M 63 (T o p V ie w ) (M a s te r) C O M 32 S E G 0 ... .... ... ...... ... ... S E G 1 3 1 [ ! " # $ @ 1 2 8 x 1 3 2 P IX E L S ! " # % & ' S E G 1 3 1 ... .... ... ... ... ... S E G 0 C O M 32 H T0324A C O M 63 COMS (T o p V ie w ) (S la v e ) COMS COM0 C O M 31 Figure 9-21. 130COM (128COM + 2COMS) x 132SEG Connect the following pins of two chips each other - Display clock pins: CL, M - Display control pin: DISP - LCD power pins: V0, V1, V2, V3, V4 TOMATO LSI Inc. 62 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Common / Segment output direction select - Master chip: SHL = 0, ADC = 0 - Slave chip: SHL = 1, ADC = 1 9-3. TCP Pin lay out (sample) FR FR S COMS C O M 63 C O M 62 : : : M CL D IS P /C S 1 CS2 /R E S E T RS R W _ /W R E _ /R D DB0 DB1 DB2 DB3 DB4 DB5 D B 6 , (S C L ) D B 7 , ( S I) DSEL0 DSEL1 VDD VCI VSS VO UT C4+ C3+ C1C1+ C2+ C2VEXT REF V1 V2 V3 V4 V0 VR MS CLS C68 PS /H P M IN T R S C O M 47 C O M 46 C O M 45 : : : H T0324A (T o p v ie w ) C O M 35 C O M 34 C O M 33 C O M 32 S EG 131 S EG 130 S EG 129 S EG 128 : : S EG 65 S EG 64 S EG 63 S EG 62 : : SEG3 SEG2 SEG1 SEG0 COMS COM0 COM1 COM2 COM3 : : C O M 14 C O M 15 C O M 16 : : C O M 28 C O M 29 C O M 30 C O M 31 TOMATO LSI Inc. 63 HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ver 0.0 Figure 9-22. TCP pin layout 9-4. Application circuit for serial -. Package type: TCP -. Device mode: Master mode, Internal OSC, normal mode, 4-times boost-up, internal resistor MPU MPU /RESET RS MPU MPU DB6, (SCL) DB7, (SI) VDD VDD VSS VSS VOUT C3+ C1C1+ C2+ C2V1 V2 V3 V4 V0 TCP in side TCP out side [18 PINS] TOMATO LSI Inc. 64 HT0324A /CS1 (Top view) MPU FRS FR NC0 NC1 M CL DISP VSS[2] /CS1 CS2 VDD /RESET RS VSS RW _/W R E_/RD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 (SCLK) DB7 (SID) VSS VDD DSEL0 DSEL1 VSS VDD[5] VCI[3] VSS[5] VOUT[4] C4+[2] C3+[2] C1-[2] C1+[2] C2+[2] C2-[2] VDD VEXT[2] REF VSS V1[2] V2[2] V3[2] V4[2] V0[3] VR[3] VSS[2] VDD MS CLS VSS C68 PS VDD /HPM VSS INTRS VDD HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Figure 9-23. HT0324A Application circuit for serial TOMATO LSI Inc. 65 Ver 0.0