(5.0V SPECIFICATION)
65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD
August. 2000
VER 0.0
TOMATO LSI Inc.
HT0324A
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
2
HT0324A Sp ec if ic atio n re vis i on hist ory
Version Content Date
0.0 1. Operating voltage range : VDD = 2.4V ~ 5.5V August. 2000
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
3
CONTENTS
1. INTRODUCTION -----------------------------------------------------------------------------------------------------------
2. FEATURES ---------------------------------------------------------------------------------------------------------------
3. BLOCK DIAGRAM -----------------------------------------------------------------------------------------------------
4. PAD CONFIGUR AT ION ------------------------------------------------------------------------------------------------
4-1. Pad center coordinates -------------------------------------------------------------------------------------------
5. PIN DESCRIPTION ----------------------------------------------------------------------------------------------------
6. FUNCTIONAL DESCRIPTION -----------------------------------------------------------------------------------
6-1. Micro processor interface ----------------------------------------------------------------------------------------
a. Chip select input
b. Interface
c. Paralle l inter face (P S = "H")
d. Serial interface (PS = "L")
e. Busy flag
f. Data accessing
6-2. Display data RAM (DDRAM) --------------------------------------------------------------------------------------
a. Display data RAM
b. Page address circuit
c. Column address circuit
d. Line address circuit
e. Segment control circuit
6-3. LCD display circuit ----------------------------------------------------------------------------------------------------
a. Oscillator
b. Display timing generator circuit
c. Common output control circuit
6-4. LCD driver circuit ---------------------------------------------------------------------------------------------------
6-5. Power supply circuits -------------------------------------------------------------------------------------------
a. Voltage converter circuits
b. Voltage regulator circuits
c. Voltage follower circuits
d. High power mode
6-6. Reference circuit examples --------------------------------------------------------------------------------------
6-7. Reset circuit --------------------------------------------------------------------------------------------------------
7. PROGRA M INSTRUCTION ----------------------------------------------------------------------------------------
7-1. Read display data -------------------------------------------------------------------------------------------------
7-2. Write display data ------------------------------------------------------------------------------------------------
7-3. Read status ----------------------------------------------------------------- ---------------------------------------
7-4. Display ON / OFF -----------------------------------------------------------------------------------------------------
7-5. Ini tial display line -------------------------------------------------------------------------------------------------
7-6. Reference voltage select --------------------------------------------------------------------------------------
7-7. Set page address ------------------------------------------------------------------------------------------------
7-8. Set column address -----------------------------------------------------------------------------------------------
7-9. ADC select ---------------------------------------------------------------------------------------------------------
7-10. Reverse display ON / OFF-----------------------------------------------------------------------------------------
7-11. Entire display ON / OFF--------------------------------------------------------------------------------------------
7-12. Select LCD bias --------------------------------------------------------------------------------------------------
7-13. Set modify-read ---------------------------------------------------------------------------------------------------
7-14. Reset modify-read -----------------------------------------------------------------------------------------------
7-15. Reset ----------------------------------------------------------------------------------------------------------------
7-16. SHL select ----------------------------------------------------------------------------------------------------------
5
5
7
8
9
12
16
16
19
22
23
24
31
32
34
35
35
36
36
37
37
38
39
39
39
40
40
40
40
41
41
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
4
7-17. Power control ---------------------------------------------------------------------------------------------------------
7-18. Regulator resistor select ------------------------------------------------------------------------------------------
7-19. Set static indicator state -------------------------------------------------------------------------------------------
7-20. NOP -----------------------------------------------------------------------------------------------------------------------
7-21. Test instruction ---------------------------------------------------------------------------------------------------------
7-22. Power save (Compound instruction) ---------------------------------------------------------------------------
7-23. Referential instruction set flow-----------------------------------------------------------------------------------
8. SPECIFIC ATIONS --------------------------------------------------------------------------------------------------------
8-1. Absolute maximum ratings ---------------------------------------------------------------------------------------
8-2. DC characteristics ----------------------------------------------------------------------------------------------------
8-3. AC characteristics --------------------------------------------------------------------------------------------------
a. Read / write characteristics (8080-series MPU)
b. Read / write characteristics (6800-series MPU)
c. Serial interface characteristics
d. Reset input timing
e. Display control output timing
9. REFERENCE APPLICATION ---------------------------------------------------------------------------------------------
9-1. MPU interface -------------------------------------------------------------------------------------------------------
9-2. Connections between HT0324A and LCD panel -----------------------------------------------------------------
9-3. TCP pin lay out (sample) -----------------------------------------------------------------------------------------
9-4. Application circuit for serial --------------------------------------------------------------------------------------
42
42
43
43
43
44
45
49
49
49
50
56
56
57
63
64
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
5
1. INTRODUCTION
The HT 0324A is a driver and contro ller LSI f or graph ic do t-m atrix liqu id cr ystal dis pla y s ystem s. It contai ns
65 common and 132 segment driver circuits. This chip is connected directly to a microprocessor (MPU),
accepts serial or 8-bit parallel display data and stores in an on-chip Display Data RAM (DDRAM) of 65 x
132 bits. It provides a high-flexible display section due to one to one correspondences between on-chip
DDRAM bits and LCD panel pixels. And it performs DDRAM read / write operation with no externally
operating clock to minimize power consumption. In addition, because it contains power supply circuits
necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver output circuits
-. 65 common outputs / 132 segment outputs
On-chip display data RAM (DDRAM)
-. Capacity: 65 x 132=8,580 bits
-. RAM bit data “1”: a dot of display is illuminated.
-. RAM bit data “0”: a dot of display is not illuminated.
Multi-chip operation
-. Master and slave mode available
Applicable duty-ratios
Duty ratio Applicable LCD bias Maximum display area
1/65 1/9 or 1/7 65 x 132
1/55 1/8 or 1/6 55 x 132
1/49 1/8 or 1/6 49 x 132
1/33 1/6 or 1/5 33 x 132
Microprocessor (MPU) interface
-. High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series
-. Serial inter-face (only write operation) available
Various Function set
-. Display ON/OFF, set initial display line, set page address, set column address, read status, write /
read display data, select segment driver output, reverse display ON/OFF, entire display ON/OFF,
select LCD bias, set/reset modify-read, select common driver output, control display power circuit,
select internal regulator resistor ratio for V0 voltage regulation, electronic volume, set static
indicator state.
-. H/W and S/W reset available
-. Static drive circuit equipped internally for indicators with 4 flashing modes
Built-in analog circuits
-. On-chip Oscillator circuit for display clock(external clock can also be used)
-. High performance voltage converter
(with booster ratios of x2, x3, x4 and x5, where the step-up reference voltage can be used
externally)
-. High accuracy voltage regulator(temperature coefficient: -0.05%/
or external input)
-. Electronic contrast control function (64 steps)
-. Vref = 2.1V ± 3% (V0 voltage adjustment voltage)
-. High performance voltage follower
(V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity)
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
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Operating voltage range
-. Supply voltage (VDD): 2.4 to 5.5V
-. LCD driving voltage (VLCD = V0 -VSS): 4.5 to 15.0V
Low power consumption
-. Operating po wer : 40µA Typ, (VDD = 3V, x4 boosting[VCI is VDD], V0=11V, internal power supply
ON, display OFF and normal mode is selected)
-. Standby power : 10µA Max. (during power save[standby] mode)
Operating Temperatures
-. Wide range of operating temperatures : -40 to 85
CMOS Process
Package type
-. Gold bumped chip and TCP available
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
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3. BLOCK DIAGRAM
Figure 3-1. block diagra
OSCILLATOR
MS
CL
M
FRS
FR
DISP
DSEL0
DSEL1
CLS
COMS
COM0
COM31
SEG0
SEG1
SEG2
SEG129
SEG130
SEG131
COM32
COM63
COMS
/CS1
CS2
RS
E_/RD
RW_/WR
PS
/RESET
C68
(SID)DB7
(SCLK)DB6
DB5
DB4
DB3
DB2
DB1
DB0
MPU INTERFACE CIRCUIT(PARALLEL & SERIAL)
VDD
V0
V1
V2
V3
V4
VSS
/HPM
V0
VR
INTRS
REF
VEXT
VOUT
C1-
C1+
C2-
C2+
C3+
C4+
VCI
I/O
BUFFER
I/O
BUFFER
PAGE
ADDRESS
CIRCUIT
PAGE
ADDRESS
CIRCUIT
DISPLAY DATA RAM
65 x 132 = 8,580 BITS
DISPLAY DATA RAM
65 x 132 = 8,580 BITS LINE
ADDRESS
CIRCUIT
LINE
ADDRESS
CIRCUIT
COLUM N ADDR ESS
CIRCUIT
COLUM N ADDR ESS
CIRCUIT
STATUS REGISTER
BUS HO LDER
INSTRUCTION REGISTER
INSTRUCTION DECODER
DISPLAY DATA
CON TROL CIRCUIT COMMON OUTPUT
CON TROL CIRCUIT
132 SEGM E NT
DRIVER
CIRCUITS
33 COMMON
DRIVER
CIRCUITS
33 COMMON
DRIVER
CIRCUITS
VOLTAGE
CONVERTER
VOLTAGE
FOLLOWER
VOLTAGE
REGULATOR
DISPLAY
TIMING
GENERATOR
CIRCUIT
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
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4. PAD CONFIGURATION
Figure 4-1. Chip configuration
Table 4-1. Pad dimensions Size
ITEM Pad No. XY
Unit
Chip size
(Include scr ibe lan e) - 9540 2310
2~93, 95~115 70
118~143, 146~291, 294~319 60
Pad pitch 1~2, 93~95, 115~116, 117~118 ,
143~144, 145~146, 291~292,
293~294, 319~320 80
2~93, 95~115 50 102
118~143, 294~319 102 40
146~291 40 102
1, 94, 116, 145, 292 55 102
Bumped pad size
(Bottom)
117, 144, 293, 320 102 55
Bumped pad height All pad 18 ±3 (Typ.)
µm
Figure 4-2. COG align key Figure 4-3. ILB align key
30µm 30µm 30µm
30µm 30µm 30µm
30µm 30µm 30µm
30µm 60µm
42µm 108µm
42µm 108µm
108µm 42µm
108µm 42µm
(-3920, -305)
(3920, 425) (-3960, 415)
(3960, -305)
(0,0)
Y
X
SL09SL0211
F111
1
320
293
292 145
117
144
116
HT0324A
TOP VIEW
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
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4-1. PAD CENTER COORDINATES
Table 4-2. Pad center coordinates [Unit: um]
PAD
No. PAD
name XY
PAD
No. PAD
name XY
PAD
No. PAD
name XY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DUMMY
FRS
FR
NC0
NC1
M
CL
DISP
VSS
VSS
/CS1
CS2
VDD
/RESET
RS
VSS
RW _/WR
E_/RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VSS
VDD
DSEL0
DSEL1
VSS
VDD
VDD
VDD
VDD
VDD
VCI
VCI
VCI
VSS
VSS
VSS
VSS
VSS
VOUT
VOUT
VOUT
VOUT
C4+
-4045
-3965
-3895
-3825
-3755
-3685
-3615
-3545
-3475
-3405
-3335
-3265
-3195
-3125
-3055
-2985
-2915
-2845
-2775
-2705
-2635
-2565
-2495
-2425
-2355
-2285
-2215
-2145
-2075
-2005
-1935
-1865
-1795
-1725
-1655
-1585
-1515
-1445
-1375
-1305
-1235
-1165
-1095
-1025
-955
-885
-815
-745
-675
-605
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
C4+
C3+
C3+
C1-
C1-
C1+
C1+
C2+
C2+
C2-
C2-
VDD
VEXT
VEXT
REF
VSS
V1
V1
V2
V2
V3
V3
V4
V4
V0
V0
V0
VR
VR
VR
VSS
VSS
VDD
MS
CLS
VSS
C68
PS
VDD
/HPM
VSS
INTRS
VDD
DUMMY
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
-535
-465
-395
-325
-255
-185
-115
-45
25
95
165
235
305
375
445
515
585
655
725
795
865
935
1005
1075
1145
1215
1285
1355
1425
1495
1565
1635
1705
1775
1845
1915
1985
2055
2125
2195
2265
2335
2405
2485
2565
2635
2705
2775
2845
2915
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
TEST6
TEST7
TEST8
TEST9
TEST10
TEST11
TEST12
TEST13
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
DUMMY
DUMMY
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
DUMMY
DUMMY
COM5
COM4
COM3
COM2
COM1
2985
3055
3125
3195
3265
3335
3405
3475
3545
3615
3685
3755
3825
3895
3965
4045
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4606
4430
4350
4290
4230
4170
4110
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-991
-860
-780
-720
-660
-600
-540
-480
-420
-360
-300
-240
-180
-120
-60
0
60
120
180
240
300
360
420
480
540
600
660
720
800
991
991
991
991
991
991
* 1. NC0, NC1: No Connection
2. Main VSS pad (PAD No. 41,42,43,44 and 45) have to be connected
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
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Table 4-2. Pad center coordinates (continued) [Unit: um]
PAD
No. Pad
name XY
PAD
No. Pad
name XY
PAD
No. PAD
name XY
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
COM0
COMS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
4050
3990
3930
3870
3810
3750
3690
3630
3570
3510
3450
3390
3330
3270
3210
3150
3090
3030
2970
2910
2850
2790
2730
2670
2610
2550
2490
2430
2370
2310
2250
2190
2130
2070
2010
1950
1890
1830
1770
1710
1650
1590
1530
1470
1410
1350
1290
1230
1170
1110
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
1050
990
930
870
810
750
690
630
570
510
450
390
330
270
210
150
90
30
-30
-90
-150
-210
-270
-330
-390
-450
-510
-570
-630
-690
-750
-810
-870
-930
-990
-1050
-1110
-1170
-1230
-1290
-1350
-1410
-1470
-1530
-1590
-1650
-1710
-1770
-1830
-1890
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
COM32
COM33
COM34
COM35
COM36
COM37
COM38
DUMMY
DUMMY
COM39
COM40
COM41
COM42
COM43
COM44
COM45
-1950
-2010
-2070
-2130
-2190
-2250
-2310
-2370
-2430
-2490
-2550
-2610
-2670
-2730
-2790
-2850
-2910
-2970
-3030
-3090
-3150
-3210
-3270
-3330
-3390
-3450
-3510
-3570
-3630
-3690
-3750
-3810
-3870
-3930
-3990
-4050
-4110
-4170
-4230
-4290
-4350
-4430
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
991
800
720
660
600
540
480
420
360
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
11
Table 4-2. Pad center coordinates (continued) [Unit: um]
PAD
No. Pad
name XY
PAD
No. Pad
name XY
PAD
No. PAD
name XY
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
DUMMY
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
-4606
300
240
180
120
60
0
-60
-120
-180
-240
-300
-360
-420
-480
-540
-600
-660
-720
-780
-860
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5. PIN DESCRIPTION
Table 5-1. Pin description
Power supply
Name I/O Description
VDD Shared with the MPU power supply terminal VCC.
VSS
Power
supply This is a 0V terminal connected to the system GND.
Main VSS pad (PAD No. 41,42,43,44 and 45) have to be connected
The voltage is determined by the LCD pixel impedance-converted for application by
an operational amplifier. Voltage have the following relationship:
V0 >V1>V2>V3>V4>VSS(GND)
When the on-chip power circuit is active, these voltages are generated
according to the state of LCD bias, as shown in the table below.
LCD Bias V1 V2 V3 V4
1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0
1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0
1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
V0
V1
V2
V3
V4
I/O
LCD driver power supply
Name I/O Description
C1+ Capacitor1+ positive connection pin for the voltage converter
C1- Capacitor1- neg ativ e conn ect ion pin for volt age conv ert er
C2+ Capacitor2+ positive connect ion pin for voltage converter
C2- Capacitor2- neg ativ e conn ect ion pin for volt age conv ert er
C3+ Capacitor3+ positive connection pin for voltage converter
C4+
O
Capacitor4+ positive connection pin for voltage converter
VOUT I/O Voltage converter input / output pin
Connect this pin to VSS through capacitor.
VR I V0 voltage adjustment pin. It is valid only when using external resistors.(INTRS=”L”)
VCI I This is the reference voltage for the voltage converter circuit for the LCD drive.
Whether internal voltage converter use or not use, this pin should be fixed.
The voltage should have the following range: 2.4V ≤ VCI ≤ 5.5V
VEXT I This is the externally input reference voltage (VREF) for the internal voltage regulator.
It is valid only when external VREF is used (REF = “L”).
When using internal VREF, this pin is Open
REF I Select the external VREF voltage via VEXT pin
-REF = “L”: using the external VREF
-REF = “H”: using the internal VREF
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Table 5-1. Pin description (continued)
System control
Name I/O Description
Master/slave mode select input. Master makes some signals for display, and slave
receives them. This for display synchronization.
MS =”H”: Master mode
MS =”L”: Slave mode
MS CLS OSC
Circuit Power
Supply CL M FRS,
FR DISP
H Enable Enable Output Output Output Output
HL Disable Enable Input Output Output Output
L - Disable Disable Input Input Output Input
MS I
CLS I Built-in oscillator circuit enables / disable select pin.
CLS = “H”: Enable
CLS = ”L”: Disable (external display clock input to CL pin)
CL I/O Display clock input / output pin. When HT0324A is used in master/slave mode(multi-chip),
the CL pin must be connected to each other.
M I/O
LCD AC signal input / output pin.
When HT0324A is used in master/slave mode(multi-chip), the M pin must be connected to
each other.
MS = “H”: Output
MS = “L”: Input
FRS O Static driver segment output. This pin is used together with the FR pin.
FR O Static driver common output. This pin is used together with the FRS pin.
DISP I/O
LCD display blanking control input/output. When HT0324A is used in master/slave mode
(multi-chip), the DISP pin must be connected to each other.
MS = “H”: Output
MS = “L”: Input
INTRS I
Internal resistor selects pin.
This pin selects the resistor for adjusting V0 voltage level and is available only in master
mode.
INTRS = “H”: using built-in resistors.
INTRS = “L”: not using built-in resistors.
V0 voltage is controlled by VR pin with external resistive divider.
/HPM I
Power control pin of the power supply circuits for LCD driver
- /HPM = “H”: normal mode
- /HPM = “L”: high power mode
This pin is valid only in master operation.
The LCD driver duty ratio depends on the following table.
DSEL1 DSEL0 DUTY RATIO
L L 1/33
L H 1/49
H L 1/55
DSEL1
DSEL0 I
H H 1/65
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Table 5-1. Pin description (continued)
MPU interface
Name I/O Description
/RESET I Hardware reset input pin.
When /RESET is “L”, initialization is exec uted.
Parallel/Serial select input pin.
PS Operating
mode Chip
select Data/
Instruction Data I/O Read/
Write Serial
H Parallel /CS1,
CS2 RS DB7 to
DB0 E_/RD,
RW_/WR -
LSerial
/CS1,
CS2 RS DB7
(SID) Write
only DB6
(SCLK)
PS I
When PS= “L”, DB5 to DB0 are high impedance.
E_/RD and RW_/WR are fixed to either “H” or “L”.
With serial data input, RAM display data reading is not supported.
C68 I This pin is the MPU interface switch terminal.
C68 = “H”: 6800 series MPU interface
C68 = “L”: 8080 series MPU interface
/CS1
CS2 IChip select input pin.
Data input/output is enables only when /CS1 is low and CS2 is high.
When chip select is non-active, DB7 to DB0 will be high impedance.
RS I Register select input pin.
RS = “H”: The data on DB7 to DB0 is used the display data.
RS = “L”: The data on DB7 to DB0 is used the control data.
RW_/WR I
When interfacing to a 6800-series MPU, read/write is enabled at;
RW_/WR = “H”: read
RW_/WR = “L”: write
When interfacing to an 8080-series MPU, RW_/WR is enabled at low.
The signals on the data bus are latched at the rising edge of the RW_/WR signal.
E_/RD I
When interfacing to a 6800-series MPU: Active High.
This pin is used as an enable clock input pin of the 6800-series MPU.
When interfacing to a 8080-series MPU: Active Low.
This pin is connected to the RD signal of the 8080-series MPU. While this signal is Low,
HT0324A data bus output is enab led .
DB7
to
DB0 I/O
8-bit bi-direction al data bus .
It is connected to the standard 8-bit microprocessor data bus.
In case of serial interface,(PS = ”L”)
DB7: Serial input data(SID)
DB6: Serial input clock(SCLK)
DB5 to DB0 : High impedance
When chip select is not active, DB7 to DB0 will be high impedance.
NC1
NC0 I/O These are set to Open.
TEST20
to
TEST0 I/O These are pins for IC chip testing.
These are set to Open.
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Table 5-1. Pin description (continued)
LCD driver output
Name I/O Description
LCD driver output for segment. The display data and the FR signal control the output
voltage of segment driver.
Segment output voltage
Display data FR Normal display Reverse disp lay
H H V0 V2
H L VSS V3
L H V2 V0
L L V3 VSS
Power save mode VSS
SEG0
to
SEG131 O
LCD driver output for common. The internal scanning data and M signal control the
output voltage of common driver.
Scan data FR Common output voltage
H H VSS
HL V0
LH V1
LL V4
Power save mode VSS
COM0
to
COM63 O
COMS O Common signal output for the icons. The output signals of two pins are the same.
When this signal is not used, should be left open. In multi-chip(master/slave) mode, all
COMS pin on both master and slave units are the same signal.
Note:
-. DUMMY, TEST0 ~ TEST20, NC0, NC1: The pins should be opened(floated).
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6. FUNCTIO NAL DESCRIPTION
6-1. MICROPROCESSOR INTERFACE
a. Chip select input
There are /CS1 and CS2 pins for chip selection. The HT0324A can interface with an MPU only when
/CS1 is “ L” an d C S2 is “ H”. When these pins are set to a n y ot her c ombinati on, RS , E_/RD, and RW_/WR
inputs are disabled and DB7 to DB0 are to be high impedance. And, in case of serial interface, the
internal shift register and the counter are reset.
b. Interface
HT0324A has three types of interface with an MPU, which are one ser ial an d two par alle l in terfac es. T his
parallel or serial interface is determined by PS pin as shown in table 6-1.
Table 6-1. Parallel / Serial interface mode
PS Type /CS1 CS2 C68 Interface mode
H 6800-series MPU mode
H Parallel /CS1 CS2 L 8080-series MPU mode
L Serial /CS1 CS2 X* Serial MPU mode
∗ X : Don't care
c. Parallel interface (PS = "H")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by C68 as
shown in table 6-2. The type of data transfer is determined by signals at RS, E_/RD, and RW_/WR as
shown in table 6-3.
Table 6-2. Microprocessor selection for parallel interface
C68 /CS1 CS2 RS E_/RD RW_/WR DB7 to DB0 MPU
H /CS1 CS2 RS E RW DB7 to DB0 6800-series
L /CS1 CS2 RS /RD /WR DB7 to DB0 8080-series
Table 6-3. Parallel data transfer
Common 6800-series 8080-series
RS E_/RD
(E) RW_/WR
(RW) E_/RD
(/RD) RW_/WR
(/WR)
Description
H H H L H Display data read out
H H L H L Display data write
L H H L H Register status read
L H L H L Writes to internal register(instruction)
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d. Serial interface (PS = "L")
W hen the HT0324A is active and s erial interfac e has been sel ected, the ser ial data (DB7) and the seri al
clock (DB6) inputs ar e enabled. And HT 0324A is n ot active, the inter nal 8-bi t shift register a nd the 3-bit
counter are reset. T he serial data can be read on the rising edge of the ser ial clock going into DB6 and
process ed as 8-b it parallel data on t he eighth ser ial clock . The serial d ata input is displa y data when RS
is high and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the
external noise caused by the line length, the operation check on the actual machine is recommended.
Figure 6-1. Serial interface timing
e. Busy flag
The busy flag indicates whether the HT0324A is operating or not. When DB7 is “H” in read status
operation, this device is in busy status and will accept only read status instruction. If the cycle time is
correct, the MPU needs not to check this flag before each instruction, which improves the MPU
performance.
D B 7 DB6 D B 5 DB 4 D B 3 D B 2 DB1 D B 0 DB7 D B 6
/CS1
CS2
SID
(DB7)
SCLK
(DB6)
RS
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f. Data accessing
The HT0324A uses bus holder and internal data bus for data read and data write with the MPU.
When writing data from the MPU to on-chip RAM, the data is automatically transferred from the bus
holder to the on-chip R AM as sho wn in f igure 6- 2. When the MPU reads data f rom on- chip RAM, t he firs t
data read c ycle stor es the data in th e bus ho lder (d um m y read) and the MPU reads t his st ored d ata fr om
bus holder for the next data read cycle as shown in figure 6-3. This means the data of the specified
address cannot be output with the read display data instruction right after the address sets, but can be
output at the sec ond r ead of data. Theref or e, a dum my read c ycle must be ins er ted bet ween eac h pair of
address sets when a sequence of address sets is executed.
Figure 6-2. Write timing
Figure 6-3. Read timing
MPU signalsInternal signals
RS
/WR
DB7
to DB0
/WR
Bus
Holder
Column
Address
N D (N ) D (N+1 ) D ( N + 2 ) D ( N + 3 ) D(N+ 4)
N D (N ) D (N+1 ) D ( N + 2 ) D ( N + 3 ) D(N+ 4)
N N + 1 N + 2 N + 3 N+4
MPU signalsInternal signals
RS
/WR
/RD
DB7
to DB0
/WR
/RD
Bus
Holder
Column
Address
N Dummy D(N) D(N+1) D(N+2) D(N+3)
N D(N) D(N+1) D(N+2) D(N+3) D(N+4)
N N+1 N+2 N+3 N+4 N+5
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6-2. DISPLAY DATA RAM (DDRAM)
a. DDRAM
The DDRAM stores pixel data f or the LC D. It has 65-row ( 8 page x 8 bit + 1) by 132-col um n addressab le
array. Each pixel can be selected by specifying the page and the column address. The 65 rows are
divided int o 8 pages of 8 lines and the 9th page with a sin gle line (DB 0 onl y). Data is read f rom or written
to the 8 lines of each page directl y thr ough DB7 to DB0. T he display data of DB0 to DB7 from the MPU
correspond to the LCD common direction as shown in Figure 6-4.
The MPU can read f r om and writ e to D D R AM t hr oug h th e I/O buffer, which is ind epe nde nt o per at io n f r om
signal rea ding for the LCD driver. This independent operat ion makes it possible that the MPU writes the
data into the DDRAM at the same time as data is being displayed without causing the LCD flicker.
Figure 6-4. RAM-to-LCD data transfer
b. Page address circuit
This circuit is for providing a page address to DDRAM shown in figure 6-6. The 4-bit page address
register c ha nge d by only the “Set page” ins truc t ion. P age add ress 8 ( DB3 , D B2, DB 1, DB 0 = 1, 0, 0 , 0) is
a special RAM area for the icons and display data DB0 is only valid.
When Page Address is above 8, it is impossible to access to on-chip RAM.
c. Column address circuit
Column addr es s c irc ui t has a 8- b it pr es et c ou nter th at provides co lumn addr es s to the DDR AM as s ho wn
in figure 6-6. When the “Set column address MSB / LSB” instruction is issued, 8-bit [Y7:Y0] is updated.
And this address is increased by +1 each display data Read/Write instruction. This allows that the MPU
display data can be accessed continuously. The increment of the column address stops with 83H. And
the counter is not increased and locked if the address is specified over 84H. It is unlocked if a column
address is set again by “Set column address MSB / LSB” instruction. The column address counter is
independent of the page address register.
The ADC select ins truc tio n m ak es it poss ib le t o c on vert t he r e lat io nship between the column addr es s and
the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing the ADC
select instruction. Refer to the figure 6-5.
Display data RAM LCD display
011……0
100……1
111……0
001……1
110……0
……
……
……
……
……
DB0
DB1
DB2
DB3
DB4
COM0
COM1
COM2
COM3
COM4
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Figure 6-5. The relationship between the column address and the segment outputs
d. Line address circuit
This circuit assigns DDRAM a line address corresponding to the first line (COM0) of the display. Using
the display start line address set command, what is normally the top line of the display can be specified.
By setting the line address repeatedly, it is possible to realize the screen scrolling and page switching
without changing the contents of DDRAM as shown in figure 6-6.
At the beginning of each LCD frame, the contents of register are copied to the line counter which is
increased by +1 and the line address is generated for transferring the 132-bit RAM data to the display
data latch circ uit. Ho wever, the d ispl ay data of ico ns is not sc rolled b ecaus e the MPU c an not acces s the
line address of icons.
e. Segment control circuit
This circuit controls the display data by the Display ON / OFF, reverse display ON / OFF and entire
display ON /OFF instructions without changing the data in the DDRAM.
SEG OUTPUT SEG0 SEG1 SEG2 SEG4 ……… SEG128 SEG129 SEG130 SEG131
Column address[Y7: Y0] 00H 01H 02H 04H ……… 80H 81H 82H 83H
Display data 1 0 1 1 0 1 0 1
LCD panel displa y
(ADC = 0)
LCD panel displa y
(ADC = 1)
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Figure 6-6. Display data RAM map
Page address
DB3 DB2 DB1 DB0 data Line
address COM
output
DB0 00H COM0
DB1 01H COM1
DB2 02H COM2
DB3 03H COM3
DB4 04H COM4
DB5 05H COM5
DB6 06H COM6
0000
DB7
Page 0
07H COM7
DB0 08H COM8
DB1 09H COM9
DB2 0AH COM10
DB3 0BH COM11
DB4 0CH COM12
DB5 0DH COM13
DB6 0EH COM14
0001
DB7
Page 1
0FH COM15
DB0 10H COM16
DB1 11H COM17
DB2 12H COM18
DB3 13H COM19
DB4 14H COM20
DB5 15H COM21
DB6 16H COM22
0010
DB7
Page 2
17H COM23
DB0 18H COM24
DB1 19H COM25
DB2 1AH COM26
DB3 1BH COM27
DB4 1CH COM28
DB5 1DH COM29
DB6 1EH COM30
0011
DB7
Page 3
1FH COM31
DB0 20H COM32
DB1 21H COM33
DB2 22H COM34
DB3 23H COM35
DB4 24H COM36
DB5 25H COM37
DB6 26H COM38
0100
DB7
Page 4
27H COM39
DB0 28H COM40
DB1 29H COM41
DB2 2AH COM42
DB3 2BH COM43
DB4 2CH COM44
DB5 2DH COM45
DB6 2EH COM46
0101
DB7
Page 5
2FH COM47
DB0 30H COM48
DB1 31H COM49
DB2 32H COM50
DB3 33H COM51
DB4 34H COM52
DB5 35H COM53
DB6 36H COM54
0110
DB7
Page 6
37H COM55
DB0 38H COM56
DB1 39H COM57
DB2 3AH COM58
DB3 3BH COM59
DB4 3CH COM60
DB5 3DH COM61
DB6 3EH COM62
0111
DB7
Page 7
3FH COM63
1000DB0 Page 8 COMS
ADC = 0 00 01 02 03 04 05 06 ………….. 7B 7C7D 7E 7F 80 81 83
Column address ADC = 1 83 82 81 80 7F 7E 7D …………. 08 07 06 05 03 02 01 00
LCD output
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
…………..
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
1/33
DUTY 1/49 DUTY
START
1/65 DUTY
When the initial display line
address is 1CH
1/55 DUTY
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6-3. LCD DISPLAY CIRCUITS
a. Oscillator
HT0324A implement complete on-chip oscillator and its frequency is nearly independent of VDD.
This oscillator signal is used in the voltage converter and display timing generation circuit.
The oscillator circuit is enabled when MS=”H” and CLS=”H”. When the external clock is used, set
CLS=”L” and imply clock signal to CL pin.
b. Display timing generator circ uit
This circuit generates timing signals to be used for displaying LCD. The display clock (CL) is generated
by oscillation clock and CL generates the clock for the line counter and the signal for the display data
latch. The line address of DDRAM is generated in synchronization with CL. The 132-bit display data is
latched in the display data latch circuit synchronized with CL. Reading to the display data liquid crystal
driver circuit is completely independent of access to the DDRAM by the MPU. The display timing
generator circuit generates an LCD AC signal (M) which enables the LCD driver to make a AC drive
waveform, and also generates an internal common timing signal and start signal to the common driver.
Driving 2-frame AC driver waveform and internal timing signal are shown in figure 6-7.
When HT0324A is used multiple-chip configuration, the slave chip requires the M, CL and DISP signals
from the master. Table 6-4 shows the M, CL, and DISP status.
Table 6-4. Master and slave timing signal status
Operation mode Clock MS CLS M CL FRS,
FR DISP
Internal H H Output Output Output Output
Master mode External H L Output Input Output Output
Internal L H Input Input Output Input
Slave mode External L L Input Input Output Input
Figure 6-7. 2-frame AC driving waveform (Duty ratio = 1/65)
CL
FR
COM0
COM1
SEGn
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
64 65 1 2 3 4 5 6 7 8 9 10 …………… 57 58 59 60 61 62 63 64 65 1 2 3 4
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c. Common output control circuit
This cir cuit c ontr o ls the re latio ns hi p be t wee n th e n umber of common output a nd s pecif ied duty rat io. SHL
select instruction specifies the scanning direction of the common output pins.
Table 6-5. The relationship between duty ratio and common output
Common output pins
Duty SHL COM
[0:15] COM
[16:23] COM
[24:26] COM
[27:36] COM
[37:39] COM
[40:47] COM
[48:63] COMS
0 COM[0:15] *NC COM[16:31]
1/33 1 COM[31:16] *NC COM[15:0] COMS
0 COM[0:23] *NC COM[24:47]
1/49 1 COM[47:24] *NC COM[23:0] COMS
0 COM[0:26] *NC COM[27:53]
1/55 1 COM[53:27] *NC COM[26:0] COMS
0 COM[0:63]
1/65 1 COM[63:0] COMS
*NC : No Connection
6-4. LCD DRIVER CIRCUIT
This driver circuit is configured by 66-channel common drivers (including 2COMS channels) and 132-
channel s egm ent dr ivers . This LCD panel dr iver vo ltage dep ends on the com binat ion of disp la y data an d
FR signal.
Figure 6-8. Segment and common timing
SEG0
SEG1
SEG2
SEG3
SEG4
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
FR
COM0
COM1
COM2
SEG0
SEG1
SEG2
VDD
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
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6-5. POWER SUPPLY CIRCUITS
The power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with
low power cons umption and t he f e west componen ts . There ar e vo ltag e c on vert er cir c uits, vo ltage reg ul ator
circuits, and voltage follower circuits. They are valid only in master operation and controlled by power
control ins truc ti on.
For details, ref ers to "Ins truct ion des cript ion". Table 6-6 sh ows th e ref erenced c om binatio ns in usin g po wer
supply circuits.
Table 6-6. Recommended power supply combinations
Mode Settings VC,VR,VF Voltage
converter Voltage
regulator Voltage
follower VOUT V0 V1 to V4
All
Internal powe r supply 1, 1, 1 ON ON ON Open Open Open
Voltage regulator
and voltage follower 0, 1, 1 OFF ON ON External
input Open Open
Voltage follower 0 , 0, 1 OFF OFF ON Open External
input Open
All
external power supply 0, 0, 0 OFF OFF OFF Open External
input External
input
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a. Voltage converter circuits
These circuits boost up the electric potential between VCI and VSS to 2, 3, 4 or 5 times toward positive side
and boosted voltage is outputted from VOUT pin.
[C1 = 1.0 to 4.7µF]
Figure 6-9. Two times boosting circuit Figure 6-10. Three times boosting circuit
Figure 6-11. Four times boosting circuit Figure 6-12. Five times boosting circuit
*. The VCI voltage range must be set so that the VOUT voltage does not exceed the absolute maximum
rated value.
VDD
VDD VCI
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VSS
C1
C1
HT0324A
VOUT = 2 x VCI
VCI
VSS
VCI
GNDGND
VDD
VDD VCI
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VSS
C1
C1
C1
HT0324A VOUT = 3 x VCI
VCI
VSS
VCI
GNDGND
VDD
VDD VCI
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VSS
C1
C1
C1
C1
HT0324A
VOUT = 5 x VCI
VCI
VSS
VCI
GNDGND
C1
VDD
VDD VCI
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VSS
C1
C1
C1
C1
HT0324A VOUT = 4 x VCI
VCI
VSS
VCI
GNDGND
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b. Voltage regulator circuits
The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0, by
the adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating
voltage of operational-amplifier circuits as shown in figure 6-13, it is necessary to be applied internally or
externally.
For the equation 1, we determine V0 by Ra, Rb and VEV. Ra and Rb are connected internally or externally by
INTRS pin. T he voltage of electr onic volum e, VEV, is determ ined b y equat ion 2, where the ref erence vol tage
parameter α
is the value selected by instruction, "Set reference voltage register", within the range 0 to 63.
Refer to table 6-8. VREF voltage at Ta =25°C is show in table 6-7.
V0 = ( 1 + ) x VEV [V] ------ (Equation 1)
VEV = ( 1 - ) x VREF [V] ------ (Equation 2)
Table 6-7. VREF voltage at Ta =25°
°°
°C
REF Temp. coefficient VREF[V]
H-0.05% / °C2.1
L External input VEXT
Table 6-8. Electronic contrast control register (Reference Voltage Parameter : α
αα
α, 64step)
SV5 SV4 SV3 SV2 SV1 SV0 Reference Voltag e
Parameter ( α
αα
α)V0 Contrast
000000 0
000001 1
:
::
::
::
::
::
::
:
100000 32 (default)
:
::
::
::
::
::
::
:
111110 62
111111 63
Minimum
:
:
:
:
:
:
:
:
:
:
:
Maximum
Low
:
:
:
:
:
:
:
:
:
:
:
High
Rb
Ra
( 63-α )
162
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Figure 6-13. Internal voltage regulator circuit
+
-
VOUT
VEV
V0
Rb
VR
Ra
VSS
GND
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b-1. In case of using internal resistors, Ra and Rb (INTRS = "H")
When INTRS pin is “H”, resistor Ra is connected internally between VR pin and VSS, and Rb is connected
between V0 and VR. We determine V0 by two instructions, "Regulator resistor select" and "Set reference
voltag e".
Table 6-9. Internal Rb / Ra ratio depending on 3-bit Data (R2, R1, R0)
3-bit data settings(R2 R1 R0: gain)
000 001 010 011 100 101 110 111
1+(Rb/Ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and
6-bit electronic volume registers for each temperature coefficient at Ta = 25 °C.
Figure 6-13. Electronic volume level
0
2
4
6
8
10
12
14
16
0 5 10 15 20 25 30 35 40 45 50 55 60 63
Electronic volum e level
V0[V]
gain 111
gain 110
gain 101
gain 100
gain 011
gain 010
gain 001
gain 000
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b-2. In case of using external resistors, Ra and Rb. (INTRS = "L")
W hen INTRS pin is “L” , it is neces sar y to conn ect exter nal r egu lator r esistor Ra betwe en V R and VSS, and
Rb between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 10V
2. 6-bit reference voltage register = ( 1, 0, 0, 0, 0, 0 : α = 32)
3. Maximum current flowing Ra, Rb = 1[µA]
From equation 1
10 = ( 1 + + ) x VEV [V] ------ (Equation 3)
From equation 2
VEV = ( 1 - - ) x 2.1 ≅ 1.698 [V] ------ (Equation 4)
From equation 3
= 1[µA] ------ (Equation 5)
From equation 3, 4 and 5 Ra = 1.69[MΩ]
Rb = 8.31[MΩ]
The following table shows the range of V0 depending on the above requirements.
Table 6-10. V0 depending on electronic volume level
Electric Volume Level
0 ------ 32 ------- 63
V0 7.57 ------ 10.00 ------- 12.43
(63-32)
162
Rb
Ra
10
(
Ra + Rb
)
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c. Voltage follower circuits
VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output
impedance are converted by the voltage follower for increasing drive capability. The following table shows
the relationship between V1 to V4 level and each duty ratio.
Table 6-11. The relationship between V1 to V4 level and duty ratio
Duty Ratio DSEL1 DSEL0 LCD Bias V1 V2 V3 V4
1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
1/33 L L 1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/49 L H 1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/55 H L 1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/7 (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0
1/65 H H 1/9 (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0
d. High power mode
The power supply circuit equipped in the HT0324A for LCD drive has very low power consumption (in
norm al mode : /HPM = “ H” ). If us e f or LCD panels with lar g e l oads, this lo w-po wer sup p l y m a y cause dis p lay
qualit y to degr ade. When this occurs , setting t he / HPM p in to “L” (high p ower m ode) can im prove the qual it y
of the display. Moreover, if the quality of display is inadequate even after High Power mode has been set,
then it is necessary to add a liquid crystal drive power supply externally (VOUT or V0 or V1 V2 V3 V4).
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6-6. REFERECE CIRCUIT EX AMPLS
When using internal regulator resistors. When not using internal regulator resistors.
Figure 6-15. When using all LCD power circuits (VCI = VDD, 4-time, V/C: ON, V/R: ON, V/F: ON)
When using internal regulator resistors. When not using internal regulator resistors.
Figure 6-16. When using some LCD power circuits (VCI = VDD, V/C: OFF, V/R: ON, V/F: ON)
VDD
IN T RS V DD VCI MS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
C1
C1
C1
C2
C2
C2
C2
C2
HT0324A
GNDGND
•
•
C1
VDD
INT R S V D D VCI MS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
C1
C1
C1
Ra
C2
C2
C2
C2
C2
HT0324A
GNDGND
•
•
Rb
GND
C1
VDD
INT RS V DD V CI MS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
C2
C2
C2
C2
C2
HT0324A
GNDGND
External
power
supply
VDD
INT R S VD D VCI M S
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
Ra
C2
C2
C2
C2
C2
HT0324A
GNDGND
Rb
GND
External
power
supply
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Figure 6-17. When using some LCD power circuits (VCI = VDD, V/C: OFF, V/R: OFF, V/F: ON)
Figure 6-18. When not using any LCD power supply circuits
(VCI = VDD, V/C: OFF, V/R: OFF, V/F: OFF)
*. C1 and C2 are determined by the size of the LCD being driven.
Select a value that will stabilize the liquid crystal drive voltage.
VDD
INTR S V DD VCI MS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
C2
C2
C2
C2
C2
HT0324A
GNDGND
External
power
supply
VDD
INTRS VDD VCI MS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VR
V0
V1
V2
V3
V4
VSS
HT0324A
GND
GND
External
power
supply
Value of external capacitance
Item Value Unit
C1 1.0 ~ 4.7
C2 0.47 ~ 1.0 µF
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6-7. RESE T CIRCUIT
Setting /RESET to “L” or reset instruction can initialize internal function.
When /RESET becomes “L”, following procedure is occurred.
Display ON / OFF: OFF (DON = 0).
Entire disp lay ON / OFF: OFF (normal = 0).
ADC select: OFF (normal = 0)
Reverse display ON / OFF: OFF (normal = 0).
Power control register (VC, VR, VF) = (0, 0, 0)
Serial interface internal register data clear
LCD power supply bias ratio: bias bit 0
(Refer to LCD bias select of instruction table and duty ratio by DSEL1, DSEL0 pin setting)
Liquid cry stal bias
Duty ratio DSEL1 DSEL0 Bias = 0 Bias = 1
1/33 0 0 1/6 1/5
1/49 0 1 1/8 1/6
1/55 1 0 1/8 1/6
1/65 1 1 1/9 1/7
On-chip oscillator OFF (while /RESET is “L”)
Power save release
Set modify-read: OFF
SHL select: OFF (normal = 0).
Static indicator mode: OFF.
Static indicator register: (S1, S0) = (0, 0)
Display start line: 0 (first)
Column address: 0.
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (1, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
Test mode release
When RESET instruction is issued, following procedure is occurred.
Set modify-read: OFF
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
SHL select: OFF (normal = 0)
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (1, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)
Test mode release
While /RESET is “L”, or Reset instruction is executed, no instruction except read status can be accepted.
Reset status appears at DB4. After DB4 becomes “L”, any instruction can be accepted. /RESET must be
connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The
initialization by /RESET is essential before used.
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7. PROGRAM INSTRUCTIO N DESCRI PTION
Table 7-1. Instruction table X: Don’t’ care
Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Read display
data 1 1 Read data Read data from DDRAM
Write display
data 1 0 Write data Write data into DDRAM
Read status 0 1 BUSY ADC ON /
OFF /RESET 0 0 0 0 Read the internal status
Display
ON / OFF 001 0 1 0 111DON Turn ON / OFF L CD panel
When DON = 0: display OFF
When DON=1 : display ON
Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM0
Set reference
voltage mode 0 0 1 0 0 0 0 0 0 1 Set reference voltage mode
Set reference
voltage register 0 0 X X SV5 SV4 SV3 SV2 SV1 SV0 Set reference voltage register
Set page
address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address
Set column
address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB
Set column
address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB
ADC select 0 0 1 0 1 0 0 0 0 ADC
Select SEG output dir ection.
When ADC = 0 : normal direction
(SEG0 ⇒ SEG131)
When ADC = 1 ; reverse direction
(SEG131⇒ SEG 0)
Reverse display
ON / OFF 001 0 1 0 011REV
Select normal / reverse display
When REV = 0 : normal display
When REV = 1 : reverse display
Entire display
ON / OFF 001 0 1 0 010EON
Select normal / entire display ON
When EON = 0 : normal display
When EON = 1 : entire display ON
LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias
Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode
Reset
modify-read 0 0 1 1 1 0 1 1 1 0 Release mod ify-read mode
Reset 0 0 1 1 1 0 0 0 1 0 Ini tialize the internal function
SHL select 0 0 1 1 0 0 SHL X X X
Select COM output direction
When SHL = 0 : normal direction
(COM0⇒ COM63)
When SHL = 1 : reverse direction
(COM63 ⇒ COM0)
Power cont rol 0 0 0 0 1 0 1 VC VR VF Control po wer circuit operatio n
Regulator
resistor se lect 00 0 0 1 0 0 R2R1 R0Select internal resistance ratio of
the regulator resistor
Set static
indi cat or mod e 0 0 1 0 1 0 1 1 0 SM Set static indicator mode
Set static
indicator register 0 0 X X X X X X S1 S0 Set static indicator register
Power save - - - - - - - - - - Compound i nstruct ion of display
OFF and entire display ON
NOP 0 0 1 1 1 0 0 0 1 1 Non-O peration command
Test
Instruction_1 0 0 1 1 1 1 X X X X Don’t use this instruction
Test
Instruction_2 0 0 1 0 0 1 X X X X Don’t use this instruction
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7-1. Read display data
The 8-bit data from DDRAM specified by the column address and the page address can be read by this
instruc tion. As the colum n addr ess is incr ease d b y 1 autom atic all y after eac h this instr uctio n, the MP U c an
continuously read the data from the addressed page. A dummy read is required after loading an address
into the column address register. Display data cannot be read through the serial interface.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 Read data
7-2. Write display data
8-bit data of display data from the MPU can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the MPU can
continuously write data to the addressed page.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 Write data
Figure 7-1. Sequence for writing display data Figure 7 -2. Sequence for reading display data
NO
YES
Data read continue?
Set page address
Set column address
Dummy data read
Column = Column + 1
Data read
Optional status
Column = Column + 1
Set page address
Data write continue?
NO
YES
Set column address
Data write
Column = Column + 1
Optional status
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7-3. Read status
Indicates the internal status of the HT0324A.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BUSY ADC ON/OFF /RESET 0000
Flag Description
BUSY The device is busy when internal operation or reset. Any instruction is rejected until
BUSY goes Low.
0: chip is active, 1: chip is being busy.
ADC Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG131 −>
−>−>
−>SEG0), 1: normal direction (SEG0 −>
−>−>
−>SEG131)
ON / OFF Indicates display ON / OFF status
0: display ON, 1: display OFF
/RESET Indicate the /RESET.
0: chip is active, 1: chip is being reset
7-4. Display ON / OFF
Turns the display ON or OFF
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010111DON
DON = 1: display ON
DON = 0: display OFF
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7-5. Initial Display Line
Sets the line a ddress of DDRA M to determ ine the initi al displa y line. The RA M display dat a is disp layed at
the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0
ST5 ST4 ST3 ST2 ST1 ST0 Line address
000000 0
000001 1
:::::: :
111110 62
111111 63
7-6. Reference voltage select
Consists of 2-b yte ins tructi on the f irst ins truct ion se ts ref erence v oltage m ode, the sec ond one updates th e
contents of reference voltage register. After second instruction, reference voltage mode is released.
The first instruction: Set reference voltage select mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0010000001
The second instruction: Set reference voltages select mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 X X SV5 SV4 SV3 SV2 SV1 SV0
SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage
parameter (α
αα
α)V0 Contrast
000000 0
000001 1
:::::: :
100 0 0 0 32 (default)
:::::: :
111110 62
111111 63
Min
:
:
:
:
:
:
:
:
:
:
Max
Low
:
:
:
:
:
:
:
:
:
:
High
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Figure 7-3. Sequence for setting the reference voltage
7-7. Set page address
Sets the p age addres s of DDRAM f rom the MP U into the page address regis ter. Any RAM da ta bi t can be
accessed when its page address and column address are specified. Along with the column address, the
page address defines the address of the DDRAM to write or read display data. Changing the page address
doesn't effect to the display status.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 1 1 P3 P2 P1 P0
P 3P 2P 1P 0 Page
0000 0
0001 1
:::: :
0111 7
1000 8
Setting reference volt age start
First instruction for mode setting
Second instruction for register setting
Setting reference voltage end
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7-8. Set column address
Sets the column address of DDRAM from the MPU into the column address register. Along with the
column address, the column address defines the address of the DDRAM to write or read display data.
When the MPU reads or writes display data to or from DDRAM, column addresses are automatically
increased.
Set column address MSB
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 1 Y7Y6Y5Y4
Set column address LSB
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 Y3Y2Y1Y0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address
00000000 0
00000001 1
:::::: :
10000010 130
10000011 131
7-9. ADC select
Changes the relati onship bet ween DDRAM colum n address and segm ent driver. The direc tion of segm ent
driver output pin can be reversed by software. This makes IC layout flexible in LCD module assembly.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010000ADC
ADC = 0: normal direction (SEG0 ⇒
⇒⇒
⇒
SEG131)
ADC = 1: reverse direction (SEG131 ⇒
⇒⇒
⇒ SEG0)
7-10. Reverse display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the DDRAM.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010011REV
REV RAM bit data = “1” RAM bit data = “0”
0(Normal) Liquid crystal pixel is illuminate d Liqu id crys tal pixel is not illuminate d
1(Reversed) Liquid crystal pixel is not illumin ated Liquid crys tal pixel is illuminate d
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7-11. Entire display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the DDRAM. At this time, the
contents of the DDRAM are held. This instruction has priority over the reverse display ON / OFF
instruction.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010010EON
EON = 0: normal display
EON = 1: entire display ON
7-12. Select LCD bias
Selects LCD bias ratio of the voltage required for driving the LCD.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010001Bias
Liquid cry stal bias
Duty ratio DSEL1 DSEL0 Bias = 0 Bias = 1
1/33 0 0 1/6 1/5
1/49 0 1 1/8 1/6
1/55 1 0 1/8 1/6
1/65 1 1 1/9 1/7
7-13. Set modif y-read
This instruction stops the autom atic increm ent of the colum n address by the read displa y data instruction,
but the colum n addres s is still inc reas e d by the wri te d isp lay data ins tr uct ion. And it r educ es the load of the
MPU when the data of a spec if ic area is r epeate dl y changed d uring curs or blink ing or other s. T his m ode is
canceled by the reset modify-read instruction.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011100000
7-14. Reset modify-read
This instruction cancels t he modif y-read m ode, and mak es the colum n addres s retur n to its in itial value j ust
before the set modify-read instruction is started.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011101110
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Figure 7-4. Seque nce for cursor display
7-15. Reset
This instruc tion r esets init ial d ispla y line, c olum n addres s, p age ad dres s, and com m on output stat us sel ect
to their initial status, but dose not affects the contents of DDRAM. This instruction can not initialize the LCD
power supply which is initialized by the /RESET pin.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011100010
7-16. SHL select
COM output scanning direction is selected by this instruction which determines the LCD driver output
status.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001100SHLXXX
Set page address
Se t m o dify-read
C hange com p lete ?
NO
Data
process
YES
Set column address(N)
Dummy read
D a ta rea d
D a ta w rite
R es e t m od ify-rea d
R eturn c olum n ad dress (N )
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SHL = 0: normal direction (COM0 ⇒
⇒⇒
⇒
COM63) X : Don’t care
SHL = 1: reverse direction (COM63 ⇒
⇒⇒
⇒
COM0)
7-17. Pow er cont ro l
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of
internal power supply functions can be used simultaneously.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 1 VC VR VF
VC VR VF Internal power supply circuits status
0
1Voltage converter circuit is OFF
Voltage converter circuit is ON
0
1Voltage regulator circuit is OFF
Voltage regulator circuit is ON
0
1Voltage follower circuit is OFF
Voltage Follower circuit is ON
7-18. Regulator resistor select
Selects resistanc e rati o of the interna l resistor used in the internal voltage regu lator. See voltage r egulator
section in power supply circuit. Refer to the table 6-9.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 0 R2 R1 R0
R2 R1 R0 (1 + Rb / Ra ) ratio
0003.0
0013.5
010 4.0
011 4.5
1 0 0 5.0 (default)
101 5.5
110 6.0
111 6.4
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7-19. Set static indicator state
Consists of two bytes instruction. The first byte instruction (set static indicator mode) enables the second
byte instruction (set static indicator register) to be valid. The first byte sets the static indicator ON / OFF.
When it is ON, the second byte updates the contents of static indicator register without issuing any other
instruction and this static indicator state is released after setting the data of indicator register.
The first instruction: Set static indicator mode (ON / OFF)
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001010110SM
SM = 0: static indicator OFF
SM = 1: static indicator ON
The second instruction: Set static indicator register
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00XXXXXXS1S0
S1 S0 Static indicator output status
00 OFF
0 1 ON (about 1 second blinking)
1 0 ON (about 0.5 second blinking)
1 1 ON ( always ON)
7-20. NOP
Non Operation Instruction
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0011100011
7-21. Test Instruction (Test Instruction_1 & Test Instruction_2)
These are the instruction for IC chip testing. Please do not use it. If the Test Instruction is used by
accident, it can be cleared by applying “0” signal to the /RESET input pin or the reset instruction.
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
001111XXXX
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001001XXXX
7-22. Power save (Compound instruction).
If the entire display ON / OFF instruction is issued during the display OFF state, HT0324A enters the
power save status to reduce the power consumption to the static power consumption value. According to
the status of static indicator m ode, po wer save is entered t o one of t wo m odes (sleep a nd sta ndby m ode).
W hen static indic ator m ode is ON , standb y mode is issued, when OFF, sleep mode is iss ued. P ower s ave
mode is released by the display OFF instruction.
Figure 7-5. Power save routine
-Sleep Mode
This stops all operations in the LCD display system, and as long as there are no access from the MPU,
the consumption current is reduced to a value near the static current. The internal modes during sleep
mode are as follows:
a. The oscillator circuit and the LCD power supply circuit are halted.
b. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VSS level.
-Standby Mode
The duty LCD display system operations are halted and only the static drive system for the indicator
continues to operate, providing the minimum required consumption current for the static drive.
The internal modes are in the following states during standby mode.
a. The LCD power supply circuits are halted. The oscillator circuit continues to operate.
b. The duty drive system liquid crystal drive circuits are halted and the segment and common drive outputs
Static ind ica t o r OFF St a t ic ind ica t o r ON
Po wer save(C ompound instruction)
[Dis p la y OF F]
[E ntire display O N ]
Sleep m od e
[Oscillator circuit:
O
[LCD power supply
[All COM/SEG :
[Consumption current:
µA>
Sleep m od e
[Os cilla t o r c ir c uit: OFF]
[LCD power supply circuit:O FF]
[A ll COM/SEG : V SS ]
[C onsumption curren t:<2µA]
Standby
d
[Oscillator circuit:
O
[LCD power supply
[All COM/SEG :
[Consumption current:
µA>
Standby
d
[Os c illa to r c irc u it: ON]
[LCD power supply circuit:O FF]
[A ll COM/SEG : V SS ]
[C onsumption curren t: <10µA]
Po wer save O FF(Compound instruction)
[E ntire display O FF]
[S ta t ic in d ic a to r ON]
2 B
y
tes C ommand
Power save OFF
[E ntire display O FF]
Release sleep
d
R elease sleep m o de Release standby
d
R elease standb y m ode
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a VSS level. When a reset command is performed while in standby mode, the system enters sleep
mode.
7-23. Referential instruction setup flow (1)
Figure 7-6. Initializing with the built-in power supply circuits
U ser system setu p by external pins
S ta rt o f in itia liz a tion
S ta rt o f in itia liz a tion
Power ON(VDD-VSS)keeping the /R ESET Pin = “L”
/RESET Pin = “H”
U ser ap plication setu p by internal instructions
[ADC s e le c t]
[SHL select]
[LC D bias select]
User LC D power setup by internal instructions
[V oltage converter ON ]
User LC D power setup by internal instructions
[V oltage follow er O N]
Wa itin g fo r s ta b iliz ing th e p o we r
User LC D power setup by internal instructions
[V o lta g e re g ula to r ON]
User LC D power setup by internal instructions
[R egulator resistor select]
[Reference voltage register set]
Wa itin g for s ta b iliz in g the LCD p owe r le v e ls
End of init ia liza t io n
End of init ia liza t io n
Wa itin g fo r >1ms
Wa itin g fo r >1ms
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Referential instruction setup flow (2)
Figure 7-7. Initializing without the built -in power supply circuits
S ta r t o f in itia liza tion
S ta r t o f in itia liza tion
P ower O n(VD D -VS S) keeping the /R ES E T P in = “L”
/RESET Pin = “H”
S et pow er save
U ser application setu p by internal instructions
[ADC s e le c t]
[SHL s ele c t ]
[LC D bias select]
R elease pow er save
U ser LC D pow er setup by internal instructions
[R egulator resistor select]
[R eference voltage register set]
E n d of in it ializ a tio n
E n d of in it ializ a tio n
U ser system setup by external pins
Wa itin g fo r s ta b iliz in g th e p o we r
Wa itin g fo r s ta b iliz in g th e L CD p o we r le v e ls
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Referential Instruction Setup Flow (3)
Figure 7-8. Data display
E n d o f in itia liz a tio n
E n d o f in itia liz a tio n
DDRA M ad dress by instruction
[initial display line]
[Set page address]
[Set column address]
Write display ON/OFF by instruction
[D isp la y O N/OF F ]
End of data display
End of data display
Turn d isplay ON /OFF by instruction
[D isp la y O N/OF F ]
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Referential instruction setup flow (4)
Figure 7-9. Power off.
Wa itin g fo r > 1m s
Wa itin g fo r > 50m s
Wa itin g fo r > 1m s
Optional status
Optional status
Turn display ON /OF F by instruction
[D isplay OF F]
Power O FF(VDD - VSS)
Power O FF(VDD - VSS)
U ser LCD pow er setup by internal instructions
[V o lta g e fo llo we r OF F]
U ser LCD pow er setup by internal instructions
[Voltage regulator O FF ]
U ser LCD pow er setup by internal instructions
[Voltage converter O FF ]
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8. SPECIFICATIONS
8-1. Absolute maximum ratings
Table 8-1. Absolute maximum ratings
Parameter Symbol Rating Unit
VDD -0.3 to +7.0
Supply voltage range VLCD -0.3 to +17.0
Input voltage range VIN -0.3 to VDD +0.3
V
Operating temperature range TOPR -40 to +85
Storage temperature range TSTR -55 to +125
oC
Notes:
1. VDD and VLCD are based on VSS = 0V.
2. Voltages V0 >V1>V2>V3>V4>VSS(GND) must always be satisfied.(VLCD = V0 - VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.
8-2. DC Characteristics
Table 8-2. DC characteristics ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85oC)
Item Symbol Condition Min Typ Max Unit Pin
Used
Operating voltage(1) VDD 2.4 - 5.5 VDD *1
Operating voltage(2) V0 4.5 - 15.0 V0 *2
High VIH 0.8VDD -V
DD
Input
voltage Low VIL VSS -0.2V
DD *3
High VOH IOH=-0.5mA 0.8VDD -V
DD
Output
voltage Low VOL IOL=0.5mA VSS -0.2V
DD
V
*4
Input leakage current IIL VIN=VDD or
VSS -1.0 - +1.0 *5
Output leakage current IOZ VIN=VDD or
VSS -3.0 - +3.0 µA *6
LCD driver
ON resistance RON Ta = 25 oC
V0 = 8V -2.03.0
kΩSEGn
COMn
*7
Internal fOSC 32.7 43.6 54.5
Oscillator
frequency External fCL
Ta = 25 oC
Duty ratio =
1/65 4.09 5.45 6.81 kHz CL*8
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Table 8-2. DC characteristics (continued) ) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85oC)
Item Symbol Condition Min. Typ. Max. Unit Pin
used
x 2 2.4 - 5.5
x 3 2.4 5.3
x 4 2.4 4.0
Voltage converter input
voltage VCI
x 5 2.4 3.2
VVCI
Voltage converter output
voltage VOUT
x 2 / x 3 / x 4 /
x 5
voltage
conversion
(no-load)
95 99 - % VOUT
Voltage regulator
operating voltage VOUT - 6.0 - 16.0 VOUT
Voltage follower
operating voltage V0 - 4.5 - 15.0 V0*9
Reference voltage VREF Ta = 25 oC
-0.05%/ oC2.04 2.1 2.16
V
*10
Table 8-2. DC Characteristics (Continued) ( VSS = 0V, VDD = 2.4V to 5.5V, Ta = -40 to +85oC)
Dynamic current consumption (1): Built-in circuit OFF (At operating mode)
Dynamic curr ent
consumption (1) IDD1
VDD = 3.0V,
V0 – VSS= 11.0V,
1/65 duty ratio,
display pattern OFF
-1523
µA*11
Dynamic Current Consumption (2): Built-in circuit ON (At operating mode)
VDD = 3.0V,
(VCI=VDD,4times
boosting)
V0 – VSS= 11.0V,
1/65 duty ratio,
display pattern OFF,
normal power mode
-4060
µA*12
Dynamic curr ent
consumption (2) IDD2 VDD = 3.0V,
(VCI=VDD, 4 times
boosting)
V0 – VSS= 11.0V,
1/65 duty ratio,
display pattern check,
normal power mode
- 150 200 µA*12
Current consumption during power sa ve mode
Sleep mode current IDDS1 During sleep - - 2.0 µA
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Standby mode current IDDS2 During standby 10.0 µA
Table 8-3. The relationship between oscillation frequency and frame frequency
Duty ratio Item fCL fFR
On-chip oscillator circuit is used fOSC / 8 fOSC / ( 2 x 8 x 65)
1/65 External clo ck is used External Input(fCL)fCL / ( 2 x 65)
On-chip oscillator circuit is used Fosc / 9 Fosc / (2 x 9 x 55)
1/55 External clo ck is used External input (fCL) fCL / (2 x 55)
On-chip oscillator circuit is used fOSC / 10 fOSC / ( 2 x 10 x 49)
1/49 External clo ck is used External Input (fCL)fCL / ( 2 x 49)
On-chip oscillator circuit is used fOSC / 15 fOSC / (2 x 15 x 33)
1/33 External clo ck is used External Input (fCL)fCL / ( 2 x 33)
*(fOSC: oscillation frequency, fCL: display clock frequency, fFR: LCD AC signal frequency)
<* Remark solves>
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU
*2. In case of external power supply is applied.
*3. /CS1, CS2, RS, DB7 to DB0, E_/RD, RW_/RW, /RESET, MS, C68, PS, INTRS, /HPM, CLS, CL, M, DISP pins.
*4. DB0 to DB7, M, FR, FRS, DISP, CL pin.
*5. /CS1, CS2, RS, DB7 to DB0, E_/RD, RW_/WR, /RESET, MS, C68, PS, INTRS, /HPM, CLS, CL, M, DISP pins.
*6. Applies when then DB7 to DB0, M, FR, FRS, DISP, and CL, pins are in high impedance.
*7. Resistance value when ±0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON = ∆V / 0.1[kΩ] (∆V :Voltage change when ±0.1[mA]is applied in the on status)
*8. See table 8-3 for the relationship between oscillation frequency and frame frequency.
*9. The Voltage regulator circuit adjusts V0 within the voltage follower operating voltage range.
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11, 12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built -in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD penal capacity, wiring capacity, etc.
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8-3. AC CHARACTERISTICS
a. Read / write characteristics (8080-series MPU)
Figure 8-4. Read / write timing chart (8080-series MPU)
(VDD = 2.4 to 3.6V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Address setup time
Address hold time RS tAS80
tAH80 0
0--ns
System cy cle tim e RS tCY80 300 - - ns
Pulse width(/WR) RW-/WR tPW80 ( W ) 60 - - ns
Pulse width(/RD) E-/RD tPW80 ( R ) 60 - - ns
Data setup time
Data hold time tDS80
tDH80 40
15 --ns
Read access time
Output disable time
DB7
to
DB0 tACC80
tOD80 -
10 -140
100 ns CL = 100pF
(VDD = 3.6 to 5.5V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Address setup time
Address hold time RS tAS80
tAH80 0
0--ns
System cy cle tim e RS tCY80 166 - - ns
Pulse width(/WR) RW-/WR tPW80 ( W ) 30 - - ns
Pulse width(/RD) E-/RD tPW80 ( R ) 30 - - ns
Data setup time
Data hold time DB7
to
DB0
tDS80
tDH80 30
10 --ns
tAS80 tAH80
tCY80
tPW80(R), tPW80(W)
0.1VDD
0.9VDD
tDS80 tDH80
tACC80 tOD80
RS
/CS1
(CS2=1)
/RD, /WR
DB7 ~ DB0
(Write)
DB7 ~ DB0
(Read)
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Read access time
Output disable time tACC80
tOD80 -
5-70
50 ns CL = 100pF
b. Read / write characteristics (6800-series MPU)
Figure 8-5. Read / write timing chart (6800-series MPU)
(VDD = 2.4 to 3.6V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Address setup time
Address hold time RS tAS68
tAH68 0
0--ns
System cy cle tim e RS tAH68 300 - - ns
Enable
pulse width Read
Write E-/RD tPW68 ( R )
tPW68 ( W ) 120
60 ---
Data setup time
Data hold time tDS68
tDH68 40
15 --ns
Access tim e
Output disable time
DB7
to
DB0 TACC68
tOD68 -
10 -140
100 ns CL =
100pF
(VDD = 3.6 to 5.5V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Address setup time
Address hold time RS tAS68
tAH68 0
0--ns
System cy cle tim e RS tAH68 166 - - ns
Enable
pulse width Read
Write E-/RD tPW68 ( R )
tPW68 ( W ) 70
30 ---
Data setup time
Data hold time tDS68
tDH68 30
10 --ns
Access tim e
Output disable time
DB7
to
DB0 TACC68
tOD68 -
10 -70
50 ns CL =
100pF
tAS68 tAH68
tCY68
tPW68(R), tPW680(W)
0.9VDD
0.1VDD
tDS68 tDH68
tACC68 tOD68
RS
/CS1
(CS2=1)
E
DB7 ~ DB0
(Write)
DB7 ~ DB0
(Read)
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c. Serial interface characteristics
Figure 8-6. Serial interface characteristics
(VDD = 2.4 to 3.6V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Serial cl oc k cycl e
SCLK high pulse width
SCLK low pulse width
DB6
(SCLK)
tCYC
tWHS
tWLS
250
100
100 --ns
Address setup time
Address hold time RS tASS
tAHS
150
150 --ns
Data setup time
Data hold time DB7
(SID) tDSS
tDHS
100
100 --ns
/CS 1 set up time
/CS1 hold time /CS1 tCSS
tCHS
150
150 --ns
(VDD = 3.6 to 5.5V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Serial cl oc k cycl e
SCLK high pulse width
SCLK low pulse width
DB6
(SCLK)
tCYC
tWHS
tWLS
200
75
75 --ns
Address setup time
Address hold time RS tASS
tAHS 50
100 --ns
Data setup time
Data hold time DB7
(SID) tDSS
tDHS 50
50 --ns
/CS 1 set up time
/CS1 hold time /CS1 tCSS
tCHS 100
100 --ns
/CS1
(CS2=1)
RS
DB6
(SCLK)
DB7
(SID)
tASS
tCHS
tCSS
0.9VDD 0.1VDD
tWLS tWHS
tDSS tDHS
tCYS
tAHS
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d. Reset input timing
Figure 8-7. Reset input timing
(VDD = 2.4 to 3.6V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Reset low pulse width /RESET tRW 1.0 - - µs
Reset time - tR--1.0
µs
(VDD = 3.6 to 5.5V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
Reset low pulse width /RESET tRW 0.5 - - µs
Reset time - tR--0.5
µs
e. Display control output timing
Figure 8-8. Display control output timing
(VDD = 2.4 to 3.6V, Ta = -40 to +85oC)
Item Signal Symbol Min. Typ. Max. Unit Remark
FR delay time FR tDFR -2080nsC
L = 50 pF
(VDD = 3.6 to 5.5V, Ta = -40 to +85oC)
/RESET
Internal
status
tRW
tR
Durin g r e s e t Re s et c o mp l e te
tDFR
CL
(OUT)
FR
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Item Signal Symbol Min. Typ. Max. Unit Remark
FR delay time FR tDFR -1040nsC
L = 50 pF
9. REFERENCE APPLICATION
9-1. Microprocessor interface
Figure 9-1. Serial Interface (PS = “L”, C68 = “ H or L”, E_/RD = “H or L”, RW_/WR = “H or L”)
Figure 9-2. 6800-series MPU Interface (PS = “H”, C68 = “ H”)
HT0324A
/CS1
CS2
RS
DB7(SID)
DB6(SCLK)
/RESET
DB5 to DB0
C68
PS
Microprocessor
/
CS1
CS2
RS
SID
SCLK
/RESET
Open
VDD or VSS
VSS
HT0324A
/CS1
CS2
RS
E_/RD
RW_/WR
DB7 to DB0
/RESET
C68
PS
6800-series
Microprocessor
/
CS1
CS2
RS
E
RW
DB7 to DB0
/RESET
VDD
VDD
HT0324A
/CS1
CS2
RS
E_/RD
RW_/WR
DB7 to DB0
/RESET
C68
PS
8080-series
Microprocessor
/
CS1
CS2
RS
/RD
/WR
DB7 to DB0
/RESET
VSS
VDD
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Figure 9-3. 8080-series MPU Interface (PS = “H”, C68 = “ L”)
9-2. CONNECTIONS BETWEEN HT0324A AND LCD PANEL
a. Single chip configuration (1/65 duty configurations)
Figure 9-4. SHL = 1, ADC = 0 Figure 9-5. SHL = 1, ADC = 1
Figure 9-6. SHL = 0, ADC = 0 Figure 9-7. SHL = 0, ADC = 1
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
64 x 132 PIXELS
SEG0 …………..……SEG131
COMS
COM0
COM31
COM32
COM63
COMS
HT0324A
(Bottom View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
64 x 132 PIXELS
SEG131 …………………SEG0
COM32
COM63
COMS
COMS
COM0
COM31
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
64 x 132 PIXELS
SEG0 ………………….SEG 13 1
COM31
COM0
COMS
COMS
COM63
COM32
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
64 x 132 PIXELS
SEG131 ………………….SEG0
COMS
COM63
COM32
COM31
COM0
COMS
HT0324A
(Botto m Vie w )
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b. Single chip configuration (1/55 duty configurations)
Figure 9-8. SHL = 1, ADC = 0 Figure 9-9. SHL = 1, ADC = 1
Figure 9-10. SHL = 0, ADC = 0 Figure 9-11. SHL = 0, ADC = 1
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
54 x 132 PIXELS
SEG0 …………..……SEG131
COMS
COM0
COM26
COM37
COM63
COMS
HT0324A
(B ottom Vie w )
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
54 x 132 PIXELS
SEG131 …………………SEG0
COM37
COM63
COMS
COMS
COM0
COM26
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
54 x 132 PIXELS
SEG0 ………………….SEG131
COM26
COM0
COMS
COMS
COM63
COM37
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
54 x 132 PIXELS
SEG131 ………………….SEG0
COMS
COM63
COM37
COM26
COM0
COMS
HT0324A
(Bottom View)
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c. Single chip configuration (1/49 duty configurations)
Figure 9-12. SHL = 1, ADC = 0 Figure 9-13. SHL = 1, ADC = 1
Figure 9-14. SHL = 0, ADC = 0 Figure 9-15. SHL = 0, ADC = 1
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
48 x 132 PIXELS
SEG0 …………..……SEG131
COMS
COM0
COM23
COM40
COM63
COMS
HT0324A
(Bottom V ie w )
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
48 x 132 PIXELS
SEG131 … … ……………SEG0
COM40
COM63
COMS
COMS
COM0
COM23
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
48 x 132 PIXELS
SEG0 ………………….SEG131
COM23
COM0
COMS
COMS
COM63
COM40
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
48 x 132 PIXELS
SEG131 ………………….SEG0
COMS
COM63
COM40
COM23
COM0
COMS
HT0324A
(Bottom View)
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
60
d. Single chip configuration (1/33 duty configurations)
Figure 9-16. SHL = 1, ADC = 0 Figure 9-17. SHL = 1, ADC = 1
Figure 9-18. SHL = 0, ADC = 0 Figure 9-19. SHL = 0, ADC = 1
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
32 x 132 PIXELS
SEG0 …………..……SEG131
COMS
COM0
COM15
COM48
COM63
COMS
HT0324A
(Bottom View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
32 x 132 PIXELS
SEG131 … … ……………SEG0
COM48
COM63
COMS
COMS
COM0
COM15
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
32 x 132 PIXELS
SEG0 ………………….SEG131
COM15
COM0
COMS
COMS
COM63
COM48
HT0324A
(Top View)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→
∞
∞∞
∞ ∃
∃∃
∃ @
32 x 132 PIXELS
SEG131 ………………….SEG0
COMS
COM63
COM48
COM15
COM0
COMS
HT0324A
(Bottom View)
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
61
e. Multiple chip configuration
- 65COM (64COM + 1COMS) x 264SEG (132SEG x 2)
Figure 9-20. SHL = 1, ADC = 1
∗
∗ ∗
∗ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
Figure 9-21. SHL = 0, ADC = 0
SEG131 … … ………SEG0
COM32
COM63
COMS
COMS
COM0
COM31
HT0324A
(Top View )
(Master)
SEG131 … … ………SEG0
COM32
COM63
COMS
COMS
COM0
COM31
HT0324A
(Top View )
(Slave)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→ ∞
∞∞
∞ ∃
∃∃
∃ @
64 x 264 PIXELS
♦
♦♦
♦ ! " # % & '
SEG 0 ……………SEG 131
COM31
COM0
COMS
COMS
COM63
COM32
HT0324A
(Top View)
(Master)
SEG0 … …………SEG 131
COM31
COM0
COMS
COMS
COM63
COM32
HT0324A
(Top View)
(Slave)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→ ∞
∞∞
∞ ∃
∃∃
∃ @
64 x 264 PIXELS
♦
♦♦
♦ ! " # % & '
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
62
∗
∗ ∗
∗ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
- 130COM (128COM + 2COMS) x 132SEG
Figure 9-21. 130COM (128COM + 2COMS) x 132SEG
∗
∗ ∗
∗ Connect the following pins of two chips each other
- Display clock pins: CL, M
- Display control pin: DISP
- LCD power pins: V0, V1, V2, V3, V4
SEG0 … .… …...… …… SEG131
COM31
COM0
COMS
COMS
COM63
COM32
HT0324A
(Top View)
(Master)
SEG131….……………SEG0
COM32
COM63
COMS
COMS
COM0
COM31
HT0324A
(Top View)
(Slave)
∠
∠∠
∠ [
[[
[ ! " # $ →
→→
→ ∞
∞∞
∞ ∃
∃∃
∃ @
128 x 132 PIXELS
♦
♦♦
♦ ! " # % & '
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
63
∗
∗ ∗
∗ Common / Segment output direction select
- Master chip: SHL = 0, ADC = 0
- Slave chip: SHL = 1, ADC = 1
9-3. TCP Pin lay ou t (sample)
M
CL
DISP
/CS1
CS2
/RESET
RS
RW_/WR
E_/RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6, (SCL)
D B7 , (SI)
DSEL0
DSEL1
VDD
VCI
VSS
VOUT
C4+
C3+
C1-
C1+
C2+
C2-
VEXT
REF
V1
V2
V3
V4
V0
VR
MS
CLS
C68
PS
/HPM
INTRS
HT0324A
(Top view)
FR
FRS
COMS
COM63
COM62
:
:
:
COM47
COM46
COM45
:
:
:
COM35
COM34
COM33
COM32
SEG131
SEG130
SEG129
SEG128
:
:
SEG65
SEG64
SEG63
SEG62
:
:
SEG3
SEG2
SEG1
SEG0
COMS
COM0
COM1
COM2
COM3
:
:
COM14
COM15
COM16
:
:
COM28
COM29
COM30
COM31
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
64
Figure 9-22. TCP pin layout
9-4. Application circuit for serial
-. Package type: TCP
-. Device mode: Master mode, Internal OSC, normal mode, 4-times boost-up, internal resistor
MPU
MPU
MPU
MPU
MPU
VDD
VSS
TCP out side
[18 PINS]
/CS1
/RESET
RS
DB6, (SCL)
DB7, (SI)
VDD
VSS
VOUT
C3+
C1-
C1+
C2+
C2-
V1
V2
V3
V4
V0
TCP in side
HT0324A
(Top view )
FRS
FR
NC0
NC1
M
CL
DISP
VSS[2]
/CS1
CS2
VDD
/RESET
RS
VSS
RW_/WR
E_/RD
VDD
DB0
DB1
DB2
DB3
DB4
DB5
DB6 (SCLK)
DB7 (SID)
VSS
VDD
DSEL0
DSEL1
VSS
VDD[5]
VCI[3]
VSS[5]
VOUT[4]
C4+[2]
C3+[2]
C1-[2]
C1+[2]
C2+[2]
C2-[2]
VDD
VEXT[2]
REF
VSS
V1[2]
V2[2]
V3[2]
V4[2]
V0[3]
VR[3]
VSS[2]
VDD
MS
CLS
VSS
C68
PS
VDD
/HPM
VSS
INTRS
VDD
TOMATO LSI Inc.
HT0324A 65COM / 132SEG DRIVER & CONTROLLER FOR STN LCD Ve r 0 .0
65
Figure 9-23. HT0324A Application circuit for serial
