K6T4016C3B-TB70 - Samsung Electronics

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

Document Title

256Kx16 bit Low Power CMOS Static RAM

Revision History

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision No.

0.0

0.1

1.0

2.0

3.0

4.0

4.01

5.0

Remark

Advance

Preliminary

Final

History

Initial draft

Revise

- Die name change ; A to B

Finalize

Revise

- Operating current update and release.

ICC(Read/Write) = 30/60 → 15/75mA

ICC1(Read/Write) = 30/60 → 15/75mA

ICC2 = 160 → 130mA

Revise

- Change datasheet format

- Remove ICC write value from table.

Revise

- Change test load at 55ns: 100pF → 50pF

Errarta correction

Revise

- Add 55ns product for industrial temperature

Draft Data

June 28, 1996

September 19, 1996

December 17, 1996

February 17, 1997

February 17, 1998

June 22, 1998

August 8, 1998

May 22, 2001

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

256Kx16 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6T4016C3B families are fabricated by SAMSUNG′s

advanced CMOS process technology. The families support

various operating temperature ranges and small package

types for user flexibility of system design. The families also

support low data retention voltage for battery back-up opera-

tion with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 256Kx16

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 44-TSOP2-400F/R

PIN DESCRIPTION

Name Function Name Function

CS Chip Select Input Vcc Power

OE Output Enable Input Vss Ground

WE Write Enable Input UB Upper Byte(I/O9~16)

A0~A17 Address Inputs LB Lower Byte (I/O1~8)

I/O1~I/O16 Data Inputs/Outputs NC No Connection

PRODUCT FAMILY

1. The parameter is measured with 50pF test load.

Product Family Operating Temperature Vcc Range Speed Power Dissipation PKG Type

Standby

(ISB1, Max) Operating

(ICC2, Max)

K6T4016C3B-B Commercial(0~70°C) 4.5~5.5V 551)/70ns 20µA130mA 44-TSOP2-400F/R

K6T4016C3B-F Industrial(-40~85°C) 551)/70/100ns 50µA

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

A10

44-TSOP2

Forward 44-TSOP2

Reverse

I/O16

I/O15

I/O14

I/O13

Vss

Vcc

I/O12

I/O11

I/O10

I/O9

A10

A11

A13 A12

A11 A12

I/OI

I/O2

I/O3

I/O4

Vcc

Vss

I/O5

I/O6

I/O7

I/O8

A17

A16

A15

A14

A13

Clk gen.

Row

select

A8 A9 A10 A5 A6 A4A7

A13

A14

A15

A16

A17

I/O1~I/O8

Data

cont

Data

cont

Data

cont

I/O9~I/O16

Vcc

Vss

A12

Precharge circuit.

Memory array

1024 rows

256×16 columns

I/O Circuit

Column select

Control

logic

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

PRODUCT LIST

Commercial Temperature Product(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

K6T4016C3B-TB55

K6T4016C3B-TB70

K6T4016C3B-RB55

K6T4016C3B-RB70

44-TSOP2-F, 55ns, LL-pwr

44-TSOP2-F, 70ns, LL-pwr

44-TSOP2-R, 55ns, LL-pwr

44-TSOP2-R, 70ns, LL-pwr

K6T4016C3B-TF55

K6T4016C3B-TF70

K6T4016C3B-TF10

K6T4016C3B-RF55

K6T4016C3B-RF70

K6T4016C3B-RF10

44-TSOP2-F, 55ns, LL-pwr

44-TSOP2-F, 70ns, LL-pwr

44-TSOP2-F, 100ns, LL-pwr

44-TSOP2-R, 55ns, .LL-pwr

44-TSOP2-R, 70ns, .LL-pwr

44-TSOP2-R, 100ns, LL-pwr

ABSOLUTE MAXIMUM RATINGS1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V-

Voltage on Vcc supply relative to Vss VCC -0.5 to7.0 V-

Power Dissipation PD1.0 W-

Storage temperature TSTG -65 to 150 °C-

Operating Temperature TA0 to 70 °CK6T4016C3B-B

-40 to 85 °CK6T4016C3B-F

Soldering temperature and time TSOLDER 260°C, 10sec(Lead Only) - -

FUNCTIONAL DESCRIPTION

1. X means don′t care. (Must be in low or high state)

CS OE WE LB UB I/O1~8 I/O9~16 Mode Power

HX1) X1) X1) X1) High-Z High-Z Deselected Standby

LH H X1) X1) High-Z High-Z Output Disabled Active

LX1) X1) H H High-Z High-Z Output Disabled Active

L L HLHDout High-Z Lower Byte Read Active

L L H H LHigh-Z Dout Upper Byte Read Active

L L HL L Dout Dout Word Read Active

LX1) L L HDin High-Z Lower Byte Write Active

LX1) LHLHigh-Z Din Upper Byte Write Active

LX1) LLL Din Din Word Write Active

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

RECOMMENDED DC OPERATING CONDITIONS1)

Note:

1. Commercial Product: TA=0 to 70°C, otherwise specified

Industrial Product: TA=-40 to 85°C, otherwise specified

2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns

3. Undershoot: -3.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Min Typ Max Unit

Supply voltage Vcc 4.5 5.0 5.5 V

Ground Vss 000V

Input high voltage VIH 2.2 -Vcc+0.52) V

Input low voltage VIL -0.53) -0.8 V

CAPACITANCE1) (f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V -8pF

Input/Output capacitance CIO VIO=0V -10 pF

DC AND OPERATING CHARACTERISTICS

1. Industrial Product = 50µA

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 -1µA

Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 -1µA

Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 15 mA

Average operating current ICC1 Cycle time=1µs, 100% duty, IIO=0mA

CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V Read - - 15 mA

Write - - 75

ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 130 mA

Output low voltage VOL IOL=2.1mA - - 0.4 V

Output high voltage VOH IOH=-1.0mA 2.4 - - V

Standby Current (TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 3mA

Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 201) µA

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

CL1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS (Test Load and Test Input/Output Reference)

Input pulse level: 0.8 to 2.4V

Input rising and falling time: 5ns

Input and output reference voltage: 1.5V

Output load (See right): CL=100pF+1TTL

CL=50pF+1TTL

AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)

Parameter List Symbol Speed Bins Units

55ns 70ns 100ns

Min Max Min Max Min Max

Read

Read cycle time tRC 55 -70 -100 -ns

Address access time tAA -55 -70 -100 ns

Chip select to output tCO -55 -70 -100 ns

Output enable to valid output tOE -25 -35 -50 ns

Chip select to low-Z output tLZ 10 -10 -10 -ns

Output enable to low-Z output tOLZ 5-5-5-ns

UB, LB enable to low-Z output tBLZ 5-5-5-ns

Chip disable to high-Z output tHZ 020 025 030 ns

Output Disable to High-Z Output tOHZ 020 025 030 ns

UB, LB disable to high-Z output tBHZ 020 025 030 ns

Output hold from address change tOH 10 -10 -10 -ns

LB, UB valid to data output tBA -25 -35 -50 ns

Write

Write cycle time tWC 55 -70 -100 -ns

Chip select to end of write tCW 45 -60 -80 -ns

Address set-up time tAS 0-0-0-ns

Address valid to end of write tAW 45 -60 -80 -ns

Write pulse width tWP 45 -55 -70 -ns

Write recovery time tWR 0-0-0-ns

Write to output high-Z tWHZ 020 025 030 ns

Data to write time overlap tDW 25 -30 -40 -ns

Data hold from write time tDH 0-0-0-ns

End write to output low-Z tOW 5-5-5-ns

LB, UB valid to end of write tBW 45 -60 - - 80 ns

DATA RETENTION CHARACTERISTICS

1. Industrial Product: 20µA

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 -5.5 V

Data retention current IDR Vcc=3.0V - - 151) µA

Data retention set-up time tSDR See data retention waveform 0- - ms

Recovery time tRDR 5- -

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

Address

Data Out Previous Data Valid Data Valid

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

tRC

Address

UB, LB

Data out

tAA

tRC

tOH

tAA

tCO

tBA

tOE

tOLZ

tBLZ

tLZ tOHZ

tBHZ

tHZ

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

tWC

tCW(2)

tAW tBW

tWP(1)

tDH

tDW

tWR(4)

tAS(3)

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

Data Undefined

UB, LB

Data in

Data out

tWC

tCW(2) tWR(4)

tAWtBW

tWP(1)

tAS(3) tDHtDW

tWHZ tOW

High-Z High-Z

Data Valid

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

Address

Data Valid

UB, LB

Data in

Data out High-Z High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS controlled

VCC

4.5V

2.2V

VDR

GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR tRDR

tAS(3)

K6T4016C3B Family CMOS SRAM

Revision 5.0

May 2001

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

Units: millimeter(inch)

0.002

0.05

#22

#44 #23

0.35±0.10

0.014±0.004 0.80

0.0315

MIN.

0.047

1.20MAX.

0.741

18.81MAX.

18.41±0.10

0.725±0.004

11.76±0.20

0.463±0.008

+ 0.10

- 0.05

0.50

+ 0.004

- 0.002

0.15

0.006

0.020

10.16

0.400

0.10

0.004

PACKAGE DIMENSIONS

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00±0.10

0.039±0.004

44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

0.002

0.05

#22

#44 #23

0.35±0.10

0.014±0.004 0.80

0.0315

MIN.

0.047

1.20 MAX.

0.741

18.81MAX.

18.41±0.10

0.725±0.004

11.76±0.20

0.463±0.008

+ 0.10

- 0.05

0.50

+ 0.004

- 0.002

0.15

0.006

0.020

10.16

0.400

0.10

0.004

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.25

( )

0.010

( )

0.805

0.032

( )

MAX

1.00±0.10

0.039±0.004